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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wang Huan550e3dc2014-09-05 13:52:44 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Biwen Li9ebde882019-12-31 15:33:44 +08004 * Copyright 2019 NXP
Wang Huan550e3dc2014-09-05 13:52:44 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Hongbo Zhang32886282016-07-21 18:09:39 +080010#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
11
Gong Qianyu18fb0e32015-10-26 19:47:42 +080012#define CONFIG_SYS_FSL_CLK
Wang Huan550e3dc2014-09-05 13:52:44 +080013
Wang Huan550e3dc2014-09-05 13:52:44 +080014#define CONFIG_SKIP_LOWLEVEL_INIT
Wang Huan550e3dc2014-09-05 13:52:44 +080015
tang yuantian41ba57d2014-12-17 12:58:05 +080016#define CONFIG_DEEP_SLEEP
tang yuantian41ba57d2014-12-17 12:58:05 +080017
Wang Huan550e3dc2014-09-05 13:52:44 +080018/*
19 * Size of malloc() pool
20 */
21#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
22
23#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
24#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
25
Wang Huan550e3dc2014-09-05 13:52:44 +080026#ifndef __ASSEMBLY__
27unsigned long get_board_sys_clk(void);
28unsigned long get_board_ddr_clk(void);
29#endif
30
Alison Wang70097022016-02-02 15:16:23 +080031#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Alison Wangd612f0a2014-12-09 17:38:02 +080032#define CONFIG_SYS_CLK_FREQ 100000000
33#define CONFIG_DDR_CLK_FREQ 100000000
34#define CONFIG_QIXIS_I2C_ACCESS
35#else
Wang Huan550e3dc2014-09-05 13:52:44 +080036#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
37#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Alison Wangd612f0a2014-12-09 17:38:02 +080038#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080039
Alison Wang86949c22014-12-03 15:00:47 +080040#ifdef CONFIG_RAMBOOT_PBL
41#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
42#endif
43
44#ifdef CONFIG_SD_BOOT
Alison Wang70097022016-02-02 15:16:23 +080045#ifdef CONFIG_SD_BOOT_QSPI
46#define CONFIG_SYS_FSL_PBL_RCW \
47 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
48#else
49#define CONFIG_SYS_FSL_PBL_RCW \
50 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
51#endif
Alison Wang86949c22014-12-03 15:00:47 +080052
Alison Wang86949c22014-12-03 15:00:47 +080053#define CONFIG_SPL_MAX_SIZE 0x1a000
54#define CONFIG_SPL_STACK 0x1001d000
55#define CONFIG_SPL_PAD_TO 0x1c000
Alison Wang86949c22014-12-03 15:00:47 +080056
tang yuantian41ba57d2014-12-17 12:58:05 +080057#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
58 CONFIG_SYS_MONITOR_LEN)
Alison Wang86949c22014-12-03 15:00:47 +080059#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
60#define CONFIG_SPL_BSS_START_ADDR 0x80100000
61#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Alison Wang7ee52af2015-10-30 22:45:38 +080062#define CONFIG_SYS_MONITOR_LEN 0xc0000
Alison Wang86949c22014-12-03 15:00:47 +080063#endif
64
Alison Wang8ab967b2014-12-09 17:38:14 +080065#ifdef CONFIG_NAND_BOOT
66#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
Alison Wang8ab967b2014-12-09 17:38:14 +080067
Alison Wang8ab967b2014-12-09 17:38:14 +080068#define CONFIG_SPL_MAX_SIZE 0x1a000
69#define CONFIG_SPL_STACK 0x1001d000
70#define CONFIG_SPL_PAD_TO 0x1c000
Alison Wang8ab967b2014-12-09 17:38:14 +080071
72#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
73#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
74#define CONFIG_SYS_NAND_PAGE_SIZE 2048
75#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
76#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
77
78#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
79#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
80#define CONFIG_SPL_BSS_START_ADDR 0x80100000
81#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
82#define CONFIG_SYS_MONITOR_LEN 0x80000
83#endif
84
Wang Huan550e3dc2014-09-05 13:52:44 +080085#define CONFIG_DDR_SPD
86#define SPD_EEPROM_ADDRESS 0x51
87#define CONFIG_SYS_SPD_BUS_NUM 0
Wang Huan550e3dc2014-09-05 13:52:44 +080088
York Sunc7eae7f2014-09-11 13:32:07 -070089#ifndef CONFIG_SYS_FSL_DDR4
York Sunc7eae7f2014-09-11 13:32:07 -070090#define CONFIG_SYS_DDR_RAW_TIMING
91#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080092#define CONFIG_DIMM_SLOTS_PER_CTLR 1
93#define CONFIG_CHIP_SELECTS_PER_CTRL 4
94
95#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
96#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97
98#define CONFIG_DDR_ECC
99#ifdef CONFIG_DDR_ECC
100#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
101#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
102#endif
103
Wang Huan550e3dc2014-09-05 13:52:44 +0800104/*
105 * IFC Definitions
106 */
Alison Wang70097022016-02-02 15:16:23 +0800107#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huan550e3dc2014-09-05 13:52:44 +0800108#define CONFIG_FSL_IFC
109#define CONFIG_SYS_FLASH_BASE 0x60000000
110#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
111
112#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
113#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
114 CSPR_PORT_SIZE_16 | \
115 CSPR_MSEL_NOR | \
116 CSPR_V)
117#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
118#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
119 + 0x8000000) | \
120 CSPR_PORT_SIZE_16 | \
121 CSPR_MSEL_NOR | \
122 CSPR_V)
123#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
124
125#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
126 CSOR_NOR_TRHZ_80)
127#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
128 FTIM0_NOR_TEADC(0x5) | \
129 FTIM0_NOR_TEAHC(0x5))
130#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
131 FTIM1_NOR_TRAD_NOR(0x1a) | \
132 FTIM1_NOR_TSEQRAD_NOR(0x13))
133#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
134 FTIM2_NOR_TCH(0x4) | \
135 FTIM2_NOR_TWPH(0xe) | \
136 FTIM2_NOR_TWP(0x1c))
137#define CONFIG_SYS_NOR_FTIM3 0
138
Wang Huan550e3dc2014-09-05 13:52:44 +0800139#define CONFIG_SYS_FLASH_QUIET_TEST
140#define CONFIG_FLASH_SHOW_PROGRESS 45
141#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800142#define CONFIG_SYS_WRITE_SWAPPED_DATA
Wang Huan550e3dc2014-09-05 13:52:44 +0800143
144#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
145#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
146#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
147#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
148
149#define CONFIG_SYS_FLASH_EMPTY_INFO
150#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
151 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
152
153/*
154 * NAND Flash Definitions
155 */
156#define CONFIG_NAND_FSL_IFC
157
158#define CONFIG_SYS_NAND_BASE 0x7e800000
159#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
160
161#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
162
163#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
164 | CSPR_PORT_SIZE_8 \
165 | CSPR_MSEL_NAND \
166 | CSPR_V)
167#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
168#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
169 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
170 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
171 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
172 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
173 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
174 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
175
176#define CONFIG_SYS_NAND_ONFI_DETECTION
177
178#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
179 FTIM0_NAND_TWP(0x18) | \
180 FTIM0_NAND_TWCHT(0x7) | \
181 FTIM0_NAND_TWH(0xa))
182#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
183 FTIM1_NAND_TWBE(0x39) | \
184 FTIM1_NAND_TRR(0xe) | \
185 FTIM1_NAND_TRP(0x18))
186#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
187 FTIM2_NAND_TREH(0xa) | \
188 FTIM2_NAND_TWHRE(0x1e))
189#define CONFIG_SYS_NAND_FTIM3 0x0
190
191#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
192#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wang Huan550e3dc2014-09-05 13:52:44 +0800193
194#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Alison Wangd612f0a2014-12-09 17:38:02 +0800195#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800196
197/*
198 * QIXIS Definitions
199 */
200#define CONFIG_FSL_QIXIS
201
202#ifdef CONFIG_FSL_QIXIS
203#define QIXIS_BASE 0x7fb00000
204#define QIXIS_BASE_PHYS QIXIS_BASE
205#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
206#define QIXIS_LBMAP_SWITCH 6
207#define QIXIS_LBMAP_MASK 0x0f
208#define QIXIS_LBMAP_SHIFT 0
209#define QIXIS_LBMAP_DFLTBANK 0x00
210#define QIXIS_LBMAP_ALTBANK 0x04
Hongbo Zhangaeb901f2016-07-21 18:09:38 +0800211#define QIXIS_PWR_CTL 0x21
212#define QIXIS_PWR_CTL_POWEROFF 0x80
Wang Huan550e3dc2014-09-05 13:52:44 +0800213#define QIXIS_RST_CTL_RESET 0x44
214#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
215#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
216#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Hongbo Zhang349cfc92016-08-19 17:20:31 +0800217#define QIXIS_CTL_SYS 0x5
218#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
219#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
220#define QIXIS_RST_FORCE_3 0x45
221#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
222#define QIXIS_PWR_CTL2 0x21
223#define QIXIS_PWR_CTL2_PCTL 0x2
Wang Huan550e3dc2014-09-05 13:52:44 +0800224
225#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
226#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
227 CSPR_PORT_SIZE_8 | \
228 CSPR_MSEL_GPCM | \
229 CSPR_V)
230#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
231#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
232 CSOR_NOR_NOR_MODE_AVD_NOR | \
233 CSOR_NOR_TRHZ_80)
234
235/*
236 * QIXIS Timing parameters for IFC GPCM
237 */
238#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
239 FTIM0_GPCM_TEADC(0xe) | \
240 FTIM0_GPCM_TEAHC(0xe))
241#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
242 FTIM1_GPCM_TRAD(0x1f))
243#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
244 FTIM2_GPCM_TCH(0xe) | \
245 FTIM2_GPCM_TWP(0xf0))
246#define CONFIG_SYS_FPGA_FTIM3 0x0
247#endif
248
Alison Wang8ab967b2014-12-09 17:38:14 +0800249#if defined(CONFIG_NAND_BOOT)
250#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
251#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
252#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
253#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
254#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
255#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
256#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
257#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
258#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
259#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
260#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
261#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
262#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
263#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
264#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
265#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
266#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
267#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
268#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
269#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
270#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
271#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
272#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
273#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
274#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
275#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
276#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
277#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
278#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
279#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
280#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
281#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
282#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800283#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
284#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
285#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
286#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
287#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
288#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
289#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
290#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
291#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
292#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
293#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
294#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
295#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
296#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
297#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
298#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
299#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
300#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
301#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
302#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
303#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
304#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
305#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
306#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
307#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
308#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
309#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
310#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
311#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
312#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
313#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
314#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
Alison Wang8ab967b2014-12-09 17:38:14 +0800315#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800316
317/*
318 * Serial Port
319 */
Alison Wang8fc21212015-01-04 15:30:58 +0800320#ifdef CONFIG_LPUART
Alison Wang8fc21212015-01-04 15:30:58 +0800321#define CONFIG_LPUART_32B_REG
322#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800323#define CONFIG_SYS_NS16550_SERIAL
York Sund83b47b2016-02-08 13:04:17 -0800324#ifndef CONFIG_DM_SERIAL
Wang Huan550e3dc2014-09-05 13:52:44 +0800325#define CONFIG_SYS_NS16550_REG_SIZE 1
York Sund83b47b2016-02-08 13:04:17 -0800326#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800327#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang8fc21212015-01-04 15:30:58 +0800328#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800329
Wang Huan550e3dc2014-09-05 13:52:44 +0800330/*
331 * I2C
332 */
Biwen Li9ebde882019-12-31 15:33:44 +0800333#ifndef CONFIG_DM_I2C
Wang Huan550e3dc2014-09-05 13:52:44 +0800334#define CONFIG_SYS_I2C
Biwen Li9ebde882019-12-31 15:33:44 +0800335#else
336#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
337#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
338#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800339#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200340#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
341#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700342#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800343
Jagdish Gediya73dc91f2018-05-10 04:04:29 +0530344/* EEPROM */
345#define CONFIG_ID_EEPROM
346#define CONFIG_SYS_I2C_EEPROM_NXID
347#define CONFIG_SYS_EEPROM_BUS_NUM 0
348#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
349#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
350#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
351#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
352
Wang Huan550e3dc2014-09-05 13:52:44 +0800353/*
354 * I2C bus multiplexer
355 */
356#define I2C_MUX_PCA_ADDR_PRI 0x77
357#define I2C_MUX_CH_DEFAULT 0x8
Xiubo Lidd048322014-12-16 14:50:33 +0800358#define I2C_MUX_CH_CH7301 0xC
Wang Huan550e3dc2014-09-05 13:52:44 +0800359
360/*
361 * MMC
362 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800363
364/*
Xiubo Lidd048322014-12-16 14:50:33 +0800365 * Video
366 */
Sanchayan Maityb215fb32017-04-11 11:12:09 +0530367#ifdef CONFIG_VIDEO_FSL_DCU_FB
Xiubo Lidd048322014-12-16 14:50:33 +0800368#define CONFIG_VIDEO_LOGO
369#define CONFIG_VIDEO_BMP_LOGO
370
371#define CONFIG_FSL_DIU_CH7301
372#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
373#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
374#define CONFIG_SYS_I2C_DVI_ADDR 0x75
375#endif
376
377/*
Wang Huan550e3dc2014-09-05 13:52:44 +0800378 * eTSEC
379 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800380
381#ifdef CONFIG_TSEC_ENET
Wang Huan550e3dc2014-09-05 13:52:44 +0800382#define CONFIG_MII_DEFAULT_TSEC 3
383#define CONFIG_TSEC1 1
384#define CONFIG_TSEC1_NAME "eTSEC1"
385#define CONFIG_TSEC2 1
386#define CONFIG_TSEC2_NAME "eTSEC2"
387#define CONFIG_TSEC3 1
388#define CONFIG_TSEC3_NAME "eTSEC3"
389
390#define TSEC1_PHY_ADDR 1
391#define TSEC2_PHY_ADDR 2
392#define TSEC3_PHY_ADDR 3
393
394#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
395#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
396#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
397
398#define TSEC1_PHYIDX 0
399#define TSEC2_PHYIDX 0
400#define TSEC3_PHYIDX 0
401
402#define CONFIG_ETHPRIME "eTSEC1"
403
Wang Huan550e3dc2014-09-05 13:52:44 +0800404#define CONFIG_HAS_ETH0
405#define CONFIG_HAS_ETH1
406#define CONFIG_HAS_ETH2
407
408#define CONFIG_FSL_SGMII_RISER 1
409#define SGMII_RISER_PHY_OFFSET 0x1b
410
411#ifdef CONFIG_FSL_SGMII_RISER
412#define CONFIG_SYS_TBIPA_VALUE 8
413#endif
414
415#endif
Minghuan Lianda419022014-10-31 13:43:44 +0800416
417/* PCIe */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400418#define CONFIG_PCIE1 /* PCIE controller 1 */
419#define CONFIG_PCIE2 /* PCIE controller 2 */
Minghuan Lianda419022014-10-31 13:43:44 +0800420
Minghuan Lian180b8682015-01-21 17:29:19 +0800421#ifdef CONFIG_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800422#define CONFIG_PCI_SCAN_SHOW
Minghuan Lian180b8682015-01-21 17:29:19 +0800423#endif
424
Wang Huan550e3dc2014-09-05 13:52:44 +0800425#define CONFIG_CMDLINE_TAG
Alison Wang86949c22014-12-03 15:00:47 +0800426
Xiubo Li1a2826f2014-11-21 17:40:57 +0800427#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu435acd82015-10-26 19:47:41 +0800428#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800429#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Andre Przywarae4916e82017-02-16 01:20:19 +0000430#define COUNTER_FREQUENCY 12500000
Xiubo Li1a2826f2014-11-21 17:40:57 +0800431
Wang Huan550e3dc2014-09-05 13:52:44 +0800432#define CONFIG_HWCONFIG
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800433#define HWCONFIG_BUFFER_SIZE 256
434
435#define CONFIG_FSL_DEVICE_DISABLE
Wang Huan550e3dc2014-09-05 13:52:44 +0800436
Wang Huan550e3dc2014-09-05 13:52:44 +0800437
Alison Wang615bfce2017-05-16 10:45:57 +0800438#define CONFIG_SYS_QE_FW_ADDR 0x60940000
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800439
Alison Wang8fc21212015-01-04 15:30:58 +0800440#ifdef CONFIG_LPUART
441#define CONFIG_EXTRA_ENV_SETTINGS \
442 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
Alison Wang99fe4542015-11-05 11:16:26 +0800443 "initrd_high=0xffffffff\0" \
Alison Wang8fc21212015-01-04 15:30:58 +0800444 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
445#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800446#define CONFIG_EXTRA_ENV_SETTINGS \
447 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wang99fe4542015-11-05 11:16:26 +0800448 "initrd_high=0xffffffff\0" \
Wang Huan550e3dc2014-09-05 13:52:44 +0800449 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
Alison Wang8fc21212015-01-04 15:30:58 +0800450#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800451
452/*
453 * Miscellaneous configurable options
454 */
Alison Wangc463eeb2020-02-03 15:25:19 +0800455#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wang Huan550e3dc2014-09-05 13:52:44 +0800456
Wang Huan550e3dc2014-09-05 13:52:44 +0800457#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huan550e3dc2014-09-05 13:52:44 +0800458
Xiubo Li660673a2014-11-21 17:40:59 +0800459#define CONFIG_LS102XA_STREAM_ID
460
Wang Huan550e3dc2014-09-05 13:52:44 +0800461#define CONFIG_SYS_INIT_SP_OFFSET \
462 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
463#define CONFIG_SYS_INIT_SP_ADDR \
464 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
465
Alison Wang86949c22014-12-03 15:00:47 +0800466#ifdef CONFIG_SPL_BUILD
467#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
468#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800469#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang86949c22014-12-03 15:00:47 +0800470#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800471
472/*
473 * Environment
474 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800475
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530476#include <asm/fsl_secure_boot.h>
Alison Wangcc7b8b92016-01-15 15:29:32 +0800477#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530478
Wang Huan550e3dc2014-09-05 13:52:44 +0800479#endif