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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2002
3 * Gary Jennejohn <gj@denx.de>
4 *
5 * Configuation settings for the TRAB board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * If we are developing, we might want to start armboot from ram
31 * so we MUST NOT initialize critical regs like mem-timing ...
32 */
33#define CONFIG_INIT_CRITICAL /* undef for developing */
34
35/*
36 * High Level Configuration Options
37 * (easy to change)
38 */
39#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
40#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
41#define CONFIG_TRAB 1 /* on a TRAB Board */
42#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
43
44/* input clock of PLL */
wdenk7f6c2cb2002-11-10 22:06:23 +000045#define CONFIG_SYS_CLK_FREQ 12000000 /* TRAB has 12 MHz input clock */
wdenkc6097192002-11-03 00:24:07 +000046
47#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
48
49#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
50#define CONFIG_SETUP_MEMORY_TAGS 1
51#define CONFIG_INITRD_TAG 1
52
53/*
54 * Size of malloc() pool
55 */
wdenk699b13a2002-11-03 18:03:52 +000056#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenkc6097192002-11-03 00:24:07 +000057
58/*
59 * Hardware drivers
60 */
61#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
62#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */
63#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
64
65#define CONFIG_VFD 1 /* VFD linear frame buffer driver */
66#define VFD_TEST_LOGO 1 /* output a test logo to the VFDs */
67
68/*
69 * select serial console configuration
70 */
71#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */
72
73#define CONFIG_HWFLOW /* include RTS/CTS flow control support */
74
75#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
76
77#define CONFIG_MODEM_KEY_MAGIC "23" /* hold down these keys to enable modem */
78
79/*
80 * The following enables modem debugging stuff. The dbg() and
81 * 'char screen[1024]' are used for debug printfs. Unfortunately,
82 * it is usable only from BDI
83 */
84#undef CONFIG_MODEM_SUPPORT_DEBUG
85
86/* allow to overwrite serial and ethaddr */
87#define CONFIG_ENV_OVERWRITE
88
89#define CONFIG_BAUDRATE 115200
90
91#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
92
93#ifdef CONFIG_HWFLOW
94#define CONFIG_COMMANDS_ADD_HWFLOW CFG_CMD_HWFLOW
95#else
96#define CONFIG_COMMANDS_ADD_HWFLOW 0
97#endif
98
99#ifdef CONFIG_VFD
100#define CONFIG_COMMANDS_ADD_VFD CFG_CMD_VFD
101#else
102#define CONFIG_COMMANDS_ADD_VFD 0
103#endif
104
105#ifndef USE_920T_MMU
106#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
107 CFG_CMD_BSP | \
108 CONFIG_COMMANDS_ADD_HWFLOW | \
109 CONFIG_COMMANDS_ADD_VFD )
110#else
111#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
112 CFG_CMD_BSP | \
113 CONFIG_COMMANDS_ADD_HWFLOW | \
114 CONFIG_COMMANDS_ADD_VFD )
115#endif
116
117/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
118#include <cmd_confdefs.h>
119
120
121#define CONFIG_BOOTDELAY 5
122#define CONFIG_PREBOOT "echo;echo *** booting ***;echo"
123#define CONFIG_BOOTARGS "console=ttyS0"
124#define CONFIG_ETHADDR 00:D0:93:00:61:11
125#define CONFIG_NETMASK 255.255.255.0
126#define CONFIG_IPADDR 192.168.3.27
127#define CONFIG_SERVERIP 192.168.3.1
128#define CONFIG_BOOTCOMMAND "run flash_nfs"
129#define CONFIG_EXTRA_ENV_SETTINGS \
130 "nfs_args=setenv bootargs root=/dev/nfs rw " \
131 "nfsroot=$(serverip):$(rootpath)\0" \
132 "rootpath=/opt/eldk/arm_920TDI\0" \
133 "ram_args=setenv bootargs root=/dev/ram rw\0" \
134 "add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
135 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
136 "add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \
137 "load=tftp 0xC100000 /tftpboot/TRAB/u-boot.bin\0" \
wdenke95b61c2002-11-04 16:02:40 +0000138 "update=protect off 1:0-8;era 1:0-8;cp.b 0xc100000 0 $(filesize);" \
wdenkc6097192002-11-03 00:24:07 +0000139 "setenv filesize;saveenv\0" \
140 "loadfile=/tftpboot/TRAB/pImage\0" \
141 "loadaddr=c400000\0" \
142 "net_load=tftpboot $(loadaddr) $(loadfile)\0" \
143 "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
144 "kernel_addr=00040000\0" \
145 "flash_nfs=run nfs_args add_net add_misc;bootm $(kernel_addr)\0" \
146 "mdm_init1=ATZ\0" \
147 "mdm_init2=ATS0=1\0" \
148 "mdm_flow_control=rts/cts\0"
149
150#if 0 /* disabled for development */
151#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
152#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
153#define CONFIG_AUTOBOOT_DELAY_STR "system" /* 1st password */
154#endif
155
156#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
157#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
158/* what's this ? it's not used anywhere */
159#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
160#endif
161
162/*
163 * Miscellaneous configurable options
164 */
165#define CFG_LONGHELP /* undef to save memory */
166#define CFG_PROMPT "TRAB # " /* Monitor Command Prompt */
167#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
168#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
169#define CFG_MAXARGS 16 /* max number of command args */
170#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
171
172#define CFG_MEMTEST_START 0x0c000000 /* memtest works on */
173#define CFG_MEMTEST_END 0x0d000000 /* 16 MB in DRAM */
174
175#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
176
177#define CFG_LOAD_ADDR 0x0cf00000 /* default load address */
178
179#ifdef CONFIG_TRAB_50MHZ
180/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
181/* it to wrap 100 times (total 1562500) to get 1 sec. */
182/* this should _really_ be calculated !! */
183#define CFG_HZ 1562500
184#else
185/* the PWM TImer 4 uses a counter of 10390 for 10 ms, so we need */
186/* it to wrap 100 times (total 1039000) to get 1 sec. */
187/* this should _really_ be calculated !! */
188#define CFG_HZ 1039000
189#endif
190
191/* valid baudrates */
192#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
193
194#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
195
196/*-----------------------------------------------------------------------
197 * Stack sizes
198 *
199 * The stack sizes are set up in start.S using the settings below
200 */
201#define CONFIG_STACKSIZE (128*1024) /* regular stack */
202#ifdef CONFIG_USE_IRQ
203#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
204#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
205#endif
206
207/*-----------------------------------------------------------------------
208 * Physical Memory Map
209 */
210#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
211#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
212#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
213
214#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
215#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
216
217/* The following #defines are needed to get flash environment right */
218#define CFG_MONITOR_BASE PHYS_FLASH_1
219#define CFG_MONITOR_LEN (256 << 10)
220
221#define CFG_FLASH_BASE PHYS_FLASH_1
222
223/*-----------------------------------------------------------------------
224 * FLASH and environment organization
225 */
226#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
227#define CFG_MAX_FLASH_SECT (71) /* max number of sectors on one chip */
228
229/* timeout values are in ticks */
230#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
231#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
232
233#define CFG_ENV_IS_IN_FLASH 1
234
235/* Address and size of Primary Environment Sector */
236#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
237#define CFG_ENV_SIZE 0x4000
238
239/* Address and size of Redundant Environment Sector */
240#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
241#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
242
243#endif /* __CONFIG_H */