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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk1cb8e982003-03-06 21:55:29 +00002/*
3 * (C) Copyright 2002
4 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
wdenk1cb8e982003-03-06 21:55:29 +00005 */
6
wdenk1cb8e982003-03-06 21:55:29 +00007#include <common.h>
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +01008#include <errno.h>
9#include <dm.h>
Rajeshwari Shindea9d2ae72012-12-26 20:03:12 +000010#include <fdtdec.h>
Piotr Wilczekc86d9ed2012-11-20 02:19:05 +000011#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000013#include <asm/arch/clk.h>
14#include <asm/arch/cpu.h>
Rajeshwari Shindea9d2ae72012-12-26 20:03:12 +000015#include <asm/arch/pinmux.h>
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000016#else
kevin.morfitt@fearnside-systems.co.ukac678042009-11-17 18:30:34 +090017#include <asm/arch/s3c24x0_cpu.h>
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000018#endif
kevin.morfitt@fearnside-systems.co.ukeb0ae7f2009-10-10 13:33:11 +090019#include <asm/io.h>
wdenk1cb8e982003-03-06 21:55:29 +000020#include <i2c.h>
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000021#include "s3c24x0_i2c.h"
wdenk1cb8e982003-03-06 21:55:29 +000022
Jaehoon Chunga2987122017-01-09 14:47:51 +090023#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
24#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
25#else
26#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
27#endif
28
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +010029DECLARE_GLOBAL_DATA_PTR;
30
Naveen Krishna Che4e24022013-10-15 16:01:43 +053031/*
32 * Wait til the byte transfer is completed.
33 *
34 * @param i2c- pointer to the appropriate i2c register bank.
35 * @return I2C_OK, if transmission was ACKED
36 * I2C_NACK, if transmission was NACKED
37 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
38 */
39
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000040static int WaitForXfer(struct s3c24x0_i2c *i2c)
wdenk1cb8e982003-03-06 21:55:29 +000041{
Naveen Krishna Che4e24022013-10-15 16:01:43 +053042 ulong start_time = get_timer(0);
wdenk1cb8e982003-03-06 21:55:29 +000043
Naveen Krishna Che4e24022013-10-15 16:01:43 +053044 do {
45 if (readl(&i2c->iiccon) & I2CCON_IRPND)
46 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
47 I2C_NACK : I2C_OK;
48 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
wdenk1cb8e982003-03-06 21:55:29 +000049
Naveen Krishna Che4e24022013-10-15 16:01:43 +053050 return I2C_NOK_TOUT;
wdenk1cb8e982003-03-06 21:55:29 +000051}
52
Simon Glass26ea7682015-07-02 18:15:46 -060053static void read_write_byte(struct s3c24x0_i2c *i2c)
wdenk1cb8e982003-03-06 21:55:29 +000054{
Simon Glass26ea7682015-07-02 18:15:46 -060055 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
wdenk1cb8e982003-03-06 21:55:29 +000056}
57
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000058static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
59{
60 ulong freq, pres = 16, div;
Piotr Wilczekc86d9ed2012-11-20 02:19:05 +000061#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000062 freq = get_i2c_clk();
63#else
64 freq = get_PCLK();
65#endif
66 /* calculate prescaler and divisor values */
67 if ((freq / pres / (16 + 1)) > speed)
68 /* set prescaler to 512 */
69 pres = 512;
70
71 div = 0;
72 while ((freq / pres / (div + 1)) > speed)
73 div++;
74
75 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
76 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
77
78 /* init to SLAVE REVEIVE and set slaveaddr */
79 writel(0, &i2c->iicstat);
80 writel(slaveadd, &i2c->iicadd);
81 /* program Master Transmit (and implicit STOP) */
82 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
83}
84
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +010085static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010086{
Simon Glass9a1bff62016-11-23 06:34:42 -070087 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010088
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010089 i2c_bus->clock_frequency = speed;
90
Simon Glass37b8eb32016-11-23 06:34:43 -070091 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
Jaehoon Chunga2987122017-01-09 14:47:51 +090092 SYS_I2C_S3C24X0_SLAVE_ADDR);
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010093
94 return 0;
95}
96
Naveen Krishna Ch296a4612013-10-15 16:02:44 +053097/*
wdenkfc3e2162003-10-08 22:33:00 +000098 * cmd_type is 0 for write, 1 for read.
99 *
100 * addr_len can take any value from 0-255, it is only limited
101 * by the char, we could make it larger if needed. If it is
102 * 0 we skip the address write cycle.
103 */
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000104static int i2c_transfer(struct s3c24x0_i2c *i2c,
105 unsigned char cmd_type,
106 unsigned char chip,
107 unsigned char addr[],
108 unsigned char addr_len,
109 unsigned char data[],
110 unsigned short data_len)
wdenk1cb8e982003-03-06 21:55:29 +0000111{
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530112 int i = 0, result;
113 ulong start_time = get_timer(0);
wdenk1cb8e982003-03-06 21:55:29 +0000114
wdenkfc3e2162003-10-08 22:33:00 +0000115 if (data == 0 || data_len == 0) {
116 /*Don't support data transfer of no length or to address 0 */
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000117 debug("i2c_transfer: bad call\n");
wdenkfc3e2162003-10-08 22:33:00 +0000118 return I2C_NOK;
119 }
wdenk1cb8e982003-03-06 21:55:29 +0000120
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530121 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
122 if (get_timer(start_time) > I2C_TIMEOUT_MS)
123 return I2C_NOK_TOUT;
wdenkfc3e2162003-10-08 22:33:00 +0000124 }
wdenk1cb8e982003-03-06 21:55:29 +0000125
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000126 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530127
128 /* Get the slave chip address going */
129 writel(chip, &i2c->iicds);
130 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
131 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
132 &i2c->iicstat);
133 else
134 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
135 &i2c->iicstat);
136
137 /* Wait for chip address to transmit. */
138 result = WaitForXfer(i2c);
139 if (result != I2C_OK)
140 goto bailout;
141
142 /* If register address needs to be transmitted - do it now. */
143 if (addr && addr_len) {
144 while ((i < addr_len) && (result == I2C_OK)) {
145 writel(addr[i++], &i2c->iicds);
Simon Glass26ea7682015-07-02 18:15:46 -0600146 read_write_byte(i2c);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530147 result = WaitForXfer(i2c);
148 }
149 i = 0;
150 if (result != I2C_OK)
151 goto bailout;
152 }
wdenk1cb8e982003-03-06 21:55:29 +0000153
wdenkfc3e2162003-10-08 22:33:00 +0000154 switch (cmd_type) {
wdenk48b42612003-06-19 23:01:32 +0000155 case I2C_WRITE:
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530156 while ((i < data_len) && (result == I2C_OK)) {
157 writel(data[i++], &i2c->iicds);
Simon Glass26ea7682015-07-02 18:15:46 -0600158 read_write_byte(i2c);
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000159 result = WaitForXfer(i2c);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530160 }
wdenkfc3e2162003-10-08 22:33:00 +0000161 break;
wdenk1cb8e982003-03-06 21:55:29 +0000162
wdenk48b42612003-06-19 23:01:32 +0000163 case I2C_READ:
wdenkfc3e2162003-10-08 22:33:00 +0000164 if (addr && addr_len) {
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530165 /*
166 * Register address has been sent, now send slave chip
167 * address again to start the actual read transaction.
168 */
C Naumand9abba82010-10-26 23:04:31 +0900169 writel(chip, &i2c->iicds);
wdenk1cb8e982003-03-06 21:55:29 +0000170
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530171 /* Generate a re-START. */
Rajeshwari Shindecb466c02013-02-19 02:19:45 +0000172 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
173 &i2c->iicstat);
Simon Glass26ea7682015-07-02 18:15:46 -0600174 read_write_byte(i2c);
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000175 result = WaitForXfer(i2c);
wdenkfc3e2162003-10-08 22:33:00 +0000176
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530177 if (result != I2C_OK)
178 goto bailout;
wdenk1cb8e982003-03-06 21:55:29 +0000179 }
180
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530181 while ((i < data_len) && (result == I2C_OK)) {
182 /* disable ACK for final READ */
183 if (i == data_len - 1)
184 writel(readl(&i2c->iiccon)
185 & ~I2CCON_ACKGEN,
186 &i2c->iiccon);
Simon Glass26ea7682015-07-02 18:15:46 -0600187 read_write_byte(i2c);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530188 result = WaitForXfer(i2c);
189 data[i++] = readl(&i2c->iicds);
190 }
191 if (result == I2C_NACK)
192 result = I2C_OK; /* Normal terminated read. */
wdenkfc3e2162003-10-08 22:33:00 +0000193 break;
wdenk1cb8e982003-03-06 21:55:29 +0000194
195 default:
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000196 debug("i2c_transfer: bad call\n");
wdenkfc3e2162003-10-08 22:33:00 +0000197 result = I2C_NOK;
198 break;
199 }
wdenk1cb8e982003-03-06 21:55:29 +0000200
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530201bailout:
202 /* Send STOP. */
203 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
Simon Glass26ea7682015-07-02 18:15:46 -0600204 read_write_byte(i2c);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530205
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000206 return result;
wdenk1cb8e982003-03-06 21:55:29 +0000207}
208
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100209static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
wdenk1cb8e982003-03-06 21:55:29 +0000210{
Simon Glass9a1bff62016-11-23 06:34:42 -0700211 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
wdenkfc3e2162003-10-08 22:33:00 +0000212 uchar buf[1];
Naveen Krishna Ch296a4612013-10-15 16:02:44 +0530213 int ret;
wdenk1cb8e982003-03-06 21:55:29 +0000214
wdenkfc3e2162003-10-08 22:33:00 +0000215 buf[0] = 0;
wdenk1cb8e982003-03-06 21:55:29 +0000216
wdenkfc3e2162003-10-08 22:33:00 +0000217 /*
218 * What is needed is to send the chip address and verify that the
219 * address was <ACK>ed (i.e. there was a chip at that address which
220 * drove the data line low).
221 */
Simon Glass37b8eb32016-11-23 06:34:43 -0700222 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
Naveen Krishna Ch296a4612013-10-15 16:02:44 +0530223
Naveen Krishna Ch296a4612013-10-15 16:02:44 +0530224 return ret != I2C_OK;
wdenk1cb8e982003-03-06 21:55:29 +0000225}
226
Simon Glass45d9ae82015-07-02 18:15:47 -0600227static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
228 int seq)
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100229{
Simon Glass45d9ae82015-07-02 18:15:47 -0600230 struct s3c24x0_i2c *i2c = i2c_bus->regs;
231 bool is_read = msg->flags & I2C_M_RD;
232 uint status;
233 uint addr;
234 int ret, i;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100235
Simon Glass45d9ae82015-07-02 18:15:47 -0600236 if (!seq)
237 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
238
239 /* Get the slave chip address going */
240 addr = msg->addr << 1;
241 writel(addr, &i2c->iicds);
242 status = I2C_TXRX_ENA | I2C_START_STOP;
243 if (is_read)
244 status |= I2C_MODE_MR;
245 else
246 status |= I2C_MODE_MT;
247 writel(status, &i2c->iicstat);
248 if (seq)
249 read_write_byte(i2c);
250
251 /* Wait for chip address to transmit */
252 ret = WaitForXfer(i2c);
253 if (ret)
254 goto err;
255
256 if (is_read) {
257 for (i = 0; !ret && i < msg->len; i++) {
258 /* disable ACK for final READ */
259 if (i == msg->len - 1)
260 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
261 read_write_byte(i2c);
262 ret = WaitForXfer(i2c);
263 msg->buf[i] = readl(&i2c->iicds);
264 }
265 if (ret == I2C_NACK)
266 ret = I2C_OK; /* Normal terminated read */
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100267 } else {
Simon Glass45d9ae82015-07-02 18:15:47 -0600268 for (i = 0; !ret && i < msg->len; i++) {
269 writel(msg->buf[i], &i2c->iicds);
270 read_write_byte(i2c);
271 ret = WaitForXfer(i2c);
272 }
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100273 }
274
Simon Glass45d9ae82015-07-02 18:15:47 -0600275err:
276 return ret;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100277}
278
279static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
280 int nmsgs)
281{
282 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Simon Glass45d9ae82015-07-02 18:15:47 -0600283 struct s3c24x0_i2c *i2c = i2c_bus->regs;
284 ulong start_time;
285 int ret, i;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100286
Simon Glass45d9ae82015-07-02 18:15:47 -0600287 start_time = get_timer(0);
288 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
289 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
290 debug("Timeout\n");
291 return -ETIMEDOUT;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100292 }
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100293 }
294
Simon Glass45d9ae82015-07-02 18:15:47 -0600295 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
296 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
297
298 /* Send STOP */
299 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
300 read_write_byte(i2c);
301
302 return ret ? -EREMOTEIO : 0;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100303}
304
Simon Glassd1998a92020-12-03 16:55:21 -0700305static int s3c_i2c_of_to_plat(struct udevice *dev)
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100306{
307 const void *blob = gd->fdt_blob;
308 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Simon Glass37b8eb32016-11-23 06:34:43 -0700309 int node;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100310
Simon Glasse160f7d2017-01-17 16:52:55 -0700311 node = dev_of_offset(dev);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100312
Masahiro Yamada8613c8d2020-07-17 14:36:46 +0900313 i2c_bus->regs = dev_read_addr_ptr(dev);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100314
315 i2c_bus->id = pinmux_decode_periph_id(blob, node);
316
Simon Glassf3d46152020-01-23 11:48:22 -0700317 i2c_bus->clock_frequency =
318 dev_read_u32_default(dev, "clock-frequency",
319 I2C_SPEED_STANDARD_RATE);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100320 i2c_bus->node = node;
Simon Glass8b85dfc2020-12-16 21:20:07 -0700321 i2c_bus->bus_num = dev_seq(dev);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100322
Simon Glass37b8eb32016-11-23 06:34:43 -0700323 exynos_pinmux_config(i2c_bus->id, 0);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100324
325 i2c_bus->active = true;
326
327 return 0;
328}
329
330static const struct dm_i2c_ops s3c_i2c_ops = {
331 .xfer = s3c24x0_i2c_xfer,
332 .probe_chip = s3c24x0_i2c_probe,
333 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
334};
335
336static const struct udevice_id s3c_i2c_ids[] = {
Simon Glass37b8eb32016-11-23 06:34:43 -0700337 { .compatible = "samsung,s3c2440-i2c" },
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100338 { }
339};
340
341U_BOOT_DRIVER(i2c_s3c) = {
342 .name = "i2c_s3c",
343 .id = UCLASS_I2C,
344 .of_match = s3c_i2c_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700345 .of_to_plat = s3c_i2c_of_to_plat,
Simon Glass41575d82020-12-03 16:55:17 -0700346 .priv_auto = sizeof(struct s3c24x0_i2c_bus),
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100347 .ops = &s3c_i2c_ops,
348};