Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 2 | /* |
Jerry Huang | d621da0 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 3 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
Yangbo Lu | 9abf648 | 2020-05-19 11:06:43 +0800 | [diff] [blame] | 4 | * Copyright 2019-2020 NXP |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 5 | * Andy Fleming |
| 6 | * |
| 7 | * Based vaguely on the pxa mmc code: |
| 8 | * (C) Copyright 2003 |
| 9 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <config.h> |
| 13 | #include <common.h> |
| 14 | #include <command.h> |
Simon Glass | 1eb69ae | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 15 | #include <cpu_func.h> |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 16 | #include <errno.h> |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 17 | #include <hwconfig.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 18 | #include <mmc.h> |
| 19 | #include <part.h> |
| 20 | #include <malloc.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 21 | #include <fsl_esdhc.h> |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 22 | #include <fdt_support.h> |
Simon Glass | 90526e9 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 23 | #include <asm/cache.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 24 | #include <asm/io.h> |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 25 | #include <dm.h> |
Simon Glass | 336d461 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 26 | #include <dm/device_compat.h> |
Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 27 | #include <linux/bitops.h> |
Simon Glass | c05ed00 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 28 | #include <linux/delay.h> |
Michael Walle | b1ba146 | 2020-09-23 12:42:48 +0200 | [diff] [blame] | 29 | #include <linux/dma-mapping.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 30 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 31 | DECLARE_GLOBAL_DATA_PTR; |
| 32 | |
| 33 | struct fsl_esdhc { |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 34 | uint dsaddr; /* SDMA system address register */ |
| 35 | uint blkattr; /* Block attributes register */ |
| 36 | uint cmdarg; /* Command argument register */ |
| 37 | uint xfertyp; /* Transfer type register */ |
| 38 | uint cmdrsp0; /* Command response 0 register */ |
| 39 | uint cmdrsp1; /* Command response 1 register */ |
| 40 | uint cmdrsp2; /* Command response 2 register */ |
| 41 | uint cmdrsp3; /* Command response 3 register */ |
| 42 | uint datport; /* Buffer data port register */ |
| 43 | uint prsstat; /* Present state register */ |
| 44 | uint proctl; /* Protocol control register */ |
| 45 | uint sysctl; /* System Control Register */ |
| 46 | uint irqstat; /* Interrupt status register */ |
| 47 | uint irqstaten; /* Interrupt status enable register */ |
| 48 | uint irqsigen; /* Interrupt signal enable register */ |
| 49 | uint autoc12err; /* Auto CMD error status register */ |
| 50 | uint hostcapblt; /* Host controller capabilities register */ |
| 51 | uint wml; /* Watermark level register */ |
Yangbo Lu | 4d8ff42 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 52 | char reserved1[8]; /* reserved */ |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 53 | uint fevt; /* Force event register */ |
| 54 | uint admaes; /* ADMA error status register */ |
| 55 | uint adsaddr; /* ADMA system address register */ |
Yangbo Lu | 4d8ff42 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 56 | char reserved2[160]; |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 57 | uint hostver; /* Host controller version register */ |
Yangbo Lu | 4d8ff42 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 58 | char reserved3[4]; /* reserved */ |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame] | 59 | uint dmaerraddr; /* DMA error address register */ |
Yangbo Lu | 4d8ff42 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 60 | char reserved4[4]; /* reserved */ |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame] | 61 | uint dmaerrattr; /* DMA error attribute register */ |
Yangbo Lu | 4d8ff42 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 62 | char reserved5[4]; /* reserved */ |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 63 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 64 | char reserved6[8]; /* reserved */ |
| 65 | uint tbctl; /* Tuning block control register */ |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 66 | char reserved7[32]; /* reserved */ |
| 67 | uint sdclkctl; /* SD clock control register */ |
| 68 | uint sdtimingctl; /* SD timing control register */ |
| 69 | char reserved8[20]; /* reserved */ |
| 70 | uint dllcfg0; /* DLL config 0 register */ |
| 71 | char reserved9[680]; /* reserved */ |
Yangbo Lu | 4d8ff42 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 72 | uint esdhcctl; /* eSDHC control register */ |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 73 | }; |
| 74 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 75 | struct fsl_esdhc_plat { |
| 76 | struct mmc_config cfg; |
| 77 | struct mmc mmc; |
| 78 | }; |
| 79 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 80 | /** |
| 81 | * struct fsl_esdhc_priv |
| 82 | * |
| 83 | * @esdhc_regs: registers of the sdhc controller |
| 84 | * @sdhc_clk: Current clk of the sdhc controller |
| 85 | * @bus_width: bus width, 1bit, 4bit or 8bit |
| 86 | * @cfg: mmc config |
| 87 | * @mmc: mmc |
| 88 | * Following is used when Driver Model is enabled for MMC |
| 89 | * @dev: pointer for the device |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 90 | * @cd_gpio: gpio for card detection |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 91 | * @wp_gpio: gpio for write protection |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 92 | */ |
| 93 | struct fsl_esdhc_priv { |
| 94 | struct fsl_esdhc *esdhc_regs; |
| 95 | unsigned int sdhc_clk; |
Yangbo Lu | f1bce08 | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 96 | bool is_sdhc_per_clk; |
Peng Fan | 51313b4 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 97 | unsigned int clock; |
Yangbo Lu | 41dec2f | 2019-10-21 18:09:07 +0800 | [diff] [blame] | 98 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 99 | struct mmc *mmc; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 100 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 101 | struct udevice *dev; |
Michael Walle | b1ba146 | 2020-09-23 12:42:48 +0200 | [diff] [blame] | 102 | dma_addr_t dma_addr; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 103 | }; |
| 104 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 105 | /* Return the XFERTYP flags for a given command and data packet */ |
Kim Phillips | eafa90a | 2012-10-29 13:34:44 +0000 | [diff] [blame] | 106 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 107 | { |
| 108 | uint xfertyp = 0; |
| 109 | |
| 110 | if (data) { |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 111 | xfertyp |= XFERTYP_DPSEL; |
| 112 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 113 | if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK && |
| 114 | cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200) |
| 115 | xfertyp |= XFERTYP_DMAEN; |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 116 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 117 | if (data->blocks > 1) { |
| 118 | xfertyp |= XFERTYP_MSBSEL; |
| 119 | xfertyp |= XFERTYP_BCEN; |
Jerry Huang | d621da0 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 120 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 121 | xfertyp |= XFERTYP_AC12EN; |
| 122 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | if (data->flags & MMC_DATA_READ) |
| 126 | xfertyp |= XFERTYP_DTDSEL; |
| 127 | } |
| 128 | |
| 129 | if (cmd->resp_type & MMC_RSP_CRC) |
| 130 | xfertyp |= XFERTYP_CCCEN; |
| 131 | if (cmd->resp_type & MMC_RSP_OPCODE) |
| 132 | xfertyp |= XFERTYP_CICEN; |
| 133 | if (cmd->resp_type & MMC_RSP_136) |
| 134 | xfertyp |= XFERTYP_RSPTYP_136; |
| 135 | else if (cmd->resp_type & MMC_RSP_BUSY) |
| 136 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; |
| 137 | else if (cmd->resp_type & MMC_RSP_PRESENT) |
| 138 | xfertyp |= XFERTYP_RSPTYP_48; |
| 139 | |
Jason Liu | 4571de3 | 2011-03-22 01:32:31 +0000 | [diff] [blame] | 140 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 141 | xfertyp |= XFERTYP_CMDTYP_ABORT; |
Yangbo Lu | 2550344 | 2016-01-21 17:33:19 +0800 | [diff] [blame] | 142 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 143 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
| 144 | } |
| 145 | |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 146 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 147 | /* |
| 148 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. |
| 149 | */ |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 150 | static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, |
| 151 | struct mmc_data *data) |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 152 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 153 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 154 | uint blocks; |
| 155 | char *buffer; |
| 156 | uint databuf; |
| 157 | uint size; |
| 158 | uint irqstat; |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 159 | ulong start; |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 160 | |
| 161 | if (data->flags & MMC_DATA_READ) { |
| 162 | blocks = data->blocks; |
| 163 | buffer = data->dest; |
| 164 | while (blocks) { |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 165 | start = get_timer(0); |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 166 | size = data->blocksize; |
| 167 | irqstat = esdhc_read32(®s->irqstat); |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 168 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { |
| 169 | if (get_timer(start) > PIO_TIMEOUT) { |
| 170 | printf("\nData Read Failed in PIO Mode."); |
| 171 | return; |
| 172 | } |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 173 | } |
| 174 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 175 | udelay(100); /* Wait before last byte transfer complete */ |
| 176 | irqstat = esdhc_read32(®s->irqstat); |
| 177 | databuf = in_le32(®s->datport); |
| 178 | *((uint *)buffer) = databuf; |
| 179 | buffer += 4; |
| 180 | size -= 4; |
| 181 | } |
| 182 | blocks--; |
| 183 | } |
| 184 | } else { |
| 185 | blocks = data->blocks; |
Wolfgang Denk | 7b43db9 | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 186 | buffer = (char *)data->src; |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 187 | while (blocks) { |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 188 | start = get_timer(0); |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 189 | size = data->blocksize; |
| 190 | irqstat = esdhc_read32(®s->irqstat); |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 191 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { |
| 192 | if (get_timer(start) > PIO_TIMEOUT) { |
| 193 | printf("\nData Write Failed in PIO Mode."); |
| 194 | return; |
| 195 | } |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 196 | } |
| 197 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 198 | udelay(100); /* Wait before last byte transfer complete */ |
| 199 | databuf = *((uint *)buffer); |
| 200 | buffer += 4; |
| 201 | size -= 4; |
| 202 | irqstat = esdhc_read32(®s->irqstat); |
| 203 | out_le32(®s->datport, databuf); |
| 204 | } |
| 205 | blocks--; |
| 206 | } |
| 207 | } |
| 208 | } |
| 209 | #endif |
| 210 | |
Michael Walle | 7e48a02 | 2020-09-23 12:42:49 +0200 | [diff] [blame^] | 211 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 212 | static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv, |
| 213 | struct mmc_data *data) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 214 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 215 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Michael Walle | 7e48a02 | 2020-09-23 12:42:49 +0200 | [diff] [blame^] | 216 | uint wml_value = data->blocksize / 4; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 217 | |
| 218 | if (data->flags & MMC_DATA_READ) { |
Priyanka Jain | 32c8cfb | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 219 | if (wml_value > WML_RD_WML_MAX) |
| 220 | wml_value = WML_RD_WML_MAX_VAL; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 221 | |
Roy Zang | ab467c5 | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 222 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 223 | } else { |
Priyanka Jain | 32c8cfb | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 224 | if (wml_value > WML_WR_WML_MAX) |
| 225 | wml_value = WML_WR_WML_MAX_VAL; |
Yangbo Lu | 0cc127c | 2019-10-31 18:54:25 +0800 | [diff] [blame] | 226 | |
Roy Zang | ab467c5 | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 227 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, |
Michael Walle | 7e48a02 | 2020-09-23 12:42:49 +0200 | [diff] [blame^] | 228 | wml_value << 16); |
| 229 | } |
| 230 | } |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 231 | #endif |
Michael Walle | 7e48a02 | 2020-09-23 12:42:49 +0200 | [diff] [blame^] | 232 | |
| 233 | static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data) |
| 234 | { |
| 235 | uint trans_bytes = data->blocksize * data->blocks; |
| 236 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 237 | void *buf; |
| 238 | |
| 239 | if (data->flags & MMC_DATA_WRITE) |
| 240 | buf = (void *)data->src; |
| 241 | else |
| 242 | buf = data->dest; |
| 243 | |
| 244 | priv->dma_addr = dma_map_single(buf, trans_bytes, |
| 245 | mmc_get_dma_dir(data)); |
| 246 | if (upper_32_bits(priv->dma_addr)) |
| 247 | printf("Cannot use 64 bit addresses with SDMA\n"); |
| 248 | esdhc_write32(®s->dsaddr, lower_32_bits(priv->dma_addr)); |
| 249 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
| 250 | } |
| 251 | |
| 252 | static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
| 253 | struct mmc_data *data) |
| 254 | { |
| 255 | int timeout; |
| 256 | bool is_write = data->flags & MMC_DATA_WRITE; |
| 257 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 258 | |
| 259 | if (is_write && !(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) { |
| 260 | printf("Can not write to locked SD card.\n"); |
| 261 | return -EINVAL; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 262 | } |
| 263 | |
Michael Walle | 7e48a02 | 2020-09-23 12:42:49 +0200 | [diff] [blame^] | 264 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 265 | esdhc_setup_watermark_level(priv, data); |
| 266 | #else |
| 267 | esdhc_setup_dma(priv, data); |
| 268 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 269 | |
| 270 | /* Calculate the timeout period for data transactions */ |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 271 | /* |
| 272 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles |
| 273 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec |
| 274 | * So, Number of SD Clock cycles for 0.25sec should be minimum |
| 275 | * (SD Clock/sec * 0.25 sec) SD Clock cycles |
Andrew Gabbasov | fb82398 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 276 | * = (mmc->clock * 1/4) SD Clock cycles |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 277 | * As 1) >= 2) |
Andrew Gabbasov | fb82398 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 278 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 279 | * Taking log2 both the sides |
Andrew Gabbasov | fb82398 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 280 | * => timeout + 13 >= log2(mmc->clock/4) |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 281 | * Rounding up to next power of 2 |
Andrew Gabbasov | fb82398 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 282 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
| 283 | * => timeout + 13 = fls(mmc->clock/4) |
Yangbo Lu | e978a31 | 2015-12-30 14:19:30 +0800 | [diff] [blame] | 284 | * |
| 285 | * However, the MMC spec "It is strongly recommended for hosts to |
| 286 | * implement more than 500ms timeout value even if the card |
| 287 | * indicates the 250ms maximum busy length." Even the previous |
| 288 | * value of 300ms is known to be insufficient for some cards. |
| 289 | * So, we use |
| 290 | * => timeout + 13 = fls(mmc->clock/2) |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 291 | */ |
Yangbo Lu | e978a31 | 2015-12-30 14:19:30 +0800 | [diff] [blame] | 292 | timeout = fls(mmc->clock/2); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 293 | timeout -= 13; |
| 294 | |
| 295 | if (timeout > 14) |
| 296 | timeout = 14; |
| 297 | |
| 298 | if (timeout < 0) |
| 299 | timeout = 0; |
| 300 | |
Kumar Gala | 5103a03 | 2011-01-29 15:36:10 -0600 | [diff] [blame] | 301 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 302 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) |
| 303 | timeout++; |
| 304 | #endif |
| 305 | |
Haijun.Zhang | 1336e2d | 2014-03-18 17:04:23 +0800 | [diff] [blame] | 306 | #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
| 307 | timeout = 0xE; |
| 308 | #endif |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 309 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 314 | /* |
| 315 | * Sends a command out on the bus. Takes the mmc pointer, |
| 316 | * a command pointer, and an optional data pointer. |
| 317 | */ |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 318 | static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
| 319 | struct mmc_cmd *cmd, struct mmc_data *data) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 320 | { |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 321 | int err = 0; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 322 | uint xfertyp; |
| 323 | uint irqstat; |
Peng Fan | 51313b4 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 324 | u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 325 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Fabio Estevam | 29c2edb | 2018-11-19 10:31:53 -0200 | [diff] [blame] | 326 | unsigned long start; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 327 | |
Jerry Huang | d621da0 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 328 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 329 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 330 | return 0; |
| 331 | #endif |
| 332 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 333 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 334 | |
| 335 | sync(); |
| 336 | |
| 337 | /* Wait for the bus to be idle */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 338 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
| 339 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) |
| 340 | ; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 341 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 342 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
| 343 | ; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 344 | |
| 345 | /* Wait at least 8 SD clock cycles before the next command */ |
| 346 | /* |
| 347 | * Note: This is way more than 8 cycles, but 1ms seems to |
| 348 | * resolve timing issues with some cards |
| 349 | */ |
| 350 | udelay(1000); |
| 351 | |
| 352 | /* Set up for a data transfer if we have one */ |
| 353 | if (data) { |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 354 | err = esdhc_setup_data(priv, mmc, data); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 355 | if(err) |
| 356 | return err; |
| 357 | } |
| 358 | |
| 359 | /* Figure out the transfer arguments */ |
| 360 | xfertyp = esdhc_xfertyp(cmd, data); |
| 361 | |
Andrew Gabbasov | 01b7735 | 2013-06-11 10:34:22 -0500 | [diff] [blame] | 362 | /* Mask all irqs */ |
| 363 | esdhc_write32(®s->irqsigen, 0); |
| 364 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 365 | /* Send the command */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 366 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
| 367 | esdhc_write32(®s->xfertyp, xfertyp); |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 368 | |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 369 | if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || |
| 370 | cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) |
| 371 | flags = IRQSTAT_BRR; |
| 372 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 373 | /* Wait for the command to complete */ |
Fabio Estevam | 29c2edb | 2018-11-19 10:31:53 -0200 | [diff] [blame] | 374 | start = get_timer(0); |
| 375 | while (!(esdhc_read32(®s->irqstat) & flags)) { |
| 376 | if (get_timer(start) > 1000) { |
| 377 | err = -ETIMEDOUT; |
| 378 | goto out; |
| 379 | } |
| 380 | } |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 381 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 382 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 383 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 384 | if (irqstat & CMD_ERR) { |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 385 | err = -ECOMM; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 386 | goto out; |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 387 | } |
| 388 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 389 | if (irqstat & IRQSTAT_CTOE) { |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 390 | err = -ETIMEDOUT; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 391 | goto out; |
| 392 | } |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 393 | |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 394 | /* Workaround for ESDHC errata ENGcm03648 */ |
| 395 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { |
Yangbo Lu | 253d5bd | 2015-04-15 10:13:12 +0800 | [diff] [blame] | 396 | int timeout = 6000; |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 397 | |
Yangbo Lu | 253d5bd | 2015-04-15 10:13:12 +0800 | [diff] [blame] | 398 | /* Poll on DATA0 line for cmd with busy signal for 600 ms */ |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 399 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
| 400 | PRSSTAT_DAT0)) { |
| 401 | udelay(100); |
| 402 | timeout--; |
| 403 | } |
| 404 | |
| 405 | if (timeout <= 0) { |
| 406 | printf("Timeout waiting for DAT0 to go high!\n"); |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 407 | err = -ETIMEDOUT; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 408 | goto out; |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 409 | } |
| 410 | } |
| 411 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 412 | /* Copy the response to the response buffer */ |
| 413 | if (cmd->resp_type & MMC_RSP_136) { |
| 414 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; |
| 415 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 416 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
| 417 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); |
| 418 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); |
| 419 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); |
Rabin Vincent | 998be3d | 2009-04-05 13:30:56 +0530 | [diff] [blame] | 420 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
| 421 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); |
| 422 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); |
| 423 | cmd->response[3] = (cmdrsp0 << 8); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 424 | } else |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 425 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 426 | |
| 427 | /* Wait until all of the blocks are transferred */ |
| 428 | if (data) { |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 429 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 430 | esdhc_pio_read_write(priv, data); |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 431 | #else |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 432 | flags = DATA_COMPLETE; |
| 433 | if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || |
| 434 | cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) |
| 435 | flags = IRQSTAT_BRR; |
| 436 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 437 | do { |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 438 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 439 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 440 | if (irqstat & IRQSTAT_DTOE) { |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 441 | err = -ETIMEDOUT; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 442 | goto out; |
| 443 | } |
Frans Meulenbroeks | 63fb5a7 | 2010-07-31 04:45:18 +0000 | [diff] [blame] | 444 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 445 | if (irqstat & DATA_ERR) { |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 446 | err = -ECOMM; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 447 | goto out; |
| 448 | } |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 449 | } while ((irqstat & flags) != flags); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 450 | |
Peng Fan | 4683b22 | 2015-06-25 10:32:26 +0800 | [diff] [blame] | 451 | /* |
| 452 | * Need invalidate the dcache here again to avoid any |
| 453 | * cache-fill during the DMA operations such as the |
| 454 | * speculative pre-fetching etc. |
| 455 | */ |
Michael Walle | b1ba146 | 2020-09-23 12:42:48 +0200 | [diff] [blame] | 456 | dma_unmap_single(priv->dma_addr, |
| 457 | data->blocks * data->blocksize, |
| 458 | mmc_get_dma_dir(data)); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 459 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 460 | } |
| 461 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 462 | out: |
| 463 | /* Reset CMD and DATA portions on error */ |
| 464 | if (err) { |
| 465 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | |
| 466 | SYSCTL_RSTC); |
| 467 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) |
| 468 | ; |
| 469 | |
| 470 | if (data) { |
| 471 | esdhc_write32(®s->sysctl, |
| 472 | esdhc_read32(®s->sysctl) | |
| 473 | SYSCTL_RSTD); |
| 474 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) |
| 475 | ; |
| 476 | } |
| 477 | } |
| 478 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 479 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 480 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 481 | return err; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 482 | } |
| 483 | |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 484 | static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 485 | { |
Benoît Thébaudeau | b9b4f14 | 2018-01-16 22:44:18 +0100 | [diff] [blame] | 486 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 487 | int div = 1; |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 488 | int pre_div = 2; |
Yinbo Zhu | 6f883e5 | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 489 | unsigned int sdhc_clk = priv->sdhc_clk; |
| 490 | u32 time_out; |
| 491 | u32 value; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 492 | uint clk; |
| 493 | |
Pantelis Antoniou | 93bfd61 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 494 | if (clock < mmc->cfg->f_min) |
| 495 | clock = mmc->cfg->f_min; |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 496 | |
Yangbo Lu | 5d336d1 | 2019-10-21 18:09:09 +0800 | [diff] [blame] | 497 | while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256) |
Lukasz Majewski | b6a0427 | 2019-05-07 17:47:28 +0200 | [diff] [blame] | 498 | pre_div *= 2; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 499 | |
Yangbo Lu | 5d336d1 | 2019-10-21 18:09:09 +0800 | [diff] [blame] | 500 | while (sdhc_clk / (div * pre_div) > clock && div < 16) |
Lukasz Majewski | b6a0427 | 2019-05-07 17:47:28 +0200 | [diff] [blame] | 501 | div++; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 502 | |
Yangbo Lu | 30f6444 | 2020-09-01 16:58:06 +0800 | [diff] [blame] | 503 | mmc->clock = sdhc_clk / pre_div / div; |
| 504 | priv->clock = mmc->clock; |
| 505 | |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 506 | pre_div >>= 1; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 507 | div -= 1; |
| 508 | |
| 509 | clk = (pre_div << 8) | (div << 4); |
| 510 | |
Kumar Gala | cc4d122 | 2010-03-18 15:51:05 -0500 | [diff] [blame] | 511 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 512 | |
| 513 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 514 | |
Yinbo Zhu | 6f883e5 | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 515 | time_out = 20; |
| 516 | value = PRSSTAT_SDSTB; |
| 517 | while (!(esdhc_read32(®s->prsstat) & value)) { |
| 518 | if (time_out == 0) { |
| 519 | printf("fsl_esdhc: Internal clock never stabilised.\n"); |
| 520 | break; |
| 521 | } |
| 522 | time_out--; |
| 523 | mdelay(1); |
| 524 | } |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 525 | |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 526 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 527 | } |
| 528 | |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 529 | static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 530 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 531 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 532 | u32 value; |
| 533 | u32 time_out; |
| 534 | |
| 535 | value = esdhc_read32(®s->sysctl); |
| 536 | |
| 537 | if (enable) |
| 538 | value |= SYSCTL_CKEN; |
| 539 | else |
| 540 | value &= ~SYSCTL_CKEN; |
| 541 | |
| 542 | esdhc_write32(®s->sysctl, value); |
| 543 | |
| 544 | time_out = 20; |
| 545 | value = PRSSTAT_SDSTB; |
| 546 | while (!(esdhc_read32(®s->prsstat) & value)) { |
| 547 | if (time_out == 0) { |
| 548 | printf("fsl_esdhc: Internal clock never stabilised.\n"); |
| 549 | break; |
| 550 | } |
| 551 | time_out--; |
| 552 | mdelay(1); |
| 553 | } |
| 554 | } |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 555 | |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 556 | static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv) |
| 557 | { |
| 558 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 559 | u32 time_out; |
| 560 | |
| 561 | esdhc_setbits32(®s->esdhcctl, ESDHCCTL_FAF); |
| 562 | |
| 563 | time_out = 20; |
| 564 | while (esdhc_read32(®s->esdhcctl) & ESDHCCTL_FAF) { |
| 565 | if (time_out == 0) { |
| 566 | printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n"); |
| 567 | break; |
| 568 | } |
| 569 | time_out--; |
| 570 | mdelay(1); |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv, |
| 575 | bool en) |
| 576 | { |
| 577 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 578 | |
| 579 | esdhc_clock_control(priv, false); |
| 580 | esdhc_flush_async_fifo(priv); |
| 581 | if (en) |
| 582 | esdhc_setbits32(®s->tbctl, TBCTL_TB_EN); |
| 583 | else |
| 584 | esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN); |
| 585 | esdhc_clock_control(priv, true); |
| 586 | } |
| 587 | |
| 588 | static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv) |
| 589 | { |
| 590 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 591 | |
| 592 | esdhc_clrbits32(®s->sdtimingctl, FLW_CTL_BG); |
| 593 | esdhc_clrbits32(®s->sdclkctl, CMD_CLK_CTL); |
| 594 | |
| 595 | esdhc_clock_control(priv, false); |
| 596 | esdhc_clrbits32(®s->tbctl, HS400_MODE); |
| 597 | esdhc_clock_control(priv, true); |
| 598 | |
| 599 | esdhc_clrbits32(®s->dllcfg0, DLL_FREQ_SEL | DLL_ENABLE); |
| 600 | esdhc_clrbits32(®s->tbctl, HS400_WNDW_ADJUST); |
| 601 | |
| 602 | esdhc_tuning_block_enable(priv, false); |
| 603 | } |
| 604 | |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 605 | static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode) |
| 606 | { |
| 607 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 608 | |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 609 | /* Exit HS400 mode before setting any other mode */ |
| 610 | if (esdhc_read32(®s->tbctl) & HS400_MODE && |
| 611 | mode != MMC_HS_400) |
| 612 | esdhc_exit_hs400(priv); |
| 613 | |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 614 | esdhc_clock_control(priv, false); |
| 615 | |
| 616 | if (mode == MMC_HS_200) |
| 617 | esdhc_clrsetbits32(®s->autoc12err, UHSM_MASK, |
| 618 | UHSM_SDR104_HS200); |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 619 | if (mode == MMC_HS_400) { |
| 620 | esdhc_setbits32(®s->tbctl, HS400_MODE); |
| 621 | esdhc_setbits32(®s->sdclkctl, CMD_CLK_CTL); |
| 622 | esdhc_clock_control(priv, true); |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 623 | |
Yangbo Lu | 78804de | 2020-09-01 16:58:07 +0800 | [diff] [blame] | 624 | if (priv->clock == 200000000) |
| 625 | esdhc_setbits32(®s->dllcfg0, DLL_FREQ_SEL); |
| 626 | |
| 627 | esdhc_setbits32(®s->dllcfg0, DLL_ENABLE); |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 628 | esdhc_setbits32(®s->tbctl, HS400_WNDW_ADJUST); |
| 629 | |
| 630 | esdhc_clock_control(priv, false); |
| 631 | esdhc_flush_async_fifo(priv); |
| 632 | } |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 633 | esdhc_clock_control(priv, true); |
| 634 | } |
| 635 | |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 636 | static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 637 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 638 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 639 | |
Yangbo Lu | f1bce08 | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 640 | if (priv->is_sdhc_per_clk) { |
| 641 | /* Select to use peripheral clock */ |
| 642 | esdhc_clock_control(priv, false); |
| 643 | esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS); |
| 644 | esdhc_clock_control(priv, true); |
| 645 | } |
| 646 | |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 647 | if (mmc->selected_mode == MMC_HS_400) |
| 648 | esdhc_tuning_block_enable(priv, true); |
| 649 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 650 | /* Set the clock speed */ |
Peng Fan | 51313b4 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 651 | if (priv->clock != mmc->clock) |
| 652 | set_sysctl(priv, mmc, mmc->clock); |
| 653 | |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 654 | /* Set timing */ |
| 655 | esdhc_set_timing(priv, mmc->selected_mode); |
| 656 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 657 | /* Set the bus width */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 658 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 659 | |
| 660 | if (mmc->bus_width == 4) |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 661 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 662 | else if (mmc->bus_width == 8) |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 663 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
| 664 | |
Jaehoon Chung | 07b0b9c | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 665 | return 0; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 666 | } |
| 667 | |
Rasmus Villemoes | ede2822 | 2020-01-30 12:06:45 +0000 | [diff] [blame] | 668 | static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs) |
| 669 | { |
| 670 | #ifdef CONFIG_ARCH_MPC830X |
| 671 | immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
| 672 | sysconf83xx_t *sysconf = &immr->sysconf; |
| 673 | |
| 674 | setbits_be32(&sysconf->sdhccr, 0x02000000); |
| 675 | #else |
| 676 | esdhc_write32(®s->esdhcctl, 0x00000040); |
| 677 | #endif |
| 678 | } |
| 679 | |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 680 | static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 681 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 682 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Simon Glass | 201e828 | 2017-07-29 11:35:20 -0600 | [diff] [blame] | 683 | ulong start; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 684 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 685 | /* Reset the entire host controller */ |
Dirk Behme | a61da72 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 686 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 687 | |
| 688 | /* Wait until the controller is available */ |
Simon Glass | 201e828 | 2017-07-29 11:35:20 -0600 | [diff] [blame] | 689 | start = get_timer(0); |
| 690 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { |
| 691 | if (get_timer(start) > 1000) |
| 692 | return -ETIMEDOUT; |
| 693 | } |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 694 | |
Yangbo Lu | 1b5f0ba | 2020-09-01 16:58:02 +0800 | [diff] [blame] | 695 | /* Clean TBCTL[TB_EN] which is not able to be reset by reset all */ |
| 696 | esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN); |
| 697 | |
Rasmus Villemoes | ede2822 | 2020-01-30 12:06:45 +0000 | [diff] [blame] | 698 | esdhc_enable_cache_snooping(regs); |
P.V.Suresh | 2c1764e | 2010-12-04 10:37:23 +0530 | [diff] [blame] | 699 | |
Dirk Behme | a61da72 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 700 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 701 | |
| 702 | /* Set the initial clock speed */ |
Jaehoon Chung | 6511718 | 2018-01-26 19:25:29 +0900 | [diff] [blame] | 703 | mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 704 | |
| 705 | /* Disable the BRR and BWR bits in IRQSTAT */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 706 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 707 | |
| 708 | /* Put the PROCTL reg back to the default */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 709 | esdhc_write32(®s->proctl, PROCTL_INIT); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 710 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 711 | /* Set timout to the maximum value */ |
| 712 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 713 | |
Thierry Reding | d48d2e2 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 714 | return 0; |
| 715 | } |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 716 | |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 717 | static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) |
Thierry Reding | d48d2e2 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 718 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 719 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 720 | |
Haijun.Zhang | f7e27cc | 2014-01-10 13:52:17 +0800 | [diff] [blame] | 721 | #ifdef CONFIG_ESDHC_DETECT_QUIRK |
| 722 | if (CONFIG_ESDHC_DETECT_QUIRK) |
| 723 | return 1; |
| 724 | #endif |
Yangbo Lu | 9abf648 | 2020-05-19 11:06:43 +0800 | [diff] [blame] | 725 | if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS) |
| 726 | return 1; |
Thierry Reding | d48d2e2 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 727 | |
Yangbo Lu | 9abf648 | 2020-05-19 11:06:43 +0800 | [diff] [blame] | 728 | return 0; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 729 | } |
| 730 | |
Yangbo Lu | 5705973 | 2019-10-31 18:54:23 +0800 | [diff] [blame] | 731 | static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, |
| 732 | struct mmc_config *cfg) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 733 | { |
Yangbo Lu | 5705973 | 2019-10-31 18:54:23 +0800 | [diff] [blame] | 734 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Yangbo Lu | 5b05fc0 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 735 | u32 caps; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 736 | |
Wang Huan | 19060bd | 2014-09-05 13:52:40 +0800 | [diff] [blame] | 737 | caps = esdhc_read32(®s->hostcapblt); |
Roy Zang | 3b4456e | 2011-01-07 00:06:47 -0600 | [diff] [blame] | 738 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 |
Yangbo Lu | 5b05fc0 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 739 | caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30); |
Roy Zang | 3b4456e | 2011-01-07 00:06:47 -0600 | [diff] [blame] | 740 | #endif |
Haijun.Zhang | ef38f3f | 2013-10-31 09:38:19 +0800 | [diff] [blame] | 741 | #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
Yangbo Lu | 5b05fc0 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 742 | caps |= HOSTCAPBLT_VS33; |
Haijun.Zhang | ef38f3f | 2013-10-31 09:38:19 +0800 | [diff] [blame] | 743 | #endif |
Yangbo Lu | 5b05fc0 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 744 | if (caps & HOSTCAPBLT_VS18) |
| 745 | cfg->voltages |= MMC_VDD_165_195; |
| 746 | if (caps & HOSTCAPBLT_VS30) |
| 747 | cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; |
| 748 | if (caps & HOSTCAPBLT_VS33) |
| 749 | cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 750 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 751 | cfg->name = "FSL_SDHC"; |
Abbas Raza | aad4659 | 2013-03-25 09:13:34 +0000 | [diff] [blame] | 752 | |
Yangbo Lu | 5b05fc0 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 753 | if (caps & HOSTCAPBLT_HSS) |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 754 | cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 755 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 756 | cfg->f_min = 400000; |
Peng Fan | 51313b4 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 757 | cfg->f_max = min(priv->sdhc_clk, (u32)200000000); |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 758 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 759 | } |
| 760 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 761 | #ifdef CONFIG_OF_LIBFDT |
Yangbo Lu | fce1e16 | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 762 | __weak int esdhc_status_fixup(void *blob, const char *compat) |
| 763 | { |
| 764 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
| 765 | if (!hwconfig("esdhc")) { |
| 766 | do_fixup_by_compat(blob, compat, "status", "disabled", |
| 767 | sizeof("disabled"), 1); |
| 768 | return 1; |
| 769 | } |
| 770 | #endif |
Yangbo Lu | fce1e16 | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 771 | return 0; |
| 772 | } |
| 773 | |
Yangbo Lu | c927d65 | 2020-05-19 11:06:44 +0800 | [diff] [blame] | 774 | #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND |
| 775 | static int fsl_esdhc_get_cd(struct udevice *dev); |
| 776 | |
| 777 | static void esdhc_disable_for_no_card(void *blob) |
| 778 | { |
| 779 | struct udevice *dev; |
| 780 | |
| 781 | for (uclass_first_device(UCLASS_MMC, &dev); |
| 782 | dev; |
| 783 | uclass_next_device(&dev)) { |
| 784 | char esdhc_path[50]; |
| 785 | |
| 786 | if (fsl_esdhc_get_cd(dev)) |
| 787 | continue; |
| 788 | |
| 789 | snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx", |
| 790 | (unsigned long)dev_read_addr(dev)); |
| 791 | do_fixup_by_path(blob, esdhc_path, "status", "disabled", |
| 792 | sizeof("disabled"), 1); |
| 793 | } |
| 794 | } |
| 795 | #endif |
| 796 | |
Masahiro Yamada | b75d8dc | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 797 | void fdt_fixup_esdhc(void *blob, struct bd_info *bd) |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 798 | { |
| 799 | const char *compat = "fsl,esdhc"; |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 800 | |
Yangbo Lu | fce1e16 | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 801 | if (esdhc_status_fixup(blob, compat)) |
Chenhui Zhao | a6da8b8 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 802 | return; |
Yangbo Lu | c927d65 | 2020-05-19 11:06:44 +0800 | [diff] [blame] | 803 | #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND |
| 804 | esdhc_disable_for_no_card(blob); |
| 805 | #endif |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 806 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
Simon Glass | e9adeca | 2012-12-13 20:49:05 +0000 | [diff] [blame] | 807 | gd->arch.sdhc_clk, 1); |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 808 | } |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 809 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 810 | |
Yangbo Lu | 6187047 | 2019-10-31 18:54:26 +0800 | [diff] [blame] | 811 | #if !CONFIG_IS_ENABLED(DM_MMC) |
| 812 | static int esdhc_getcd(struct mmc *mmc) |
| 813 | { |
| 814 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 815 | |
| 816 | return esdhc_getcd_common(priv); |
| 817 | } |
| 818 | |
| 819 | static int esdhc_init(struct mmc *mmc) |
| 820 | { |
| 821 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 822 | |
| 823 | return esdhc_init_common(priv, mmc); |
| 824 | } |
| 825 | |
| 826 | static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
| 827 | struct mmc_data *data) |
| 828 | { |
| 829 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 830 | |
| 831 | return esdhc_send_cmd_common(priv, mmc, cmd, data); |
| 832 | } |
| 833 | |
| 834 | static int esdhc_set_ios(struct mmc *mmc) |
| 835 | { |
| 836 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 837 | |
| 838 | return esdhc_set_ios_common(priv, mmc); |
| 839 | } |
| 840 | |
| 841 | static const struct mmc_ops esdhc_ops = { |
| 842 | .getcd = esdhc_getcd, |
| 843 | .init = esdhc_init, |
| 844 | .send_cmd = esdhc_send_cmd, |
| 845 | .set_ios = esdhc_set_ios, |
| 846 | }; |
| 847 | |
Masahiro Yamada | b75d8dc | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 848 | int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg) |
Yangbo Lu | 6187047 | 2019-10-31 18:54:26 +0800 | [diff] [blame] | 849 | { |
| 850 | struct fsl_esdhc_plat *plat; |
| 851 | struct fsl_esdhc_priv *priv; |
| 852 | struct mmc_config *mmc_cfg; |
| 853 | struct mmc *mmc; |
| 854 | |
| 855 | if (!cfg) |
| 856 | return -EINVAL; |
| 857 | |
| 858 | priv = calloc(sizeof(struct fsl_esdhc_priv), 1); |
| 859 | if (!priv) |
| 860 | return -ENOMEM; |
| 861 | plat = calloc(sizeof(struct fsl_esdhc_plat), 1); |
| 862 | if (!plat) { |
| 863 | free(priv); |
| 864 | return -ENOMEM; |
| 865 | } |
| 866 | |
| 867 | priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); |
| 868 | priv->sdhc_clk = cfg->sdhc_clk; |
Yangbo Lu | f1bce08 | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 869 | if (gd->arch.sdhc_per_clk) |
| 870 | priv->is_sdhc_per_clk = true; |
Yangbo Lu | 6187047 | 2019-10-31 18:54:26 +0800 | [diff] [blame] | 871 | |
| 872 | mmc_cfg = &plat->cfg; |
| 873 | |
| 874 | if (cfg->max_bus_width == 8) { |
| 875 | mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | |
| 876 | MMC_MODE_8BIT; |
| 877 | } else if (cfg->max_bus_width == 4) { |
| 878 | mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT; |
| 879 | } else if (cfg->max_bus_width == 1) { |
| 880 | mmc_cfg->host_caps |= MMC_MODE_1BIT; |
| 881 | } else { |
| 882 | mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | |
| 883 | MMC_MODE_8BIT; |
| 884 | printf("No max bus width provided. Assume 8-bit supported.\n"); |
| 885 | } |
| 886 | |
| 887 | #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK |
| 888 | if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) |
| 889 | mmc_cfg->host_caps &= ~MMC_MODE_8BIT; |
| 890 | #endif |
| 891 | mmc_cfg->ops = &esdhc_ops; |
| 892 | |
| 893 | fsl_esdhc_get_cfg_common(priv, mmc_cfg); |
| 894 | |
| 895 | mmc = mmc_create(mmc_cfg, priv); |
| 896 | if (!mmc) |
| 897 | return -EIO; |
| 898 | |
| 899 | priv->mmc = mmc; |
| 900 | return 0; |
| 901 | } |
| 902 | |
Masahiro Yamada | b75d8dc | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 903 | int fsl_esdhc_mmc_init(struct bd_info *bis) |
Yangbo Lu | 6187047 | 2019-10-31 18:54:26 +0800 | [diff] [blame] | 904 | { |
| 905 | struct fsl_esdhc_cfg *cfg; |
| 906 | |
| 907 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
| 908 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
Yangbo Lu | f1bce08 | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 909 | /* Prefer peripheral clock which provides higher frequency. */ |
| 910 | if (gd->arch.sdhc_per_clk) |
| 911 | cfg->sdhc_clk = gd->arch.sdhc_per_clk; |
| 912 | else |
| 913 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
Yangbo Lu | 6187047 | 2019-10-31 18:54:26 +0800 | [diff] [blame] | 914 | return fsl_esdhc_initialize(bis, cfg); |
| 915 | } |
| 916 | #else /* DM_MMC */ |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 917 | static int fsl_esdhc_probe(struct udevice *dev) |
| 918 | { |
| 919 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 920 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 921 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 922 | fdt_addr_t addr; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 923 | struct mmc *mmc; |
Yangbo Lu | c927d65 | 2020-05-19 11:06:44 +0800 | [diff] [blame] | 924 | int ret; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 925 | |
Simon Glass | 4aac33f | 2017-07-29 11:35:23 -0600 | [diff] [blame] | 926 | addr = dev_read_addr(dev); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 927 | if (addr == FDT_ADDR_T_NONE) |
| 928 | return -EINVAL; |
Yinbo Zhu | b69e1d0 | 2019-04-11 11:01:50 +0000 | [diff] [blame] | 929 | #ifdef CONFIG_PPC |
| 930 | priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr); |
| 931 | #else |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 932 | priv->esdhc_regs = (struct fsl_esdhc *)addr; |
Yinbo Zhu | b69e1d0 | 2019-04-11 11:01:50 +0000 | [diff] [blame] | 933 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 934 | priv->dev = dev; |
| 935 | |
Yangbo Lu | f1bce08 | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 936 | if (gd->arch.sdhc_per_clk) { |
| 937 | priv->sdhc_clk = gd->arch.sdhc_per_clk; |
| 938 | priv->is_sdhc_per_clk = true; |
| 939 | } else { |
| 940 | priv->sdhc_clk = gd->arch.sdhc_clk; |
| 941 | } |
| 942 | |
Yangbo Lu | 5e81cbf | 2019-11-12 19:28:36 +0800 | [diff] [blame] | 943 | if (priv->sdhc_clk <= 0) { |
| 944 | dev_err(dev, "Unable to get clk for %s\n", dev->name); |
| 945 | return -EINVAL; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 946 | } |
| 947 | |
Yangbo Lu | 5705973 | 2019-10-31 18:54:23 +0800 | [diff] [blame] | 948 | fsl_esdhc_get_cfg_common(priv, &plat->cfg); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 949 | |
Yinbo Zhu | 6f883e5 | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 950 | mmc_of_parse(dev, &plat->cfg); |
| 951 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 952 | mmc = &plat->mmc; |
| 953 | mmc->cfg = &plat->cfg; |
| 954 | mmc->dev = dev; |
Yangbo Lu | 66fa035 | 2019-05-23 11:05:46 +0800 | [diff] [blame] | 955 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 956 | upriv->mmc = mmc; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 957 | |
Yangbo Lu | c927d65 | 2020-05-19 11:06:44 +0800 | [diff] [blame] | 958 | ret = esdhc_init_common(priv, mmc); |
| 959 | if (ret) |
| 960 | return ret; |
| 961 | |
| 962 | #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND |
| 963 | if (!fsl_esdhc_get_cd(dev)) |
| 964 | esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL); |
| 965 | #endif |
| 966 | return 0; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 967 | } |
| 968 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 969 | static int fsl_esdhc_get_cd(struct udevice *dev) |
| 970 | { |
Yangbo Lu | 08197cb | 2019-10-31 18:54:24 +0800 | [diff] [blame] | 971 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 972 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 973 | |
Yangbo Lu | 08197cb | 2019-10-31 18:54:24 +0800 | [diff] [blame] | 974 | if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE) |
| 975 | return 1; |
| 976 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 977 | return esdhc_getcd_common(priv); |
| 978 | } |
| 979 | |
| 980 | static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
| 981 | struct mmc_data *data) |
| 982 | { |
| 983 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 984 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 985 | |
| 986 | return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); |
| 987 | } |
| 988 | |
| 989 | static int fsl_esdhc_set_ios(struct udevice *dev) |
| 990 | { |
| 991 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 992 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 993 | |
| 994 | return esdhc_set_ios_common(priv, &plat->mmc); |
| 995 | } |
| 996 | |
Yangbo Lu | 1fdefd1 | 2020-09-01 16:58:00 +0800 | [diff] [blame] | 997 | static int fsl_esdhc_reinit(struct udevice *dev) |
| 998 | { |
| 999 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 1000 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1001 | |
| 1002 | return esdhc_init_common(priv, &plat->mmc); |
| 1003 | } |
| 1004 | |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 1005 | #ifdef MMC_SUPPORTS_TUNING |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 1006 | static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) |
| 1007 | { |
| 1008 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 1009 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1010 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 1011 | u32 val, irqstaten; |
| 1012 | int i; |
| 1013 | |
| 1014 | esdhc_tuning_block_enable(priv, true); |
| 1015 | esdhc_setbits32(®s->autoc12err, EXECUTE_TUNING); |
| 1016 | |
| 1017 | irqstaten = esdhc_read32(®s->irqstaten); |
| 1018 | esdhc_write32(®s->irqstaten, IRQSTATEN_BRR); |
| 1019 | |
| 1020 | for (i = 0; i < MAX_TUNING_LOOP; i++) { |
| 1021 | mmc_send_tuning(&plat->mmc, opcode, NULL); |
| 1022 | mdelay(1); |
| 1023 | |
| 1024 | val = esdhc_read32(®s->autoc12err); |
| 1025 | if (!(val & EXECUTE_TUNING)) { |
| 1026 | if (val & SMPCLKSEL) |
| 1027 | break; |
| 1028 | } |
| 1029 | } |
| 1030 | |
| 1031 | esdhc_write32(®s->irqstaten, irqstaten); |
| 1032 | |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 1033 | if (i != MAX_TUNING_LOOP) { |
| 1034 | if (plat->mmc.hs400_tuning) |
| 1035 | esdhc_setbits32(®s->sdtimingctl, FLW_CTL_BG); |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 1036 | return 0; |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 1037 | } |
Yangbo Lu | b1a4247 | 2020-09-01 16:58:01 +0800 | [diff] [blame] | 1038 | |
| 1039 | printf("fsl_esdhc: tuning failed!\n"); |
| 1040 | esdhc_clrbits32(®s->autoc12err, SMPCLKSEL); |
| 1041 | esdhc_clrbits32(®s->autoc12err, EXECUTE_TUNING); |
| 1042 | esdhc_tuning_block_enable(priv, false); |
| 1043 | return -ETIMEDOUT; |
| 1044 | } |
| 1045 | #endif |
| 1046 | |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 1047 | int fsl_esdhc_hs400_prepare_ddr(struct udevice *dev) |
| 1048 | { |
| 1049 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1050 | |
| 1051 | esdhc_tuning_block_enable(priv, false); |
| 1052 | return 0; |
| 1053 | } |
| 1054 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1055 | static const struct dm_mmc_ops fsl_esdhc_ops = { |
| 1056 | .get_cd = fsl_esdhc_get_cd, |
| 1057 | .send_cmd = fsl_esdhc_send_cmd, |
| 1058 | .set_ios = fsl_esdhc_set_ios, |
Yinbo Zhu | 6f883e5 | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 1059 | #ifdef MMC_SUPPORTS_TUNING |
| 1060 | .execute_tuning = fsl_esdhc_execute_tuning, |
| 1061 | #endif |
Yangbo Lu | 1fdefd1 | 2020-09-01 16:58:00 +0800 | [diff] [blame] | 1062 | .reinit = fsl_esdhc_reinit, |
Yangbo Lu | db8f936 | 2020-09-01 16:58:05 +0800 | [diff] [blame] | 1063 | .hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr, |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1064 | }; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1065 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1066 | static const struct udevice_id fsl_esdhc_ids[] = { |
Yangbo Lu | a6473f8 | 2016-12-07 11:54:31 +0800 | [diff] [blame] | 1067 | { .compatible = "fsl,esdhc", }, |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1068 | { /* sentinel */ } |
| 1069 | }; |
| 1070 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1071 | static int fsl_esdhc_bind(struct udevice *dev) |
| 1072 | { |
| 1073 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 1074 | |
| 1075 | return mmc_bind(dev, &plat->mmc, &plat->cfg); |
| 1076 | } |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1077 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1078 | U_BOOT_DRIVER(fsl_esdhc) = { |
| 1079 | .name = "fsl-esdhc-mmc", |
| 1080 | .id = UCLASS_MMC, |
| 1081 | .of_match = fsl_esdhc_ids, |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1082 | .ops = &fsl_esdhc_ops, |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1083 | .bind = fsl_esdhc_bind, |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1084 | .probe = fsl_esdhc_probe, |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 1085 | .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1086 | .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), |
| 1087 | }; |
| 1088 | #endif |