blob: 3e3212848591ed15af2d3806ef47c4fc1c2b07e4 [file] [log] [blame]
Wang Huanc8a7d9d2014-09-05 13:52:45 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Wang Huanc8a7d9d2014-09-05 13:52:45 +080010#define CONFIG_LS102XA
11
Wang Dongsheng340848b2015-06-04 12:01:09 +080012#define CONFIG_ARMV7_PSCI
13
Gong Qianyu18fb0e32015-10-26 19:47:42 +080014#define CONFIG_SYS_FSL_CLK
Wang Huanc8a7d9d2014-09-05 13:52:45 +080015
16#define CONFIG_DISPLAY_CPUINFO
17#define CONFIG_DISPLAY_BOARDINFO
18
19#define CONFIG_SKIP_LOWLEVEL_INIT
20#define CONFIG_BOARD_EARLY_INIT_F
Tang Yuantian99e1bd42015-05-14 17:20:28 +080021#define CONFIG_DEEP_SLEEP
22#ifdef CONFIG_DEEP_SLEEP
23#define CONFIG_SILENT_CONSOLE
24#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +080025
26/*
27 * Size of malloc() pool
28 */
29#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
30
31#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
32#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
33
34/*
Ramneek Mehresh10a28642015-05-29 14:47:21 +053035 * USB
36 */
37
38/*
39 * EHCI Support - disbaled by default as
40 * there is no signal coming out of soc on
41 * this board for this controller. However,
42 * the silicon still has this controller,
43 * and anyone can use this controller by
44 * taking signals out on their board.
45 */
46
47/*#define CONFIG_HAS_FSL_DR_USB*/
48
49#ifdef CONFIG_HAS_FSL_DR_USB
50#define CONFIG_USB_EHCI
51#define CONFIG_USB_EHCI_FSL
52#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
53#endif
54
55/* XHCI Support - enabled by default */
56#define CONFIG_HAS_FSL_XHCI_USB
57
58#ifdef CONFIG_HAS_FSL_XHCI_USB
59#define CONFIG_USB_XHCI_FSL
60#define CONFIG_USB_XHCI_DWC3
61#define CONFIG_USB_XHCI
62#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
63#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
64#endif
65
66#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
Ramneek Mehresh10a28642015-05-29 14:47:21 +053067#define CONFIG_USB_STORAGE
Ramneek Mehresh10a28642015-05-29 14:47:21 +053068#endif
69
70/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +080071 * Generic Timer Definitions
72 */
73#define GENERIC_TIMER_CLK 12500000
74
75#define CONFIG_SYS_CLK_FREQ 100000000
76#define CONFIG_DDR_CLK_FREQ 100000000
77
York Suna88cc3b2015-04-29 10:35:35 -070078#define DDR_SDRAM_CFG 0x470c0008
79#define DDR_CS0_BNDS 0x008000bf
80#define DDR_CS0_CONFIG 0x80014302
81#define DDR_TIMING_CFG_0 0x50550004
82#define DDR_TIMING_CFG_1 0xbcb38c56
83#define DDR_TIMING_CFG_2 0x0040d120
84#define DDR_TIMING_CFG_3 0x010e1000
85#define DDR_TIMING_CFG_4 0x00000001
86#define DDR_TIMING_CFG_5 0x03401400
87#define DDR_SDRAM_CFG_2 0x00401010
88#define DDR_SDRAM_MODE 0x00061c60
89#define DDR_SDRAM_MODE_2 0x00180000
90#define DDR_SDRAM_INTERVAL 0x18600618
91#define DDR_DDR_WRLVL_CNTL 0x8655f605
92#define DDR_DDR_WRLVL_CNTL_2 0x05060607
93#define DDR_DDR_WRLVL_CNTL_3 0x05050505
94#define DDR_DDR_CDR1 0x80040000
95#define DDR_DDR_CDR2 0x00000001
96#define DDR_SDRAM_CLK_CNTL 0x02000000
97#define DDR_DDR_ZQ_CNTL 0x89080600
98#define DDR_CS0_CONFIG_2 0
99#define DDR_SDRAM_CFG_MEM_EN 0x80000000
Tang Yuantian99e1bd42015-05-14 17:20:28 +0800100#define SDRAM_CFG2_D_INIT 0x00000010
101#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
102#define SDRAM_CFG2_FRC_SR 0x80000000
103#define SDRAM_CFG_BI 0x00000001
York Suna88cc3b2015-04-29 10:35:35 -0700104
Alison Wang8415bb62014-12-03 15:00:48 +0800105#ifdef CONFIG_RAMBOOT_PBL
106#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
107#endif
108
109#ifdef CONFIG_SD_BOOT
Alison Wang947cee12015-10-15 17:54:40 +0800110#ifdef CONFIG_SD_BOOT_QSPI
111#define CONFIG_SYS_FSL_PBL_RCW \
112 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
113#else
114#define CONFIG_SYS_FSL_PBL_RCW \
115 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
116#endif
Alison Wang8415bb62014-12-03 15:00:48 +0800117#define CONFIG_SPL_FRAMEWORK
118#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
119#define CONFIG_SPL_LIBCOMMON_SUPPORT
120#define CONFIG_SPL_LIBGENERIC_SUPPORT
121#define CONFIG_SPL_ENV_SUPPORT
122#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
123#define CONFIG_SPL_I2C_SUPPORT
124#define CONFIG_SPL_WATCHDOG_SUPPORT
125#define CONFIG_SPL_SERIAL_SUPPORT
126#define CONFIG_SPL_MMC_SUPPORT
127#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
128#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
129
130#define CONFIG_SPL_TEXT_BASE 0x10000000
131#define CONFIG_SPL_MAX_SIZE 0x1a000
132#define CONFIG_SPL_STACK 0x1001d000
133#define CONFIG_SPL_PAD_TO 0x1c000
134#define CONFIG_SYS_TEXT_BASE 0x82000000
135
Tang Yuantian99e1bd42015-05-14 17:20:28 +0800136#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
137 CONFIG_SYS_MONITOR_LEN)
Alison Wang8415bb62014-12-03 15:00:48 +0800138#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
139#define CONFIG_SPL_BSS_START_ADDR 0x80100000
140#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
141#define CONFIG_SYS_MONITOR_LEN 0x80000
142#endif
143
Alison Wangd612f0a2014-12-09 17:38:02 +0800144#ifdef CONFIG_QSPI_BOOT
145#define CONFIG_SYS_TEXT_BASE 0x40010000
Alison Wang947cee12015-10-15 17:54:40 +0800146#endif
147
148#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Alison Wangd612f0a2014-12-09 17:38:02 +0800149#define CONFIG_SYS_NO_FLASH
150#endif
151
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800152#ifndef CONFIG_SYS_TEXT_BASE
Alison Wang1c69a512015-04-21 16:04:38 +0800153#define CONFIG_SYS_TEXT_BASE 0x60100000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800154#endif
155
156#define CONFIG_NR_DRAM_BANKS 1
157#define PHYS_SDRAM 0x80000000
158#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
159
160#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
161#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
162
163#define CONFIG_SYS_HAS_SERDES
164
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530165#define CONFIG_FSL_CAAM /* Enable CAAM */
166
Alison Wang4c59ab92014-12-09 17:37:49 +0800167#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
168 !defined(CONFIG_QSPI_BOOT)
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800169#define CONFIG_U_QE
170#endif
171
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800172/*
173 * IFC Definitions
174 */
Alison Wang947cee12015-10-15 17:54:40 +0800175#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800176#define CONFIG_FSL_IFC
177#define CONFIG_SYS_FLASH_BASE 0x60000000
178#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
179
180#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
181#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
182 CSPR_PORT_SIZE_16 | \
183 CSPR_MSEL_NOR | \
184 CSPR_V)
185#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
186
187/* NOR Flash Timing Params */
188#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
189 CSOR_NOR_TRHZ_80)
190#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
191 FTIM0_NOR_TEADC(0x5) | \
192 FTIM0_NOR_TAVDS(0x0) | \
193 FTIM0_NOR_TEAHC(0x5))
194#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
195 FTIM1_NOR_TRAD_NOR(0x1A) | \
196 FTIM1_NOR_TSEQRAD_NOR(0x13))
197#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
198 FTIM2_NOR_TCH(0x4) | \
199 FTIM2_NOR_TWP(0x1c) | \
200 FTIM2_NOR_TWPH(0x0e))
201#define CONFIG_SYS_NOR_FTIM3 0
202
203#define CONFIG_FLASH_CFI_DRIVER
204#define CONFIG_SYS_FLASH_CFI
205#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
206#define CONFIG_SYS_FLASH_QUIET_TEST
207#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
208
209#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
210#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
211#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
212#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
213
214#define CONFIG_SYS_FLASH_EMPTY_INFO
215#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
216
217#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800218#define CONFIG_SYS_WRITE_SWAPPED_DATA
Alison Wangd612f0a2014-12-09 17:38:02 +0800219#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800220
221/* CPLD */
222
223#define CONFIG_SYS_CPLD_BASE 0x7fb00000
224#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
225
226#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
227#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
228 CSPR_PORT_SIZE_8 | \
229 CSPR_MSEL_GPCM | \
230 CSPR_V)
231#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
232#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
233 CSOR_NOR_NOR_MODE_AVD_NOR | \
234 CSOR_NOR_TRHZ_80)
235
236/* CPLD Timing parameters for IFC GPCM */
237#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
238 FTIM0_GPCM_TEADC(0xf) | \
239 FTIM0_GPCM_TEAHC(0xf))
240#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
241 FTIM1_GPCM_TRAD(0x3f))
242#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
243 FTIM2_GPCM_TCH(0xf) | \
244 FTIM2_GPCM_TWP(0xff))
245#define CONFIG_SYS_FPGA_FTIM3 0x0
246#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
247#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
248#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
249#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
250#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
251#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
252#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
253#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
254#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
255#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
256#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
257#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
258#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
259#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
260#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
261#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
262
263/*
264 * Serial Port
265 */
Alison Wang55d53ab2015-01-04 15:30:59 +0800266#ifdef CONFIG_LPUART
Alison Wang55d53ab2015-01-04 15:30:59 +0800267#define CONFIG_LPUART_32B_REG
268#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800269#define CONFIG_CONS_INDEX 1
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800270#define CONFIG_SYS_NS16550_SERIAL
Bin Mengf833cd62016-01-13 19:38:59 -0800271#ifndef CONFIG_DM_SERIAL
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800272#define CONFIG_SYS_NS16550_REG_SIZE 1
Bin Mengf833cd62016-01-13 19:38:59 -0800273#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800274#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang55d53ab2015-01-04 15:30:59 +0800275#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800276
277#define CONFIG_BAUDRATE 115200
278
279/*
280 * I2C
281 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800282#define CONFIG_SYS_I2C
283#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200284#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
285#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700286#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800287
Alison Wang5175a282014-10-17 15:26:35 +0800288/* EEPROM */
Alison Wang5175a282014-10-17 15:26:35 +0800289#define CONFIG_ID_EEPROM
290#define CONFIG_SYS_I2C_EEPROM_NXID
291#define CONFIG_SYS_EEPROM_BUS_NUM 1
292#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
293#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
294#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
295#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
Alison Wang5175a282014-10-17 15:26:35 +0800296
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800297/*
298 * MMC
299 */
300#define CONFIG_MMC
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800301#define CONFIG_FSL_ESDHC
302#define CONFIG_GENERIC_MMC
303
Alison Wang8251ed22014-12-09 17:37:34 +0800304#define CONFIG_DOS_PARTITION
305
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530306/* SPI */
Alison Wang947cee12015-10-15 17:54:40 +0800307#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530308/* QSPI */
Alison Wangd612f0a2014-12-09 17:38:02 +0800309#define QSPI0_AMBA_BASE 0x40000000
310#define FSL_QSPI_FLASH_SIZE (1 << 24)
311#define FSL_QSPI_FLASH_NUM 2
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530312
Yao Yuan03d1d562015-09-15 18:28:20 +0800313/* DSPI */
Yao Yuan03d1d562015-09-15 18:28:20 +0800314#endif
315
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530316/* DM SPI */
317#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
Haikun Wang9dd3d3c2015-06-27 21:46:13 +0530318#define CONFIG_DM_SPI_FLASH
319#endif
Alison Wangd612f0a2014-12-09 17:38:02 +0800320
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800321/*
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800322 * Video
323 */
324#define CONFIG_FSL_DCU_FB
325
326#ifdef CONFIG_FSL_DCU_FB
327#define CONFIG_VIDEO
328#define CONFIG_CMD_BMP
329#define CONFIG_CFB_CONSOLE
330#define CONFIG_VGA_AS_SINGLE_DEVICE
331#define CONFIG_VIDEO_LOGO
332#define CONFIG_VIDEO_BMP_LOGO
Alison Wangf8008f12016-03-08 11:59:59 +0800333#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Wang Huanb4ecc8c2014-09-05 13:52:50 +0800334
335#define CONFIG_FSL_DCU_SII9022A
336#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
337#define CONFIG_SYS_I2C_DVI_ADDR 0x39
338#endif
339
340/*
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800341 * eTSEC
342 */
343#define CONFIG_TSEC_ENET
344
345#ifdef CONFIG_TSEC_ENET
346#define CONFIG_MII
347#define CONFIG_MII_DEFAULT_TSEC 1
348#define CONFIG_TSEC1 1
349#define CONFIG_TSEC1_NAME "eTSEC1"
350#define CONFIG_TSEC2 1
351#define CONFIG_TSEC2_NAME "eTSEC2"
352#define CONFIG_TSEC3 1
353#define CONFIG_TSEC3_NAME "eTSEC3"
354
355#define TSEC1_PHY_ADDR 2
356#define TSEC2_PHY_ADDR 0
357#define TSEC3_PHY_ADDR 1
358
359#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
360#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
361#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
362
363#define TSEC1_PHYIDX 0
364#define TSEC2_PHYIDX 0
365#define TSEC3_PHYIDX 0
366
367#define CONFIG_ETHPRIME "eTSEC1"
368
369#define CONFIG_PHY_GIGE
370#define CONFIG_PHYLIB
371#define CONFIG_PHY_ATHEROS
372
373#define CONFIG_HAS_ETH0
374#define CONFIG_HAS_ETH1
375#define CONFIG_HAS_ETH2
376#endif
377
Minghuan Lianda419022014-10-31 13:43:44 +0800378/* PCIe */
379#define CONFIG_PCI /* Enable PCI/PCIE */
380#define CONFIG_PCIE1 /* PCIE controler 1 */
381#define CONFIG_PCIE2 /* PCIE controler 2 */
382#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
383#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
384
Minghuan Lian180b8682015-01-21 17:29:19 +0800385#define CONFIG_SYS_PCI_64BIT
386
387#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
388#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
389#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
390#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
391
392#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
393#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
394#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
395
396#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
397#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
398#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
399
400#ifdef CONFIG_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800401#define CONFIG_PCI_PNP
Minghuan Lian180b8682015-01-21 17:29:19 +0800402#define CONFIG_PCI_SCAN_SHOW
403#define CONFIG_CMD_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800404#endif
405
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800406#define CONFIG_CMDLINE_TAG
407#define CONFIG_CMDLINE_EDITING
Alison Wang8415bb62014-12-03 15:00:48 +0800408
Xiubo Li1a2826f2014-11-21 17:40:57 +0800409#define CONFIG_ARMV7_NONSEC
410#define CONFIG_ARMV7_VIRT
411#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu435acd82015-10-26 19:47:41 +0800412#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800413#define CONFIG_SMP_PEN_ADDR 0x01ee0200
414#define CONFIG_TIMER_CLK_FREQ 12500000
Xiubo Li1a2826f2014-11-21 17:40:57 +0800415
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800416#define CONFIG_HWCONFIG
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800417#define HWCONFIG_BUFFER_SIZE 256
418
419#define CONFIG_FSL_DEVICE_DISABLE
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800420
421#define CONFIG_BOOTDELAY 3
422
Alison Wang55d53ab2015-01-04 15:30:59 +0800423#ifdef CONFIG_LPUART
424#define CONFIG_EXTRA_ENV_SETTINGS \
425 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800426 "initrd_high=0xffffffff\0" \
427 "fdt_high=0xffffffff\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800428#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800429#define CONFIG_EXTRA_ENV_SETTINGS \
430 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wang7ff71662015-10-26 14:08:28 +0800431 "initrd_high=0xffffffff\0" \
432 "fdt_high=0xffffffff\0"
Alison Wang55d53ab2015-01-04 15:30:59 +0800433#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800434
435/*
436 * Miscellaneous configurable options
437 */
438#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800439#define CONFIG_AUTO_COMPLETE
440#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
441#define CONFIG_SYS_PBSIZE \
442 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
443#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
444#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
445
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800446#define CONFIG_SYS_MEMTEST_START 0x80000000
447#define CONFIG_SYS_MEMTEST_END 0x9fffffff
448
449#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800450
Xiubo Li660673a2014-11-21 17:40:59 +0800451#define CONFIG_LS102XA_STREAM_ID
452
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800453/*
454 * Stack sizes
455 * The stack sizes are set up in start.S using the settings below
456 */
457#define CONFIG_STACKSIZE (30 * 1024)
458
459#define CONFIG_SYS_INIT_SP_OFFSET \
460 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
461#define CONFIG_SYS_INIT_SP_ADDR \
462 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
463
Alison Wang8415bb62014-12-03 15:00:48 +0800464#ifdef CONFIG_SPL_BUILD
465#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
466#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800467#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang8415bb62014-12-03 15:00:48 +0800468#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800469
Zhao Qiang713bf942015-09-16 16:20:42 +0800470#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
Zhao Qiangeaa859e2014-09-26 16:25:33 +0800471
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800472/*
473 * Environment
474 */
475#define CONFIG_ENV_OVERWRITE
476
Alison Wang8415bb62014-12-03 15:00:48 +0800477#if defined(CONFIG_SD_BOOT)
478#define CONFIG_ENV_OFFSET 0x100000
479#define CONFIG_ENV_IS_IN_MMC
480#define CONFIG_SYS_MMC_ENV_DEV 0
481#define CONFIG_ENV_SIZE 0x20000
Alison Wangd612f0a2014-12-09 17:38:02 +0800482#elif defined(CONFIG_QSPI_BOOT)
483#define CONFIG_ENV_IS_IN_SPI_FLASH
484#define CONFIG_ENV_SIZE 0x2000
485#define CONFIG_ENV_OFFSET 0x100000
486#define CONFIG_ENV_SECT_SIZE 0x10000
Alison Wang8415bb62014-12-03 15:00:48 +0800487#else
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800488#define CONFIG_ENV_IS_IN_FLASH
489#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
490#define CONFIG_ENV_SIZE 0x20000
491#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Alison Wang8415bb62014-12-03 15:00:48 +0800492#endif
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800493
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530494#define CONFIG_MISC_INIT_R
495
496/* Hash command with SHA acceleration supported in hardware */
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530497#ifdef CONFIG_FSL_CAAM
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530498#define CONFIG_CMD_HASH
499#define CONFIG_SHA_HW_ACCEL
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530500#endif
501
502#include <asm/fsl_secure_boot.h>
Alison Wangcc7b8b92016-01-15 15:29:32 +0800503#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530504
Wang Huanc8a7d9d2014-09-05 13:52:45 +0800505#endif