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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk2262cfe2002-11-18 00:14:45 +00002/*
Graeme Russdbf71152011-04-13 19:43:26 +10003 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
5 *
wdenk2262cfe2002-11-18 00:14:45 +00006 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02007 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk8bde7f72003-06-27 21:31:46 +00008 *
wdenk2262cfe2002-11-18 00:14:45 +00009 * (C) Copyright 2002
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
12 *
13 * (C) Copyright 2002
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
16 *
Bin Meng52f952b2014-11-09 22:18:56 +080017 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
wdenk2262cfe2002-11-18 00:14:45 +000019 */
20
wdenk2262cfe2002-11-18 00:14:45 +000021#include <common.h>
22#include <command.h>
Simon Glass9edefc22019-11-14 12:57:37 -070023#include <cpu_func.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080024#include <dm.h>
Simon Glass200182a2014-10-10 08:21:55 -060025#include <errno.h>
Simon Glass35a3f872019-12-28 10:44:56 -070026#include <init.h>
Simon Glass200182a2014-10-10 08:21:55 -060027#include <malloc.h>
Bin Mengd8906c12016-06-08 05:07:38 -070028#include <syscon.h>
Simon Glass3cabcf92020-04-08 16:57:35 -060029#include <acpi/acpi_s3.h>
Simon Glass776cc202020-04-08 16:57:36 -060030#include <acpi/acpi_table.h>
Bin Menga0609a82018-07-18 21:42:15 -070031#include <asm/acpi.h>
Stefan Reinauer095593c2012-12-02 04:49:50 +000032#include <asm/control_regs.h>
Bin Mengd19c9072016-05-11 07:45:01 -070033#include <asm/coreboot_tables.h>
Simon Glass200182a2014-10-10 08:21:55 -060034#include <asm/cpu.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080035#include <asm/lapic.h>
Simon Glasse77b62e2016-03-11 22:07:11 -070036#include <asm/microcode.h>
Bin Meng6e6f4ce2015-06-17 11:15:36 +080037#include <asm/mp.h>
Bin Meng0c2b7ee2016-05-11 07:45:00 -070038#include <asm/mrccache.h>
Bin Meng43dd22f2015-07-06 16:31:30 +080039#include <asm/msr.h>
40#include <asm/mtrr.h>
Simon Glassa49e3c72014-11-12 22:42:26 -070041#include <asm/post.h>
Graeme Russc53fd2b2011-02-12 15:11:30 +110042#include <asm/processor.h>
Graeme Russ0c24c9c2011-02-12 15:11:32 +110043#include <asm/processor-flags.h>
Graeme Russ3f5f18d2008-12-07 10:29:02 +110044#include <asm/interrupt.h>
Bin Meng5e2400e2015-04-24 18:10:04 +080045#include <asm/tables.h>
Gabe Black60a9b6b2011-11-16 23:32:50 +000046#include <linux/compiler.h>
wdenk2262cfe2002-11-18 00:14:45 +000047
Bin Meng52f952b2014-11-09 22:18:56 +080048DECLARE_GLOBAL_DATA_PTR;
49
Simon Glasscaca13f2019-12-06 21:41:51 -070050#ifndef CONFIG_TPL_BUILD
Bin Meng52f952b2014-11-09 22:18:56 +080051static const char *const x86_vendor_name[] = {
52 [X86_VENDOR_INTEL] = "Intel",
53 [X86_VENDOR_CYRIX] = "Cyrix",
54 [X86_VENDOR_AMD] = "AMD",
55 [X86_VENDOR_UMC] = "UMC",
56 [X86_VENDOR_NEXGEN] = "NexGen",
57 [X86_VENDOR_CENTAUR] = "Centaur",
58 [X86_VENDOR_RISE] = "Rise",
59 [X86_VENDOR_TRANSMETA] = "Transmeta",
60 [X86_VENDOR_NSC] = "NSC",
61 [X86_VENDOR_SIS] = "SiS",
62};
Simon Glasscaca13f2019-12-06 21:41:51 -070063#endif
Bin Meng52f952b2014-11-09 22:18:56 +080064
Gabe Blackf30fc4d2012-10-20 12:33:10 +000065int __weak x86_cleanup_before_linux(void)
66{
Simon Glass79497032013-04-17 16:13:35 +000067#ifdef CONFIG_BOOTSTAGE_STASH
Simon Glassee2b2432015-03-02 17:04:37 -070068 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
Simon Glass79497032013-04-17 16:13:35 +000069 CONFIG_BOOTSTAGE_STASH_SIZE);
70#endif
71
Gabe Blackf30fc4d2012-10-20 12:33:10 +000072 return 0;
73}
74
Graeme Russd6532442011-12-27 22:46:43 +110075int x86_init_cache(void)
76{
77 enable_caches();
78
wdenk2262cfe2002-11-18 00:14:45 +000079 return 0;
80}
Graeme Russd6532442011-12-27 22:46:43 +110081int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
wdenk2262cfe2002-11-18 00:14:45 +000082
Graeme Russ717979f2011-11-08 02:33:13 +000083void flush_cache(unsigned long dummy1, unsigned long dummy2)
wdenk2262cfe2002-11-18 00:14:45 +000084{
85 asm("wbinvd\n");
wdenk2262cfe2002-11-18 00:14:45 +000086}
Graeme Russ3f5f18d2008-12-07 10:29:02 +110087
Stefan Reinauer095593c2012-12-02 04:49:50 +000088/* Define these functions to allow ehch-hcd to function */
89void flush_dcache_range(unsigned long start, unsigned long stop)
90{
91}
92
93void invalidate_dcache_range(unsigned long start, unsigned long stop)
94{
95}
Simon Glass89371402013-02-28 19:26:11 +000096
97void dcache_enable(void)
98{
99 enable_caches();
100}
101
102void dcache_disable(void)
103{
104 disable_caches();
105}
106
107void icache_enable(void)
108{
109}
110
111void icache_disable(void)
112{
113}
114
115int icache_status(void)
116{
117 return 1;
118}
Simon Glass7bddac92014-10-10 08:21:52 -0600119
Simon Glasscaca13f2019-12-06 21:41:51 -0700120#ifndef CONFIG_TPL_BUILD
Bin Meng52f952b2014-11-09 22:18:56 +0800121const char *cpu_vendor_name(int vendor)
122{
123 const char *name;
124 name = "<invalid cpu vendor>";
Heinrich Schuchardt39670c32017-11-20 19:45:56 +0100125 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
126 x86_vendor_name[vendor])
Bin Meng52f952b2014-11-09 22:18:56 +0800127 name = x86_vendor_name[vendor];
128
129 return name;
130}
Simon Glasscaca13f2019-12-06 21:41:51 -0700131#endif
Bin Meng52f952b2014-11-09 22:18:56 +0800132
Simon Glass727c1a92014-11-10 18:00:26 -0700133char *cpu_get_name(char *name)
Bin Meng52f952b2014-11-09 22:18:56 +0800134{
Simon Glass727c1a92014-11-10 18:00:26 -0700135 unsigned int *name_as_ints = (unsigned int *)name;
Bin Meng52f952b2014-11-09 22:18:56 +0800136 struct cpuid_result regs;
Simon Glass727c1a92014-11-10 18:00:26 -0700137 char *ptr;
Bin Meng52f952b2014-11-09 22:18:56 +0800138 int i;
139
Simon Glass727c1a92014-11-10 18:00:26 -0700140 /* This bit adds up to 48 bytes */
Bin Meng52f952b2014-11-09 22:18:56 +0800141 for (i = 0; i < 3; i++) {
142 regs = cpuid(0x80000002 + i);
143 name_as_ints[i * 4 + 0] = regs.eax;
144 name_as_ints[i * 4 + 1] = regs.ebx;
145 name_as_ints[i * 4 + 2] = regs.ecx;
146 name_as_ints[i * 4 + 3] = regs.edx;
147 }
Simon Glass727c1a92014-11-10 18:00:26 -0700148 name[CPU_MAX_NAME_LEN - 1] = '\0';
Bin Meng52f952b2014-11-09 22:18:56 +0800149
150 /* Skip leading spaces. */
Simon Glass727c1a92014-11-10 18:00:26 -0700151 ptr = name;
152 while (*ptr == ' ')
153 ptr++;
Bin Meng52f952b2014-11-09 22:18:56 +0800154
Simon Glass727c1a92014-11-10 18:00:26 -0700155 return ptr;
Bin Meng52f952b2014-11-09 22:18:56 +0800156}
157
Simon Glass727c1a92014-11-10 18:00:26 -0700158int default_print_cpuinfo(void)
Simon Glass92cc94a2014-10-10 08:21:54 -0600159{
Bin Meng52f952b2014-11-09 22:18:56 +0800160 printf("CPU: %s, vendor %s, device %xh\n",
161 cpu_has_64bit() ? "x86_64" : "x86",
162 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
Simon Glass92cc94a2014-10-10 08:21:54 -0600163
Bin Mengb7279612017-04-21 07:24:32 -0700164#ifdef CONFIG_HAVE_ACPI_RESUME
165 debug("ACPI previous sleep state: %s\n",
166 acpi_ss_string(gd->arch.prev_sleep_state));
167#endif
168
Simon Glass92cc94a2014-10-10 08:21:54 -0600169 return 0;
170}
Simon Glass200182a2014-10-10 08:21:55 -0600171
Simon Glassa49e3c72014-11-12 22:42:26 -0700172void show_boot_progress(int val)
173{
Simon Glassa49e3c72014-11-12 22:42:26 -0700174 outb(val, POST_PORT);
175}
Bin Meng5e2400e2015-04-24 18:10:04 +0800176
Bin Meng1ab2c012018-06-17 05:57:53 -0700177#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
Bin Meng1e2f7b92016-05-11 07:44:56 -0700178/*
179 * Implement a weak default function for boards that optionally
180 * need to clean up the system before jumping to the kernel.
181 */
182__weak void board_final_cleanup(void)
183{
184}
185
Bin Meng5e2400e2015-04-24 18:10:04 +0800186int last_stage_init(void)
187{
Bin Meng474a62b2018-07-18 21:42:16 -0700188 struct acpi_fadt __maybe_unused *fadt;
189
Bin Mengbffd7982017-04-21 07:24:41 -0700190 board_final_cleanup();
191
Bin Meng474a62b2018-07-18 21:42:16 -0700192#ifdef CONFIG_HAVE_ACPI_RESUME
193 fadt = acpi_find_fadt();
Bin Meng3a34cae2017-04-21 07:24:37 -0700194
Bin Meng474a62b2018-07-18 21:42:16 -0700195 if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
Bin Meng0f4e2582017-04-21 07:24:44 -0700196 acpi_resume(fadt);
Bin Meng3a34cae2017-04-21 07:24:37 -0700197#endif
198
Bin Meng5e2400e2015-04-24 18:10:04 +0800199 write_tables();
200
Bin Meng474a62b2018-07-18 21:42:16 -0700201#ifdef CONFIG_GENERATE_ACPI_TABLE
202 fadt = acpi_find_fadt();
203
204 /* Don't touch ACPI hardware on HW reduced platforms */
205 if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
206 /*
207 * Other than waiting for OSPM to request us to switch to ACPI
208 * mode, do it by ourselves, since SMI will not be triggered.
209 */
210 enter_acpi_mode(fadt->pm1a_cnt_blk);
211 }
212#endif
213
Bin Meng5e2400e2015-04-24 18:10:04 +0800214 return 0;
215}
216#endif
Simon Glassbcb0c612015-04-29 22:26:01 -0600217
Simon Glassafd5d502016-01-17 16:11:28 -0700218static int x86_init_cpus(void)
Simon Glassbcb0c612015-04-29 22:26:01 -0600219{
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800220#ifdef CONFIG_SMP
221 debug("Init additional CPUs\n");
222 x86_mp_init();
Bin Mengc77b8912015-07-22 01:21:12 -0700223#else
224 struct udevice *dev;
225
226 /*
227 * This causes the cpu-x86 driver to be probed.
228 * We don't check return value here as we want to allow boards
229 * which have not been converted to use cpu uclass driver to boot.
230 */
231 uclass_first_device(UCLASS_CPU, &dev);
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800232#endif
233
Simon Glassbcb0c612015-04-29 22:26:01 -0600234 return 0;
235}
236
237int cpu_init_r(void)
238{
Simon Glassac643e02016-01-17 16:11:30 -0700239 struct udevice *dev;
240 int ret;
241
Simon Glass526aabe2020-04-26 09:12:55 -0600242 if (!ll_boot_init()) {
243 uclass_first_device(UCLASS_PCI, &dev);
Simon Glassac643e02016-01-17 16:11:30 -0700244 return 0;
Simon Glass526aabe2020-04-26 09:12:55 -0600245 }
Simon Glassac643e02016-01-17 16:11:30 -0700246
247 ret = x86_init_cpus();
248 if (ret)
249 return ret;
250
251 /*
252 * Set up the northbridge, PCH and LPC if available. Note that these
253 * may have had some limited pre-relocation init if they were probed
254 * before relocation, but this is post relocation.
255 */
256 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
257 uclass_first_device(UCLASS_PCH, &dev);
258 uclass_first_device(UCLASS_LPC, &dev);
Simon Glasse49ccea2015-08-04 12:34:00 -0600259
Bin Mengd8906c12016-06-08 05:07:38 -0700260 /* Set up pin control if available */
261 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
262 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
263
Simon Glasse49ccea2015-08-04 12:34:00 -0600264 return 0;
Simon Glassbcb0c612015-04-29 22:26:01 -0600265}
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700266
267#ifndef CONFIG_EFI_STUB
268int reserve_arch(void)
269{
270#ifdef CONFIG_ENABLE_MRC_CACHE
Bin Mengd19c9072016-05-11 07:45:01 -0700271 mrccache_reserve();
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700272#endif
Bin Mengd19c9072016-05-11 07:45:01 -0700273
274#ifdef CONFIG_SEABIOS
275 high_table_reserve();
276#endif
277
Bin Meng5ae5aa92017-04-21 07:24:47 -0700278#ifdef CONFIG_HAVE_ACPI_RESUME
279 acpi_s3_reserve();
280
281#ifdef CONFIG_HAVE_FSP
Bin Mengba658082017-04-21 07:24:39 -0700282 /*
283 * Save stack address to CMOS so that at next S3 boot,
284 * we can use it as the stack address for fsp_contiue()
285 */
286 fsp_save_s3_stack();
Bin Meng5ae5aa92017-04-21 07:24:47 -0700287#endif /* CONFIG_HAVE_FSP */
288#endif /* CONFIG_HAVE_ACPI_RESUME */
Bin Mengba658082017-04-21 07:24:39 -0700289
Bin Mengd19c9072016-05-11 07:45:01 -0700290 return 0;
Bin Meng0c2b7ee2016-05-11 07:45:00 -0700291}
292#endif