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wdenk2262cfe2002-11-18 00:14:45 +00001/*
Graeme Russdbf71152011-04-13 19:43:26 +10002 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
4 *
wdenk2262cfe2002-11-18 00:14:45 +00005 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02006 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk8bde7f72003-06-27 21:31:46 +00007 *
wdenk2262cfe2002-11-18 00:14:45 +00008 * (C) Copyright 2002
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
11 *
12 * (C) Copyright 2002
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Alex Zuepke <azu@sysgo.de>
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
wdenk2262cfe2002-11-18 00:14:45 +000035#include <common.h>
36#include <command.h>
Stefan Reinauer095593c2012-12-02 04:49:50 +000037#include <asm/control_regs.h>
Graeme Russc53fd2b2011-02-12 15:11:30 +110038#include <asm/processor.h>
Graeme Russ0c24c9c2011-02-12 15:11:32 +110039#include <asm/processor-flags.h>
Graeme Russ3f5f18d2008-12-07 10:29:02 +110040#include <asm/interrupt.h>
Gabe Black60a9b6b2011-11-16 23:32:50 +000041#include <linux/compiler.h>
wdenk2262cfe2002-11-18 00:14:45 +000042
Graeme Russdbf71152011-04-13 19:43:26 +100043/*
44 * Constructor for a conventional segment GDT (or LDT) entry
45 * This is a macro so it can be used in initialisers
46 */
Graeme Russ59c6d0e2010-10-07 20:03:21 +110047#define GDT_ENTRY(flags, base, limit) \
48 ((((base) & 0xff000000ULL) << (56-24)) | \
49 (((flags) & 0x0000f0ffULL) << 40) | \
50 (((limit) & 0x000f0000ULL) << (48-16)) | \
51 (((base) & 0x00ffffffULL) << 16) | \
52 (((limit) & 0x0000ffffULL)))
53
Graeme Russ59c6d0e2010-10-07 20:03:21 +110054struct gdt_ptr {
55 u16 len;
56 u32 ptr;
Graeme Russ717979f2011-11-08 02:33:13 +000057} __packed;
Graeme Russ59c6d0e2010-10-07 20:03:21 +110058
Graeme Russ74bfbe12011-12-29 21:45:33 +110059static void load_ds(u32 segment)
Graeme Russ59c6d0e2010-10-07 20:03:21 +110060{
Graeme Russ74bfbe12011-12-29 21:45:33 +110061 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
62}
Graeme Russ59c6d0e2010-10-07 20:03:21 +110063
Graeme Russ74bfbe12011-12-29 21:45:33 +110064static void load_es(u32 segment)
65{
66 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
67}
Graeme Russ59c6d0e2010-10-07 20:03:21 +110068
Graeme Russ74bfbe12011-12-29 21:45:33 +110069static void load_fs(u32 segment)
70{
71 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
72}
73
74static void load_gs(u32 segment)
75{
76 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
77}
78
79static void load_ss(u32 segment)
80{
81 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
82}
83
84static void load_gdt(const u64 *boot_gdt, u16 num_entries)
85{
86 struct gdt_ptr gdt;
87
88 gdt.len = (num_entries * 8) - 1;
89 gdt.ptr = (u32)boot_gdt;
90
91 asm volatile("lgdtl %0\n" : : "m" (gdt));
Graeme Russ59c6d0e2010-10-07 20:03:21 +110092}
93
Graeme Russ9e6c5722011-12-31 22:58:15 +110094void setup_gdt(gd_t *id, u64 *gdt_addr)
95{
96 /* CS: code, read/execute, 4 GB, base 0 */
97 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
98
99 /* DS: data, read/write, 4 GB, base 0 */
100 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
101
102 /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
Simon Glass5a35e6c2012-12-13 20:48:41 +0000103 id->arch.gd_addr = id;
Simon Glass0cecc3b2012-12-13 20:48:42 +0000104 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
Simon Glass5a35e6c2012-12-13 20:48:41 +0000105 (ulong)&id->arch.gd_addr, 0xfffff);
Graeme Russ9e6c5722011-12-31 22:58:15 +1100106
107 /* 16-bit CS: code, read/execute, 64 kB, base 0 */
108 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff);
109
110 /* 16-bit DS: data, read/write, 64 kB, base 0 */
111 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff);
112
113 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
114 load_ds(X86_GDT_ENTRY_32BIT_DS);
115 load_es(X86_GDT_ENTRY_32BIT_DS);
116 load_gs(X86_GDT_ENTRY_32BIT_DS);
117 load_ss(X86_GDT_ENTRY_32BIT_DS);
118 load_fs(X86_GDT_ENTRY_32BIT_FS);
119}
120
Gabe Blackf30fc4d2012-10-20 12:33:10 +0000121int __weak x86_cleanup_before_linux(void)
122{
Simon Glass79497032013-04-17 16:13:35 +0000123#ifdef CONFIG_BOOTSTAGE_STASH
124 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH,
125 CONFIG_BOOTSTAGE_STASH_SIZE);
126#endif
127
Gabe Blackf30fc4d2012-10-20 12:33:10 +0000128 return 0;
129}
130
Graeme Russ0ea76e92011-02-12 15:11:35 +1100131int x86_cpu_init_f(void)
wdenk2262cfe2002-11-18 00:14:45 +0000132{
Graeme Russ0c24c9c2011-02-12 15:11:32 +1100133 const u32 em_rst = ~X86_CR0_EM;
134 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
135
wdenk7a8e9bed2003-05-31 18:35:21 +0000136 /* initialize FPU, reset EM, set MP and NE */
137 asm ("fninit\n" \
Graeme Russ0c24c9c2011-02-12 15:11:32 +1100138 "movl %%cr0, %%eax\n" \
139 "andl %0, %%eax\n" \
140 "orl %1, %%eax\n" \
141 "movl %%eax, %%cr0\n" \
142 : : "i" (em_rst), "i" (mp_ne_set) : "eax");
wdenk8bde7f72003-06-27 21:31:46 +0000143
Graeme Russ1c409bc2009-11-24 20:04:21 +1100144 return 0;
145}
Graeme Russ0ea76e92011-02-12 15:11:35 +1100146int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
Graeme Russ1c409bc2009-11-24 20:04:21 +1100147
Graeme Russ0ea76e92011-02-12 15:11:35 +1100148int x86_cpu_init_r(void)
Graeme Russ1c409bc2009-11-24 20:04:21 +1100149{
Graeme Russd6532442011-12-27 22:46:43 +1100150 /* Initialize core interrupt and exception functionality of CPU */
151 cpu_init_interrupts();
152 return 0;
153}
154int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
155
156void x86_enable_caches(void)
157{
Stefan Reinauer095593c2012-12-02 04:49:50 +0000158 unsigned long cr0;
Graeme Russ0ea76e92011-02-12 15:11:35 +1100159
Stefan Reinauer095593c2012-12-02 04:49:50 +0000160 cr0 = read_cr0();
161 cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
162 write_cr0(cr0);
163 wbinvd();
Graeme Russd6532442011-12-27 22:46:43 +1100164}
165void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
Graeme Russ0ea76e92011-02-12 15:11:35 +1100166
Stefan Reinauer095593c2012-12-02 04:49:50 +0000167void x86_disable_caches(void)
168{
169 unsigned long cr0;
170
171 cr0 = read_cr0();
172 cr0 |= X86_CR0_NW | X86_CR0_CD;
173 wbinvd();
174 write_cr0(cr0);
175 wbinvd();
176}
177void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
178
Graeme Russd6532442011-12-27 22:46:43 +1100179int x86_init_cache(void)
180{
181 enable_caches();
182
wdenk2262cfe2002-11-18 00:14:45 +0000183 return 0;
184}
Graeme Russd6532442011-12-27 22:46:43 +1100185int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
wdenk2262cfe2002-11-18 00:14:45 +0000186
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200187int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
wdenk2262cfe2002-11-18 00:14:45 +0000188{
Graeme Russ717979f2011-11-08 02:33:13 +0000189 printf("resetting ...\n");
Graeme Russdbf71152011-04-13 19:43:26 +1000190
191 /* wait 50 ms */
192 udelay(50000);
wdenk2262cfe2002-11-18 00:14:45 +0000193 disable_interrupts();
194 reset_cpu(0);
195
196 /*NOTREACHED*/
197 return 0;
198}
199
Graeme Russ717979f2011-11-08 02:33:13 +0000200void flush_cache(unsigned long dummy1, unsigned long dummy2)
wdenk2262cfe2002-11-18 00:14:45 +0000201{
202 asm("wbinvd\n");
wdenk2262cfe2002-11-18 00:14:45 +0000203}
Graeme Russ3f5f18d2008-12-07 10:29:02 +1100204
205void __attribute__ ((regparm(0))) generate_gpf(void);
206
207/* segment 0x70 is an arbitrary segment which does not exist */
208asm(".globl generate_gpf\n"
Graeme Russ717979f2011-11-08 02:33:13 +0000209 ".hidden generate_gpf\n"
210 ".type generate_gpf, @function\n"
211 "generate_gpf:\n"
212 "ljmp $0x70, $0x47114711\n");
Graeme Russ3f5f18d2008-12-07 10:29:02 +1100213
214void __reset_cpu(ulong addr)
215{
Graeme Russfea25722011-04-13 19:43:28 +1000216 printf("Resetting using x86 Triple Fault\n");
Graeme Russ717979f2011-11-08 02:33:13 +0000217 set_vector(13, generate_gpf); /* general protection fault handler */
218 set_vector(8, generate_gpf); /* double fault handler */
219 generate_gpf(); /* start the show */
Graeme Russ3f5f18d2008-12-07 10:29:02 +1100220}
221void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
Stefan Reinauer095593c2012-12-02 04:49:50 +0000222
223int dcache_status(void)
224{
225 return !(read_cr0() & 0x40000000);
226}
227
228/* Define these functions to allow ehch-hcd to function */
229void flush_dcache_range(unsigned long start, unsigned long stop)
230{
231}
232
233void invalidate_dcache_range(unsigned long start, unsigned long stop)
234{
235}
Simon Glass89371402013-02-28 19:26:11 +0000236
237void dcache_enable(void)
238{
239 enable_caches();
240}
241
242void dcache_disable(void)
243{
244 disable_caches();
245}
246
247void icache_enable(void)
248{
249}
250
251void icache_disable(void)
252{
253}
254
255int icache_status(void)
256{
257 return 1;
258}