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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 7f2e60f1ba8e1a44640c4e38a3f0ae009361b1b4 / . / drivers / pinctrl / renesas / pfc-r8a77965.c
blob: 2523904aec1215e715d9f50e42b23f24fab23c4b [file] [log] [blame]
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15#include <common.h>
16#include <dm.h>
17#include <errno.h>
18#include <dm/pinctrl.h>
19#include <linux/kernel.h>
20
21#include "sh_pfc.h"
22
23#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
24 SH_PFC_PIN_CFG_PULL_UP | \
25 SH_PFC_PIN_CFG_PULL_DOWN)
26
27#define CPU_ALL_PORT(fn, sfx) \
28 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
37 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
40/*
41 * F_() : just information
42 * FM() : macro for FN_xxx / xxx_MARK
43 */
44
45/* GPSR0 */
46#define GPSR0_15 F_(D15, IP7_11_8)
47#define GPSR0_14 F_(D14, IP7_7_4)
48#define GPSR0_13 F_(D13, IP7_3_0)
49#define GPSR0_12 F_(D12, IP6_31_28)
50#define GPSR0_11 F_(D11, IP6_27_24)
51#define GPSR0_10 F_(D10, IP6_23_20)
52#define GPSR0_9 F_(D9, IP6_19_16)
53#define GPSR0_8 F_(D8, IP6_15_12)
54#define GPSR0_7 F_(D7, IP6_11_8)
55#define GPSR0_6 F_(D6, IP6_7_4)
56#define GPSR0_5 F_(D5, IP6_3_0)
57#define GPSR0_4 F_(D4, IP5_31_28)
58#define GPSR0_3 F_(D3, IP5_27_24)
59#define GPSR0_2 F_(D2, IP5_23_20)
60#define GPSR0_1 F_(D1, IP5_19_16)
61#define GPSR0_0 F_(D0, IP5_15_12)
62
63/* GPSR1 */
64#define GPSR1_28 FM(CLKOUT)
65#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
66#define GPSR1_26 F_(WE1_N, IP5_7_4)
67#define GPSR1_25 F_(WE0_N, IP5_3_0)
68#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
69#define GPSR1_23 F_(RD_N, IP4_27_24)
70#define GPSR1_22 F_(BS_N, IP4_23_20)
71#define GPSR1_21 F_(CS1_N, IP4_19_16)
72#define GPSR1_20 F_(CS0_N, IP4_15_12)
73#define GPSR1_19 F_(A19, IP4_11_8)
74#define GPSR1_18 F_(A18, IP4_7_4)
75#define GPSR1_17 F_(A17, IP4_3_0)
76#define GPSR1_16 F_(A16, IP3_31_28)
77#define GPSR1_15 F_(A15, IP3_27_24)
78#define GPSR1_14 F_(A14, IP3_23_20)
79#define GPSR1_13 F_(A13, IP3_19_16)
80#define GPSR1_12 F_(A12, IP3_15_12)
81#define GPSR1_11 F_(A11, IP3_11_8)
82#define GPSR1_10 F_(A10, IP3_7_4)
83#define GPSR1_9 F_(A9, IP3_3_0)
84#define GPSR1_8 F_(A8, IP2_31_28)
85#define GPSR1_7 F_(A7, IP2_27_24)
86#define GPSR1_6 F_(A6, IP2_23_20)
87#define GPSR1_5 F_(A5, IP2_19_16)
88#define GPSR1_4 F_(A4, IP2_15_12)
89#define GPSR1_3 F_(A3, IP2_11_8)
90#define GPSR1_2 F_(A2, IP2_7_4)
91#define GPSR1_1 F_(A1, IP2_3_0)
92#define GPSR1_0 F_(A0, IP1_31_28)
93
94/* GPSR2 */
95#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
96#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
97#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
98#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
99#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
100#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
101#define GPSR2_8 F_(PWM2_A, IP1_27_24)
102#define GPSR2_7 F_(PWM1_A, IP1_23_20)
103#define GPSR2_6 F_(PWM0, IP1_19_16)
104#define GPSR2_5 F_(IRQ5, IP1_15_12)
105#define GPSR2_4 F_(IRQ4, IP1_11_8)
106#define GPSR2_3 F_(IRQ3, IP1_7_4)
107#define GPSR2_2 F_(IRQ2, IP1_3_0)
108#define GPSR2_1 F_(IRQ1, IP0_31_28)
109#define GPSR2_0 F_(IRQ0, IP0_27_24)
110
111/* GPSR3 */
112#define GPSR3_15 F_(SD1_WP, IP11_23_20)
113#define GPSR3_14 F_(SD1_CD, IP11_19_16)
114#define GPSR3_13 F_(SD0_WP, IP11_15_12)
115#define GPSR3_12 F_(SD0_CD, IP11_11_8)
116#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
117#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
118#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
119#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
120#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
121#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
122#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
123#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
124#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
125#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
126#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
127#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
128
129/* GPSR4 */
130#define GPSR4_17 F_(SD3_DS, IP11_7_4)
131#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
132#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
133#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
134#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
135#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
136#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
137#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
138#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
139#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
140#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
141#define GPSR4_6 F_(SD2_DS, IP9_27_24)
142#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
143#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
144#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
145#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
146#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
147#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
148
149/* GPSR5 */
150#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
151#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
152#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
153#define GPSR5_22 FM(MSIOF0_RXD)
154#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
155#define GPSR5_20 FM(MSIOF0_TXD)
156#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
157#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
158#define GPSR5_17 FM(MSIOF0_SCK)
159#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
160#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
161#define GPSR5_14 F_(HTX0, IP13_19_16)
162#define GPSR5_13 F_(HRX0, IP13_15_12)
163#define GPSR5_12 F_(HSCK0, IP13_11_8)
164#define GPSR5_11 F_(RX2_A, IP13_7_4)
165#define GPSR5_10 F_(TX2_A, IP13_3_0)
166#define GPSR5_9 F_(SCK2, IP12_31_28)
167#define GPSR5_8 F_(RTS1_N, IP12_27_24)
168#define GPSR5_7 F_(CTS1_N, IP12_23_20)
169#define GPSR5_6 F_(TX1_A, IP12_19_16)
170#define GPSR5_5 F_(RX1_A, IP12_15_12)
171#define GPSR5_4 F_(RTS0_N, IP12_11_8)
172#define GPSR5_3 F_(CTS0_N, IP12_7_4)
173#define GPSR5_2 F_(TX0, IP12_3_0)
174#define GPSR5_1 F_(RX0, IP11_31_28)
175#define GPSR5_0 F_(SCK0, IP11_27_24)
176
177/* GPSR6 */
178#define GPSR6_31 F_(GP6_31, IP18_7_4)
179#define GPSR6_30 F_(GP6_30, IP18_3_0)
180#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
181#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
182#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
183#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
184#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
185#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
186#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
187#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
188#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
189#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
190#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
191#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
192#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
193#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
194#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
195#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
196#define GPSR6_13 FM(SSI_SDATA5)
197#define GPSR6_12 FM(SSI_WS5)
198#define GPSR6_11 FM(SSI_SCK5)
199#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
200#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
201#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
202#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
203#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
204#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
205#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
206#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
207#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
208#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
209#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
210
211/* GPSR7 */
212#define GPSR7_3 FM(GP7_03)
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]213#define GPSR7_2 FM(GP7_02)
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]214#define GPSR7_1 FM(AVS2)
215#define GPSR7_0 FM(AVS1)
216
217
218/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
219#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246
247/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
248#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277
278/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
279#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313
314/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
315#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
336#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343
344/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
345#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]362#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]363#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
365#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
366#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
367#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
368#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
369#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
371#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
372
373#define PINMUX_GPSR \
374\
375 GPSR6_31 \
376 GPSR6_30 \
377 GPSR6_29 \
378 GPSR1_28 GPSR6_28 \
379 GPSR1_27 GPSR6_27 \
380 GPSR1_26 GPSR6_26 \
381 GPSR1_25 GPSR5_25 GPSR6_25 \
382 GPSR1_24 GPSR5_24 GPSR6_24 \
383 GPSR1_23 GPSR5_23 GPSR6_23 \
384 GPSR1_22 GPSR5_22 GPSR6_22 \
385 GPSR1_21 GPSR5_21 GPSR6_21 \
386 GPSR1_20 GPSR5_20 GPSR6_20 \
387 GPSR1_19 GPSR5_19 GPSR6_19 \
388 GPSR1_18 GPSR5_18 GPSR6_18 \
389 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
390 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
391GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
392GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
393GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
394GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
395GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
396GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
397GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
398GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
399GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
400GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
401GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
402GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
403GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
404GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
405GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
406GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
407
408#define PINMUX_IPSR \
409\
410FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
411FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
412FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
413FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
414FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
415FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
416FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
417FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
418\
419FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
420FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
421FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
422FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
423FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
424FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
425FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
426FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
427\
428FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
429FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
430FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
431FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
432FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
433FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
434FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
435FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
436\
437FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
438FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
439FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
440FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
441FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
442FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
443FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
444FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
445\
446FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
447FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
448FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
449FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
450FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
451FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
452FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
453FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
454
455/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
456#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
457#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
458#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
459#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
460#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
461#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
462#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
463#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
464#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
465#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
466#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
467#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
468#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
469#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
470#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
471#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
472#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]473#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]474
475/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
476#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
477#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
479#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
480#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
481#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
482#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
483#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
484#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
485#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
486#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
487#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
488#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
489#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
490#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
491#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
492#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
493#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
494#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
495#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
496#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
497#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
498
499/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
500#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
501#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
502#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
503#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
504#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
505#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]506#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]507#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
508#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
509#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]510#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
511#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]512#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
513
514#define PINMUX_MOD_SELS \
515\
516MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
517 MOD_SEL2_30 \
518 MOD_SEL1_29_28_27 MOD_SEL2_29 \
519MOD_SEL0_28_27 MOD_SEL2_28_27 \
520MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
521 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
522MOD_SEL0_23 MOD_SEL1_23_22_21 \
523MOD_SEL0_22 MOD_SEL2_22 \
524MOD_SEL0_21 MOD_SEL2_21 \
525MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
526MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
527MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
528 MOD_SEL2_17 \
529MOD_SEL0_16 MOD_SEL1_16 \
530 MOD_SEL1_15_14 \
531MOD_SEL0_14_13 \
532 MOD_SEL1_13 \
533MOD_SEL0_12 MOD_SEL1_12 \
534MOD_SEL0_11 MOD_SEL1_11 \
535MOD_SEL0_10 MOD_SEL1_10 \
536MOD_SEL0_9_8 MOD_SEL1_9 \
537MOD_SEL0_7_6 \
538 MOD_SEL1_6 \
539MOD_SEL0_5 MOD_SEL1_5 \
540MOD_SEL0_4_3 MOD_SEL1_4 \
541 MOD_SEL1_3 \
542 MOD_SEL1_2 \
543 MOD_SEL1_1 \
544 MOD_SEL1_0 MOD_SEL2_0
545
546/*
547 * These pins are not able to be muxed but have other properties
548 * that can be set, such as drive-strength or pull-up/pull-down enable.
549 */
550#define PINMUX_STATIC \
551 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
552 FM(QSPI0_IO2) FM(QSPI0_IO3) \
553 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
554 FM(QSPI1_IO2) FM(QSPI1_IO3) \
555 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
556 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
557 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
558 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
559 FM(PRESETOUT) \
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]560 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]561 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
562
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]563#define PINMUX_PHYS \
564 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
565
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]566enum {
567 PINMUX_RESERVED = 0,
568
569 PINMUX_DATA_BEGIN,
570 GP_ALL(DATA),
571 PINMUX_DATA_END,
572
573#define F_(x, y)
574#define FM(x) FN_##x,
575 PINMUX_FUNCTION_BEGIN,
576 GP_ALL(FN),
577 PINMUX_GPSR
578 PINMUX_IPSR
579 PINMUX_MOD_SELS
580 PINMUX_FUNCTION_END,
581#undef F_
582#undef FM
583
584#define F_(x, y)
585#define FM(x) x##_MARK,
586 PINMUX_MARK_BEGIN,
587 PINMUX_GPSR
588 PINMUX_IPSR
589 PINMUX_MOD_SELS
590 PINMUX_STATIC
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]591 PINMUX_PHYS
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]592 PINMUX_MARK_END,
593#undef F_
594#undef FM
595};
596
597static const u16 pinmux_data[] = {
598 PINMUX_DATA_GP_ALL(),
599
600 PINMUX_SINGLE(AVS1),
601 PINMUX_SINGLE(AVS2),
602 PINMUX_SINGLE(CLKOUT),
603 PINMUX_SINGLE(GP7_03),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]604 PINMUX_SINGLE(GP7_02),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]605 PINMUX_SINGLE(MSIOF0_RXD),
606 PINMUX_SINGLE(MSIOF0_SCK),
607 PINMUX_SINGLE(MSIOF0_TXD),
608 PINMUX_SINGLE(SSI_SCK5),
609 PINMUX_SINGLE(SSI_SDATA5),
610 PINMUX_SINGLE(SSI_WS5),
611
612 /* IPSR0 */
613 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
614 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
615
616 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
617 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
621 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
623
624 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
625 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
626 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
627 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
628
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]629 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
630 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
631 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
632 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]633
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]634 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
635 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
636 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
637 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]638
639 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
640 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
641 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
642 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
645 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
646
647 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
648 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
649 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
650 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
651 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
652 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
653 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
654
655 /* IPSR1 */
656 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
657 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
658 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
659 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
660 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
661 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
662
663 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
664 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
665 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
666 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
667 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
668 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
669
670 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
671 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
672 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
673 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
675 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
676
677 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
678 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
679 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
680 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
681 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
682 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
683 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
684
685 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
686 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
687 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
688 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
689
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]690 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
691 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
692 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
693 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
694 PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]695
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]696 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
697 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
698 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
699 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]700
701 PINMUX_IPSR_GPSR(IP1_31_28, A0),
702 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
703 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
704 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
705 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
706 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
707
708 /* IPSR2 */
709 PINMUX_IPSR_GPSR(IP2_3_0, A1),
710 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
711 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
712 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
713 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
714 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
715
716 PINMUX_IPSR_GPSR(IP2_7_4, A2),
717 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
718 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
719 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
720 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
721 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
722
723 PINMUX_IPSR_GPSR(IP2_11_8, A3),
724 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
725 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
726 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
727 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
728 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
729
730 PINMUX_IPSR_GPSR(IP2_15_12, A4),
731 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
732 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
733 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
734 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
735 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
736
737 PINMUX_IPSR_GPSR(IP2_19_16, A5),
738 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
739 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
740 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
741 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
742 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
743 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
744
745 PINMUX_IPSR_GPSR(IP2_23_20, A6),
746 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
747 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
749 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
750 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
751 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
752
753 PINMUX_IPSR_GPSR(IP2_27_24, A7),
754 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
755 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
757 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
758 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
759 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
760
761 PINMUX_IPSR_GPSR(IP2_31_28, A8),
762 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
763 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
765 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
766 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
767 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
768
769 /* IPSR3 */
770 PINMUX_IPSR_GPSR(IP3_3_0, A9),
771 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
774
775 PINMUX_IPSR_GPSR(IP3_7_4, A10),
776 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
777 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
778 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
779
780 PINMUX_IPSR_GPSR(IP3_11_8, A11),
781 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
782 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
783 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
784 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
785 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
786 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
787 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
788 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
789
790 PINMUX_IPSR_GPSR(IP3_15_12, A12),
791 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
792 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
793 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
794 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
795 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
796
797 PINMUX_IPSR_GPSR(IP3_19_16, A13),
798 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
799 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
800 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
801 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
802 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
803
804 PINMUX_IPSR_GPSR(IP3_23_20, A14),
805 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
806 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
807 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
808 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
809 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
810
811 PINMUX_IPSR_GPSR(IP3_27_24, A15),
812 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
813 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
814 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
815 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
816 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
817
818 PINMUX_IPSR_GPSR(IP3_31_28, A16),
819 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
820 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
821 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
822
823 /* IPSR4 */
824 PINMUX_IPSR_GPSR(IP4_3_0, A17),
825 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
826 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
827 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
828
829 PINMUX_IPSR_GPSR(IP4_7_4, A18),
830 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
831 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
832 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
833
834 PINMUX_IPSR_GPSR(IP4_11_8, A19),
835 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
836 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
837 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
838
839 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
840 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
841
842 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
843 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
844 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
845
846 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
847 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
848 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
850 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
851 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
852 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
853 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
854
855 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
856 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
857 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
859 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
860 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
861
862 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
863 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
864 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
865 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
866 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
867 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
868
869 /* IPSR5 */
870 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
871 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
872 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
873 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
874 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
875 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
876 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
877
878 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
879 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
880 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
881 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
882 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
883 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
884 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
885 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
886
887 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
888 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
889 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
890 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
891
892 PINMUX_IPSR_GPSR(IP5_15_12, D0),
893 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
894 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
896 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
897
898 PINMUX_IPSR_GPSR(IP5_19_16, D1),
899 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
900 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
901 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
902 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
903
904 PINMUX_IPSR_GPSR(IP5_23_20, D2),
905 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
906 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
907 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
908
909 PINMUX_IPSR_GPSR(IP5_27_24, D3),
910 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
911 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
912 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
913
914 PINMUX_IPSR_GPSR(IP5_31_28, D4),
915 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
917 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
918
919 /* IPSR6 */
920 PINMUX_IPSR_GPSR(IP6_3_0, D5),
921 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
922 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
923 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
924
925 PINMUX_IPSR_GPSR(IP6_7_4, D6),
926 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
927 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
928 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
929
930 PINMUX_IPSR_GPSR(IP6_11_8, D7),
931 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
932 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
933 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
934
935 PINMUX_IPSR_GPSR(IP6_15_12, D8),
936 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
937 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
938 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
939 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
940 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
941
942 PINMUX_IPSR_GPSR(IP6_19_16, D9),
943 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
944 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
945 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
946 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
947
948 PINMUX_IPSR_GPSR(IP6_23_20, D10),
949 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
950 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
955
956 PINMUX_IPSR_GPSR(IP6_27_24, D11),
957 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
958 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
960 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
961 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
962 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
963
964 PINMUX_IPSR_GPSR(IP6_31_28, D12),
965 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
966 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
970
971 /* IPSR7 */
972 PINMUX_IPSR_GPSR(IP7_3_0, D13),
973 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
974 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
975 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
976 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
977 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
978
979 PINMUX_IPSR_GPSR(IP7_7_4, D14),
980 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
981 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
985 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
986
987 PINMUX_IPSR_GPSR(IP7_11_8, D15),
988 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
989 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
990 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
991 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
992 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
993 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
994
995 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
996 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
998
999 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1000 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1002
1003 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1004 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1009 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1012
1013 /* IPSR8 */
1014 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1015 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1016 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1017 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1018
1019 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1020 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1021 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1022 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1023
1024 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1025 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1027
1028 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1029 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1030 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1031 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1032 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1033
1034 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1035 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1036 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1037 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1038 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1039 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1040
1041 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1042 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1043 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1044 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1045 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1046 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1047
1048 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1049 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1050 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1051 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1052 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1053 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1054
1055 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1056 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1057 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1058 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1059 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1060 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1061
1062 /* IPSR9 */
1063 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1064 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1065
1066 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1067 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1068
1069 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1070 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1071
1072 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1073 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1074
1075 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1076 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1077
1078 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1079 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1080
1081 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1082 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1083 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1084
1085 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1086 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1087
1088 /* IPSR10 */
1089 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1090 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1091
1092 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1093 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1094
1095 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1096 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1097
1098 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1099 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1100
1101 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1102 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1103
1104 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1105 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1106 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1107
1108 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1109 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1110 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1111
1112 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1113 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1114 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1115
1116 /* IPSR11 */
1117 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1118 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1119 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1120
1121 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1122 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1123
1124 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1125 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1126 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1127 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1128
1129 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1130 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1131 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1132
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1133 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1134 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1135 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1136 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1137
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1138 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1139 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1140 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1141 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1142
1143 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1144 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1145 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1146 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1147 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1148 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1149 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1150 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1151 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1152 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1153
1154 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1155 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1156 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1157 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1158 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1159
1160 /* IPSR12 */
1161 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1162 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1163 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1164 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1165 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1166
1167 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1168 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1169 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1170 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1171 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1172 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1173 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1174 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1175
1176 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1177 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1178 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1179 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1180 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1181 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1182 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1183 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1184
1185 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1187 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1188 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1189 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1190
1191 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1192 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1194 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1195 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1196
1197 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1198 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1199 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1200 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1201 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1202 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1203 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1204
1205 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1206 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1207 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1208 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1209 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1210 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1211 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1212
1213 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1214 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1215 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1216 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1217 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1218 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1219 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1220
1221 /* IPSR13 */
1222 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1223 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1224 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1225 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1226 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1227 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1228
1229 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1230 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1231 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1232 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1233 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1234 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1235
1236 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1237 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1238 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1239 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1240 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1241 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1242 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1243 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1244
1245 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1246 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1247 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1248 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1249 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1250 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1251
1252 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1253 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1254 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1255 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1256 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1257 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1258
1259 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1260 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1261 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1262 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1263 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1264 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1265 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1266 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1267
1268 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1269 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1270 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1271 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1272 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1273 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1274 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1275
1276 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1277 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1278 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1279 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1280
1281 /* IPSR14 */
1282 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1283 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1284 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1285 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1286 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1287 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1288 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1289 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1292 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1293 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1294 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1295 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1296 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1297 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1298 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1299
1300 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1301 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1302 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1303
1304 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1305 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1306 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1307 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1308
1309 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1310 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1311 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1312
1313 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1314 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1315
1316 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1317 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1318
1319 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1320 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1321
1322 /* IPSR15 */
1323 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1324
1325 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1326 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1327
1328 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1329 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1331
1332 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1333 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1334 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1335 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1336
1337 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1338 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1339 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1340 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1342 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1344
1345 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1346 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1347 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1348 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1350 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1352
1353 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1354 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1355 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1356 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1357 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1358 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1359 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1360
1361 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1362 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1363 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1364 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1365 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1366 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1367 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1368
1369 /* IPSR16 */
1370 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1371 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1372
1373 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1374 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1375
1376 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1377 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1378 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1379
1380 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1381 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1385 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1386 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1387
1388 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1389 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1395
1396 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1397 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1398 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1399 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1400 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1401 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1402 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1403 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1404
1405 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1406 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1407 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1408 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1409 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1410 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1411 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1412
1413 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1414 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1415 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1416 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1417 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1418 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1419 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1420 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1421
1422 /* IPSR17 */
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1423 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1424
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]1425 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1426 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1427 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1429 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1430
1431 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1432 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1433 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1434 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1435 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1436 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1437 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1438
1439 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1440 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1441 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1442 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1443 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1444 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1445
1446 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1447 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1448 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1449 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1450 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1451 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1452 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1453 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1454 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1455
1456 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1457 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1458 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1459 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1460 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1462 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1463 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1464 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1465
1466 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1467 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1468 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1469 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1472 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1474 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1475 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1476 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1477
1478 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1479 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1480 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1481 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1482 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1483 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1484 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1485 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1486 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1487
1488 /* IPSR18 */
1489 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1490 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1491 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1492 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1493 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1494 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1495 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1496 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1497 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1498
1499 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1500 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1501 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1502 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1503 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1504 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1505 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1506 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1507 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1508
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1509/*
1510 * Static pins can not be muxed between different functions but
1511 * still need mark entries in the pinmux list. Add each static
1512 * pin to the list without an associated function. The sh-pfc
1513 * core will do the right thing and skip trying to mux the pin
1514 * while still applying configuration to it.
1515 */
1516#define FM(x) PINMUX_DATA(x##_MARK, 0),
1517 PINMUX_STATIC
1518#undef FM
1519};
1520
1521/*
1522 * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1523 * Physical layout rows: A - AW, cols: 1 - 39.
1524 */
1525#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1526#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1527#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1528#define PIN_NONE U16_MAX
1529
1530static const struct sh_pfc_pin pinmux_pins[] = {
1531 PINMUX_GPIO_GP_ALL(),
1532
1533 /*
1534 * Pins not associated with a GPIO port.
1535 *
1536 * The pin positions are different between different r8a77965
1537 * packages, all that is needed for the pfc driver is a unique
1538 * number for each pin. To this end use the pin layout from
1539 * R-Car M3SiP to calculate a unique number for each pin.
1540 */
1541 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]1577 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1578 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1579 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1580 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1581 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1582 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1583};
1584
1585/* - AUDIO CLOCK ------------------------------------------------------------ */
1586static const unsigned int audio_clk_a_a_pins[] = {
1587 /* CLK A */
1588 RCAR_GP_PIN(6, 22),
1589};
1590static const unsigned int audio_clk_a_a_mux[] = {
1591 AUDIO_CLKA_A_MARK,
1592};
1593static const unsigned int audio_clk_a_b_pins[] = {
1594 /* CLK A */
1595 RCAR_GP_PIN(5, 4),
1596};
1597static const unsigned int audio_clk_a_b_mux[] = {
1598 AUDIO_CLKA_B_MARK,
1599};
1600static const unsigned int audio_clk_a_c_pins[] = {
1601 /* CLK A */
1602 RCAR_GP_PIN(5, 19),
1603};
1604static const unsigned int audio_clk_a_c_mux[] = {
1605 AUDIO_CLKA_C_MARK,
1606};
1607static const unsigned int audio_clk_b_a_pins[] = {
1608 /* CLK B */
1609 RCAR_GP_PIN(5, 12),
1610};
1611static const unsigned int audio_clk_b_a_mux[] = {
1612 AUDIO_CLKB_A_MARK,
1613};
1614static const unsigned int audio_clk_b_b_pins[] = {
1615 /* CLK B */
1616 RCAR_GP_PIN(6, 23),
1617};
1618static const unsigned int audio_clk_b_b_mux[] = {
1619 AUDIO_CLKB_B_MARK,
1620};
1621static const unsigned int audio_clk_c_a_pins[] = {
1622 /* CLK C */
1623 RCAR_GP_PIN(5, 21),
1624};
1625static const unsigned int audio_clk_c_a_mux[] = {
1626 AUDIO_CLKC_A_MARK,
1627};
1628static const unsigned int audio_clk_c_b_pins[] = {
1629 /* CLK C */
1630 RCAR_GP_PIN(5, 0),
1631};
1632static const unsigned int audio_clk_c_b_mux[] = {
1633 AUDIO_CLKC_B_MARK,
1634};
1635static const unsigned int audio_clkout_a_pins[] = {
1636 /* CLKOUT */
1637 RCAR_GP_PIN(5, 18),
1638};
1639static const unsigned int audio_clkout_a_mux[] = {
1640 AUDIO_CLKOUT_A_MARK,
1641};
1642static const unsigned int audio_clkout_b_pins[] = {
1643 /* CLKOUT */
1644 RCAR_GP_PIN(6, 28),
1645};
1646static const unsigned int audio_clkout_b_mux[] = {
1647 AUDIO_CLKOUT_B_MARK,
1648};
1649static const unsigned int audio_clkout_c_pins[] = {
1650 /* CLKOUT */
1651 RCAR_GP_PIN(5, 3),
1652};
1653static const unsigned int audio_clkout_c_mux[] = {
1654 AUDIO_CLKOUT_C_MARK,
1655};
1656static const unsigned int audio_clkout_d_pins[] = {
1657 /* CLKOUT */
1658 RCAR_GP_PIN(5, 21),
1659};
1660static const unsigned int audio_clkout_d_mux[] = {
1661 AUDIO_CLKOUT_D_MARK,
1662};
1663static const unsigned int audio_clkout1_a_pins[] = {
1664 /* CLKOUT1 */
1665 RCAR_GP_PIN(5, 15),
1666};
1667static const unsigned int audio_clkout1_a_mux[] = {
1668 AUDIO_CLKOUT1_A_MARK,
1669};
1670static const unsigned int audio_clkout1_b_pins[] = {
1671 /* CLKOUT1 */
1672 RCAR_GP_PIN(6, 29),
1673};
1674static const unsigned int audio_clkout1_b_mux[] = {
1675 AUDIO_CLKOUT1_B_MARK,
1676};
1677static const unsigned int audio_clkout2_a_pins[] = {
1678 /* CLKOUT2 */
1679 RCAR_GP_PIN(5, 16),
1680};
1681static const unsigned int audio_clkout2_a_mux[] = {
1682 AUDIO_CLKOUT2_A_MARK,
1683};
1684static const unsigned int audio_clkout2_b_pins[] = {
1685 /* CLKOUT2 */
1686 RCAR_GP_PIN(6, 30),
1687};
1688static const unsigned int audio_clkout2_b_mux[] = {
1689 AUDIO_CLKOUT2_B_MARK,
1690};
1691
1692static const unsigned int audio_clkout3_a_pins[] = {
1693 /* CLKOUT3 */
1694 RCAR_GP_PIN(5, 19),
1695};
1696static const unsigned int audio_clkout3_a_mux[] = {
1697 AUDIO_CLKOUT3_A_MARK,
1698};
1699static const unsigned int audio_clkout3_b_pins[] = {
1700 /* CLKOUT3 */
1701 RCAR_GP_PIN(6, 31),
1702};
1703static const unsigned int audio_clkout3_b_mux[] = {
1704 AUDIO_CLKOUT3_B_MARK,
1705};
1706
1707/* - EtherAVB --------------------------------------------------------------- */
1708static const unsigned int avb_link_pins[] = {
1709 /* AVB_LINK */
1710 RCAR_GP_PIN(2, 12),
1711};
1712static const unsigned int avb_link_mux[] = {
1713 AVB_LINK_MARK,
1714};
1715static const unsigned int avb_magic_pins[] = {
1716 /* AVB_MAGIC_ */
1717 RCAR_GP_PIN(2, 10),
1718};
1719static const unsigned int avb_magic_mux[] = {
1720 AVB_MAGIC_MARK,
1721};
1722static const unsigned int avb_phy_int_pins[] = {
1723 /* AVB_PHY_INT */
1724 RCAR_GP_PIN(2, 11),
1725};
1726static const unsigned int avb_phy_int_mux[] = {
1727 AVB_PHY_INT_MARK,
1728};
1729static const unsigned int avb_mdio_pins[] = {
1730 /* AVB_MDC, AVB_MDIO */
1731 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1732};
1733static const unsigned int avb_mdio_mux[] = {
1734 AVB_MDC_MARK, AVB_MDIO_MARK,
1735};
1736static const unsigned int avb_mii_pins[] = {
1737 /*
1738 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1739 * AVB_TD1, AVB_TD2, AVB_TD3,
1740 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1741 * AVB_RD1, AVB_RD2, AVB_RD3,
1742 * AVB_TXCREFCLK
1743 */
1744 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1745 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1746 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1747 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1748 PIN_NUMBER('A', 12),
1749
1750};
1751static const unsigned int avb_mii_mux[] = {
1752 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1753 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1754 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1755 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1756 AVB_TXCREFCLK_MARK,
1757};
1758static const unsigned int avb_avtp_pps_pins[] = {
1759 /* AVB_AVTP_PPS */
1760 RCAR_GP_PIN(2, 6),
1761};
1762static const unsigned int avb_avtp_pps_mux[] = {
1763 AVB_AVTP_PPS_MARK,
1764};
1765static const unsigned int avb_avtp_match_a_pins[] = {
1766 /* AVB_AVTP_MATCH_A */
1767 RCAR_GP_PIN(2, 13),
1768};
1769static const unsigned int avb_avtp_match_a_mux[] = {
1770 AVB_AVTP_MATCH_A_MARK,
1771};
1772static const unsigned int avb_avtp_capture_a_pins[] = {
1773 /* AVB_AVTP_CAPTURE_A */
1774 RCAR_GP_PIN(2, 14),
1775};
1776static const unsigned int avb_avtp_capture_a_mux[] = {
1777 AVB_AVTP_CAPTURE_A_MARK,
1778};
1779static const unsigned int avb_avtp_match_b_pins[] = {
1780 /* AVB_AVTP_MATCH_B */
1781 RCAR_GP_PIN(1, 8),
1782};
1783static const unsigned int avb_avtp_match_b_mux[] = {
1784 AVB_AVTP_MATCH_B_MARK,
1785};
1786static const unsigned int avb_avtp_capture_b_pins[] = {
1787 /* AVB_AVTP_CAPTURE_B */
1788 RCAR_GP_PIN(1, 11),
1789};
1790static const unsigned int avb_avtp_capture_b_mux[] = {
1791 AVB_AVTP_CAPTURE_B_MARK,
1792};
1793
1794/* - CAN ------------------------------------------------------------------ */
1795static const unsigned int can0_data_a_pins[] = {
1796 /* TX, RX */
1797 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1798};
1799
1800static const unsigned int can0_data_a_mux[] = {
1801 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1802};
1803
1804static const unsigned int can0_data_b_pins[] = {
1805 /* TX, RX */
1806 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1807};
1808
1809static const unsigned int can0_data_b_mux[] = {
1810 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1811};
1812
1813static const unsigned int can1_data_pins[] = {
1814 /* TX, RX */
1815 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1816};
1817
1818static const unsigned int can1_data_mux[] = {
1819 CAN1_TX_MARK, CAN1_RX_MARK,
1820};
1821
1822/* - CAN Clock -------------------------------------------------------------- */
1823static const unsigned int can_clk_pins[] = {
1824 /* CLK */
1825 RCAR_GP_PIN(1, 25),
1826};
1827
1828static const unsigned int can_clk_mux[] = {
1829 CAN_CLK_MARK,
1830};
1831
1832/* - CAN FD --------------------------------------------------------------- */
1833static const unsigned int canfd0_data_a_pins[] = {
1834 /* TX, RX */
1835 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1836};
1837
1838static const unsigned int canfd0_data_a_mux[] = {
1839 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1840};
1841
1842static const unsigned int canfd0_data_b_pins[] = {
1843 /* TX, RX */
1844 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1845};
1846
1847static const unsigned int canfd0_data_b_mux[] = {
1848 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1849};
1850
1851static const unsigned int canfd1_data_pins[] = {
1852 /* TX, RX */
1853 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1854};
1855
1856static const unsigned int canfd1_data_mux[] = {
1857 CANFD1_TX_MARK, CANFD1_RX_MARK,
1858};
1859
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]1860/* - DRIF0 --------------------------------------------------------------- */
1861static const unsigned int drif0_ctrl_a_pins[] = {
1862 /* CLK, SYNC */
1863 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1864};
1865
1866static const unsigned int drif0_ctrl_a_mux[] = {
1867 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1868};
1869
1870static const unsigned int drif0_data0_a_pins[] = {
1871 /* D0 */
1872 RCAR_GP_PIN(6, 10),
1873};
1874
1875static const unsigned int drif0_data0_a_mux[] = {
1876 RIF0_D0_A_MARK,
1877};
1878
1879static const unsigned int drif0_data1_a_pins[] = {
1880 /* D1 */
1881 RCAR_GP_PIN(6, 7),
1882};
1883
1884static const unsigned int drif0_data1_a_mux[] = {
1885 RIF0_D1_A_MARK,
1886};
1887
1888static const unsigned int drif0_ctrl_b_pins[] = {
1889 /* CLK, SYNC */
1890 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1891};
1892
1893static const unsigned int drif0_ctrl_b_mux[] = {
1894 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1895};
1896
1897static const unsigned int drif0_data0_b_pins[] = {
1898 /* D0 */
1899 RCAR_GP_PIN(5, 1),
1900};
1901
1902static const unsigned int drif0_data0_b_mux[] = {
1903 RIF0_D0_B_MARK,
1904};
1905
1906static const unsigned int drif0_data1_b_pins[] = {
1907 /* D1 */
1908 RCAR_GP_PIN(5, 2),
1909};
1910
1911static const unsigned int drif0_data1_b_mux[] = {
1912 RIF0_D1_B_MARK,
1913};
1914
1915static const unsigned int drif0_ctrl_c_pins[] = {
1916 /* CLK, SYNC */
1917 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1918};
1919
1920static const unsigned int drif0_ctrl_c_mux[] = {
1921 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1922};
1923
1924static const unsigned int drif0_data0_c_pins[] = {
1925 /* D0 */
1926 RCAR_GP_PIN(5, 13),
1927};
1928
1929static const unsigned int drif0_data0_c_mux[] = {
1930 RIF0_D0_C_MARK,
1931};
1932
1933static const unsigned int drif0_data1_c_pins[] = {
1934 /* D1 */
1935 RCAR_GP_PIN(5, 14),
1936};
1937
1938static const unsigned int drif0_data1_c_mux[] = {
1939 RIF0_D1_C_MARK,
1940};
1941
1942/* - DRIF1 --------------------------------------------------------------- */
1943static const unsigned int drif1_ctrl_a_pins[] = {
1944 /* CLK, SYNC */
1945 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1946};
1947
1948static const unsigned int drif1_ctrl_a_mux[] = {
1949 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1950};
1951
1952static const unsigned int drif1_data0_a_pins[] = {
1953 /* D0 */
1954 RCAR_GP_PIN(6, 19),
1955};
1956
1957static const unsigned int drif1_data0_a_mux[] = {
1958 RIF1_D0_A_MARK,
1959};
1960
1961static const unsigned int drif1_data1_a_pins[] = {
1962 /* D1 */
1963 RCAR_GP_PIN(6, 20),
1964};
1965
1966static const unsigned int drif1_data1_a_mux[] = {
1967 RIF1_D1_A_MARK,
1968};
1969
1970static const unsigned int drif1_ctrl_b_pins[] = {
1971 /* CLK, SYNC */
1972 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1973};
1974
1975static const unsigned int drif1_ctrl_b_mux[] = {
1976 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1977};
1978
1979static const unsigned int drif1_data0_b_pins[] = {
1980 /* D0 */
1981 RCAR_GP_PIN(5, 7),
1982};
1983
1984static const unsigned int drif1_data0_b_mux[] = {
1985 RIF1_D0_B_MARK,
1986};
1987
1988static const unsigned int drif1_data1_b_pins[] = {
1989 /* D1 */
1990 RCAR_GP_PIN(5, 8),
1991};
1992
1993static const unsigned int drif1_data1_b_mux[] = {
1994 RIF1_D1_B_MARK,
1995};
1996
1997static const unsigned int drif1_ctrl_c_pins[] = {
1998 /* CLK, SYNC */
1999 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
2000};
2001
2002static const unsigned int drif1_ctrl_c_mux[] = {
2003 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
2004};
2005
2006static const unsigned int drif1_data0_c_pins[] = {
2007 /* D0 */
2008 RCAR_GP_PIN(5, 6),
2009};
2010
2011static const unsigned int drif1_data0_c_mux[] = {
2012 RIF1_D0_C_MARK,
2013};
2014
2015static const unsigned int drif1_data1_c_pins[] = {
2016 /* D1 */
2017 RCAR_GP_PIN(5, 10),
2018};
2019
2020static const unsigned int drif1_data1_c_mux[] = {
2021 RIF1_D1_C_MARK,
2022};
2023
2024/* - DRIF2 --------------------------------------------------------------- */
2025static const unsigned int drif2_ctrl_a_pins[] = {
2026 /* CLK, SYNC */
2027 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2028};
2029
2030static const unsigned int drif2_ctrl_a_mux[] = {
2031 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2032};
2033
2034static const unsigned int drif2_data0_a_pins[] = {
2035 /* D0 */
2036 RCAR_GP_PIN(6, 7),
2037};
2038
2039static const unsigned int drif2_data0_a_mux[] = {
2040 RIF2_D0_A_MARK,
2041};
2042
2043static const unsigned int drif2_data1_a_pins[] = {
2044 /* D1 */
2045 RCAR_GP_PIN(6, 10),
2046};
2047
2048static const unsigned int drif2_data1_a_mux[] = {
2049 RIF2_D1_A_MARK,
2050};
2051
2052static const unsigned int drif2_ctrl_b_pins[] = {
2053 /* CLK, SYNC */
2054 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2055};
2056
2057static const unsigned int drif2_ctrl_b_mux[] = {
2058 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2059};
2060
2061static const unsigned int drif2_data0_b_pins[] = {
2062 /* D0 */
2063 RCAR_GP_PIN(6, 30),
2064};
2065
2066static const unsigned int drif2_data0_b_mux[] = {
2067 RIF2_D0_B_MARK,
2068};
2069
2070static const unsigned int drif2_data1_b_pins[] = {
2071 /* D1 */
2072 RCAR_GP_PIN(6, 31),
2073};
2074
2075static const unsigned int drif2_data1_b_mux[] = {
2076 RIF2_D1_B_MARK,
2077};
2078
2079/* - DRIF3 --------------------------------------------------------------- */
2080static const unsigned int drif3_ctrl_a_pins[] = {
2081 /* CLK, SYNC */
2082 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2083};
2084
2085static const unsigned int drif3_ctrl_a_mux[] = {
2086 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2087};
2088
2089static const unsigned int drif3_data0_a_pins[] = {
2090 /* D0 */
2091 RCAR_GP_PIN(6, 19),
2092};
2093
2094static const unsigned int drif3_data0_a_mux[] = {
2095 RIF3_D0_A_MARK,
2096};
2097
2098static const unsigned int drif3_data1_a_pins[] = {
2099 /* D1 */
2100 RCAR_GP_PIN(6, 20),
2101};
2102
2103static const unsigned int drif3_data1_a_mux[] = {
2104 RIF3_D1_A_MARK,
2105};
2106
2107static const unsigned int drif3_ctrl_b_pins[] = {
2108 /* CLK, SYNC */
2109 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2110};
2111
2112static const unsigned int drif3_ctrl_b_mux[] = {
2113 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2114};
2115
2116static const unsigned int drif3_data0_b_pins[] = {
2117 /* D0 */
2118 RCAR_GP_PIN(6, 28),
2119};
2120
2121static const unsigned int drif3_data0_b_mux[] = {
2122 RIF3_D0_B_MARK,
2123};
2124
2125static const unsigned int drif3_data1_b_pins[] = {
2126 /* D1 */
2127 RCAR_GP_PIN(6, 29),
2128};
2129
2130static const unsigned int drif3_data1_b_mux[] = {
2131 RIF3_D1_B_MARK,
2132};
2133
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2134/* - DU --------------------------------------------------------------------- */
2135static const unsigned int du_rgb666_pins[] = {
2136 /* R[7:2], G[7:2], B[7:2] */
2137 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2138 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2139 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2140 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2141 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2142 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2143};
2144
2145static const unsigned int du_rgb666_mux[] = {
2146 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2147 DU_DR3_MARK, DU_DR2_MARK,
2148 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2149 DU_DG3_MARK, DU_DG2_MARK,
2150 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2151 DU_DB3_MARK, DU_DB2_MARK,
2152};
2153
2154static const unsigned int du_rgb888_pins[] = {
2155 /* R[7:0], G[7:0], B[7:0] */
2156 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2157 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2158 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2159 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2160 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2161 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2162 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2163 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2164 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2165};
2166
2167static const unsigned int du_rgb888_mux[] = {
2168 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2169 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2170 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2171 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2172 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2173 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2174};
2175
2176static const unsigned int du_clk_out_0_pins[] = {
2177 /* CLKOUT */
2178 RCAR_GP_PIN(1, 27),
2179};
2180
2181static const unsigned int du_clk_out_0_mux[] = {
2182 DU_DOTCLKOUT0_MARK
2183};
2184
2185static const unsigned int du_clk_out_1_pins[] = {
2186 /* CLKOUT */
2187 RCAR_GP_PIN(2, 3),
2188};
2189
2190static const unsigned int du_clk_out_1_mux[] = {
2191 DU_DOTCLKOUT1_MARK
2192};
2193
2194static const unsigned int du_sync_pins[] = {
2195 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2196 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2197};
2198
2199static const unsigned int du_sync_mux[] = {
2200 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2201};
2202
2203static const unsigned int du_oddf_pins[] = {
2204 /* EXDISP/EXODDF/EXCDE */
2205 RCAR_GP_PIN(2, 2),
2206};
2207
2208static const unsigned int du_oddf_mux[] = {
2209 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2210};
2211
2212static const unsigned int du_cde_pins[] = {
2213 /* CDE */
2214 RCAR_GP_PIN(2, 0),
2215};
2216
2217static const unsigned int du_cde_mux[] = {
2218 DU_CDE_MARK,
2219};
2220
2221static const unsigned int du_disp_pins[] = {
2222 /* DISP */
2223 RCAR_GP_PIN(2, 1),
2224};
2225
2226static const unsigned int du_disp_mux[] = {
2227 DU_DISP_MARK,
2228};
2229
2230/* - HSCIF0 ----------------------------------------------------------------- */
2231static const unsigned int hscif0_data_pins[] = {
2232 /* RX, TX */
2233 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2234};
2235
2236static const unsigned int hscif0_data_mux[] = {
2237 HRX0_MARK, HTX0_MARK,
2238};
2239
2240static const unsigned int hscif0_clk_pins[] = {
2241 /* SCK */
2242 RCAR_GP_PIN(5, 12),
2243};
2244
2245static const unsigned int hscif0_clk_mux[] = {
2246 HSCK0_MARK,
2247};
2248
2249static const unsigned int hscif0_ctrl_pins[] = {
2250 /* RTS, CTS */
2251 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2252};
2253
2254static const unsigned int hscif0_ctrl_mux[] = {
2255 HRTS0_N_MARK, HCTS0_N_MARK,
2256};
2257
2258/* - HSCIF1 ----------------------------------------------------------------- */
2259static const unsigned int hscif1_data_a_pins[] = {
2260 /* RX, TX */
2261 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2262};
2263
2264static const unsigned int hscif1_data_a_mux[] = {
2265 HRX1_A_MARK, HTX1_A_MARK,
2266};
2267
2268static const unsigned int hscif1_clk_a_pins[] = {
2269 /* SCK */
2270 RCAR_GP_PIN(6, 21),
2271};
2272
2273static const unsigned int hscif1_clk_a_mux[] = {
2274 HSCK1_A_MARK,
2275};
2276
2277static const unsigned int hscif1_ctrl_a_pins[] = {
2278 /* RTS, CTS */
2279 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2280};
2281
2282static const unsigned int hscif1_ctrl_a_mux[] = {
2283 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2284};
2285
2286static const unsigned int hscif1_data_b_pins[] = {
2287 /* RX, TX */
2288 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2289};
2290
2291static const unsigned int hscif1_data_b_mux[] = {
2292 HRX1_B_MARK, HTX1_B_MARK,
2293};
2294
2295static const unsigned int hscif1_clk_b_pins[] = {
2296 /* SCK */
2297 RCAR_GP_PIN(5, 0),
2298};
2299
2300static const unsigned int hscif1_clk_b_mux[] = {
2301 HSCK1_B_MARK,
2302};
2303
2304static const unsigned int hscif1_ctrl_b_pins[] = {
2305 /* RTS, CTS */
2306 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2307};
2308
2309static const unsigned int hscif1_ctrl_b_mux[] = {
2310 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2311};
2312
2313/* - HSCIF2 ----------------------------------------------------------------- */
2314static const unsigned int hscif2_data_a_pins[] = {
2315 /* RX, TX */
2316 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2317};
2318
2319static const unsigned int hscif2_data_a_mux[] = {
2320 HRX2_A_MARK, HTX2_A_MARK,
2321};
2322
2323static const unsigned int hscif2_clk_a_pins[] = {
2324 /* SCK */
2325 RCAR_GP_PIN(6, 10),
2326};
2327
2328static const unsigned int hscif2_clk_a_mux[] = {
2329 HSCK2_A_MARK,
2330};
2331
2332static const unsigned int hscif2_ctrl_a_pins[] = {
2333 /* RTS, CTS */
2334 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2335};
2336
2337static const unsigned int hscif2_ctrl_a_mux[] = {
2338 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2339};
2340
2341static const unsigned int hscif2_data_b_pins[] = {
2342 /* RX, TX */
2343 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2344};
2345
2346static const unsigned int hscif2_data_b_mux[] = {
2347 HRX2_B_MARK, HTX2_B_MARK,
2348};
2349
2350static const unsigned int hscif2_clk_b_pins[] = {
2351 /* SCK */
2352 RCAR_GP_PIN(6, 21),
2353};
2354
2355static const unsigned int hscif2_clk_b_mux[] = {
2356 HSCK2_B_MARK,
2357};
2358
2359static const unsigned int hscif2_ctrl_b_pins[] = {
2360 /* RTS, CTS */
2361 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2362};
2363
2364static const unsigned int hscif2_ctrl_b_mux[] = {
2365 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2366};
2367
2368static const unsigned int hscif2_data_c_pins[] = {
2369 /* RX, TX */
2370 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2371};
2372
2373static const unsigned int hscif2_data_c_mux[] = {
2374 HRX2_C_MARK, HTX2_C_MARK,
2375};
2376
2377static const unsigned int hscif2_clk_c_pins[] = {
2378 /* SCK */
2379 RCAR_GP_PIN(6, 24),
2380};
2381
2382static const unsigned int hscif2_clk_c_mux[] = {
2383 HSCK2_C_MARK,
2384};
2385
2386static const unsigned int hscif2_ctrl_c_pins[] = {
2387 /* RTS, CTS */
2388 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2389};
2390
2391static const unsigned int hscif2_ctrl_c_mux[] = {
2392 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2393};
2394
2395/* - HSCIF3 ----------------------------------------------------------------- */
2396static const unsigned int hscif3_data_a_pins[] = {
2397 /* RX, TX */
2398 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2399};
2400
2401static const unsigned int hscif3_data_a_mux[] = {
2402 HRX3_A_MARK, HTX3_A_MARK,
2403};
2404
2405static const unsigned int hscif3_clk_pins[] = {
2406 /* SCK */
2407 RCAR_GP_PIN(1, 22),
2408};
2409
2410static const unsigned int hscif3_clk_mux[] = {
2411 HSCK3_MARK,
2412};
2413
2414static const unsigned int hscif3_ctrl_pins[] = {
2415 /* RTS, CTS */
2416 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2417};
2418
2419static const unsigned int hscif3_ctrl_mux[] = {
2420 HRTS3_N_MARK, HCTS3_N_MARK,
2421};
2422
2423static const unsigned int hscif3_data_b_pins[] = {
2424 /* RX, TX */
2425 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2426};
2427
2428static const unsigned int hscif3_data_b_mux[] = {
2429 HRX3_B_MARK, HTX3_B_MARK,
2430};
2431
2432static const unsigned int hscif3_data_c_pins[] = {
2433 /* RX, TX */
2434 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2435};
2436
2437static const unsigned int hscif3_data_c_mux[] = {
2438 HRX3_C_MARK, HTX3_C_MARK,
2439};
2440
2441static const unsigned int hscif3_data_d_pins[] = {
2442 /* RX, TX */
2443 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2444};
2445
2446static const unsigned int hscif3_data_d_mux[] = {
2447 HRX3_D_MARK, HTX3_D_MARK,
2448};
2449
2450/* - HSCIF4 ----------------------------------------------------------------- */
2451static const unsigned int hscif4_data_a_pins[] = {
2452 /* RX, TX */
2453 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2454};
2455
2456static const unsigned int hscif4_data_a_mux[] = {
2457 HRX4_A_MARK, HTX4_A_MARK,
2458};
2459
2460static const unsigned int hscif4_clk_pins[] = {
2461 /* SCK */
2462 RCAR_GP_PIN(1, 11),
2463};
2464
2465static const unsigned int hscif4_clk_mux[] = {
2466 HSCK4_MARK,
2467};
2468
2469static const unsigned int hscif4_ctrl_pins[] = {
2470 /* RTS, CTS */
2471 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2472};
2473
2474static const unsigned int hscif4_ctrl_mux[] = {
2475 HRTS4_N_MARK, HCTS4_N_MARK,
2476};
2477
2478static const unsigned int hscif4_data_b_pins[] = {
2479 /* RX, TX */
2480 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2481};
2482
2483static const unsigned int hscif4_data_b_mux[] = {
2484 HRX4_B_MARK, HTX4_B_MARK,
2485};
2486
2487/* - I2C -------------------------------------------------------------------- */
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2488static const unsigned int i2c0_pins[] = {
2489 /* SCL, SDA */
2490 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2491};
2492
2493static const unsigned int i2c0_mux[] = {
2494 SCL0_MARK, SDA0_MARK,
2495};
2496
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2497static const unsigned int i2c1_a_pins[] = {
2498 /* SDA, SCL */
2499 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2500};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2501
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2502static const unsigned int i2c1_a_mux[] = {
2503 SDA1_A_MARK, SCL1_A_MARK,
2504};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2505
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2506static const unsigned int i2c1_b_pins[] = {
2507 /* SDA, SCL */
2508 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2509};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2510
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2511static const unsigned int i2c1_b_mux[] = {
2512 SDA1_B_MARK, SCL1_B_MARK,
2513};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2514
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2515static const unsigned int i2c2_a_pins[] = {
2516 /* SDA, SCL */
2517 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2518};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2519
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2520static const unsigned int i2c2_a_mux[] = {
2521 SDA2_A_MARK, SCL2_A_MARK,
2522};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2523
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2524static const unsigned int i2c2_b_pins[] = {
2525 /* SDA, SCL */
2526 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2527};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2528
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2529static const unsigned int i2c2_b_mux[] = {
2530 SDA2_B_MARK, SCL2_B_MARK,
2531};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2532
2533static const unsigned int i2c3_pins[] = {
2534 /* SCL, SDA */
2535 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2536};
2537
2538static const unsigned int i2c3_mux[] = {
2539 SCL3_MARK, SDA3_MARK,
2540};
2541
2542static const unsigned int i2c5_pins[] = {
2543 /* SCL, SDA */
2544 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2545};
2546
2547static const unsigned int i2c5_mux[] = {
2548 SCL5_MARK, SDA5_MARK,
2549};
2550
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2551static const unsigned int i2c6_a_pins[] = {
2552 /* SDA, SCL */
2553 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2554};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2555
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2556static const unsigned int i2c6_a_mux[] = {
2557 SDA6_A_MARK, SCL6_A_MARK,
2558};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2559
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2560static const unsigned int i2c6_b_pins[] = {
2561 /* SDA, SCL */
2562 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2563};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2564
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2565static const unsigned int i2c6_b_mux[] = {
2566 SDA6_B_MARK, SCL6_B_MARK,
2567};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2568
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2569static const unsigned int i2c6_c_pins[] = {
2570 /* SDA, SCL */
2571 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2572};
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]2573
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]2574static const unsigned int i2c6_c_mux[] = {
2575 SDA6_C_MARK, SCL6_C_MARK,
2576};
2577
2578/* - INTC-EX ---------------------------------------------------------------- */
2579static const unsigned int intc_ex_irq0_pins[] = {
2580 /* IRQ0 */
2581 RCAR_GP_PIN(2, 0),
2582};
2583static const unsigned int intc_ex_irq0_mux[] = {
2584 IRQ0_MARK,
2585};
2586static const unsigned int intc_ex_irq1_pins[] = {
2587 /* IRQ1 */
2588 RCAR_GP_PIN(2, 1),
2589};
2590static const unsigned int intc_ex_irq1_mux[] = {
2591 IRQ1_MARK,
2592};
2593static const unsigned int intc_ex_irq2_pins[] = {
2594 /* IRQ2 */
2595 RCAR_GP_PIN(2, 2),
2596};
2597static const unsigned int intc_ex_irq2_mux[] = {
2598 IRQ2_MARK,
2599};
2600static const unsigned int intc_ex_irq3_pins[] = {
2601 /* IRQ3 */
2602 RCAR_GP_PIN(2, 3),
2603};
2604static const unsigned int intc_ex_irq3_mux[] = {
2605 IRQ3_MARK,
2606};
2607static const unsigned int intc_ex_irq4_pins[] = {
2608 /* IRQ4 */
2609 RCAR_GP_PIN(2, 4),
2610};
2611static const unsigned int intc_ex_irq4_mux[] = {
2612 IRQ4_MARK,
2613};
2614static const unsigned int intc_ex_irq5_pins[] = {
2615 /* IRQ5 */
2616 RCAR_GP_PIN(2, 5),
2617};
2618static const unsigned int intc_ex_irq5_mux[] = {
2619 IRQ5_MARK,
2620};
2621
2622/* - MSIOF0 ----------------------------------------------------------------- */
2623static const unsigned int msiof0_clk_pins[] = {
2624 /* SCK */
2625 RCAR_GP_PIN(5, 17),
2626};
2627static const unsigned int msiof0_clk_mux[] = {
2628 MSIOF0_SCK_MARK,
2629};
2630static const unsigned int msiof0_sync_pins[] = {
2631 /* SYNC */
2632 RCAR_GP_PIN(5, 18),
2633};
2634static const unsigned int msiof0_sync_mux[] = {
2635 MSIOF0_SYNC_MARK,
2636};
2637static const unsigned int msiof0_ss1_pins[] = {
2638 /* SS1 */
2639 RCAR_GP_PIN(5, 19),
2640};
2641static const unsigned int msiof0_ss1_mux[] = {
2642 MSIOF0_SS1_MARK,
2643};
2644static const unsigned int msiof0_ss2_pins[] = {
2645 /* SS2 */
2646 RCAR_GP_PIN(5, 21),
2647};
2648static const unsigned int msiof0_ss2_mux[] = {
2649 MSIOF0_SS2_MARK,
2650};
2651static const unsigned int msiof0_txd_pins[] = {
2652 /* TXD */
2653 RCAR_GP_PIN(5, 20),
2654};
2655static const unsigned int msiof0_txd_mux[] = {
2656 MSIOF0_TXD_MARK,
2657};
2658static const unsigned int msiof0_rxd_pins[] = {
2659 /* RXD */
2660 RCAR_GP_PIN(5, 22),
2661};
2662static const unsigned int msiof0_rxd_mux[] = {
2663 MSIOF0_RXD_MARK,
2664};
2665/* - MSIOF1 ----------------------------------------------------------------- */
2666static const unsigned int msiof1_clk_a_pins[] = {
2667 /* SCK */
2668 RCAR_GP_PIN(6, 8),
2669};
2670static const unsigned int msiof1_clk_a_mux[] = {
2671 MSIOF1_SCK_A_MARK,
2672};
2673static const unsigned int msiof1_sync_a_pins[] = {
2674 /* SYNC */
2675 RCAR_GP_PIN(6, 9),
2676};
2677static const unsigned int msiof1_sync_a_mux[] = {
2678 MSIOF1_SYNC_A_MARK,
2679};
2680static const unsigned int msiof1_ss1_a_pins[] = {
2681 /* SS1 */
2682 RCAR_GP_PIN(6, 5),
2683};
2684static const unsigned int msiof1_ss1_a_mux[] = {
2685 MSIOF1_SS1_A_MARK,
2686};
2687static const unsigned int msiof1_ss2_a_pins[] = {
2688 /* SS2 */
2689 RCAR_GP_PIN(6, 6),
2690};
2691static const unsigned int msiof1_ss2_a_mux[] = {
2692 MSIOF1_SS2_A_MARK,
2693};
2694static const unsigned int msiof1_txd_a_pins[] = {
2695 /* TXD */
2696 RCAR_GP_PIN(6, 7),
2697};
2698static const unsigned int msiof1_txd_a_mux[] = {
2699 MSIOF1_TXD_A_MARK,
2700};
2701static const unsigned int msiof1_rxd_a_pins[] = {
2702 /* RXD */
2703 RCAR_GP_PIN(6, 10),
2704};
2705static const unsigned int msiof1_rxd_a_mux[] = {
2706 MSIOF1_RXD_A_MARK,
2707};
2708static const unsigned int msiof1_clk_b_pins[] = {
2709 /* SCK */
2710 RCAR_GP_PIN(5, 9),
2711};
2712static const unsigned int msiof1_clk_b_mux[] = {
2713 MSIOF1_SCK_B_MARK,
2714};
2715static const unsigned int msiof1_sync_b_pins[] = {
2716 /* SYNC */
2717 RCAR_GP_PIN(5, 3),
2718};
2719static const unsigned int msiof1_sync_b_mux[] = {
2720 MSIOF1_SYNC_B_MARK,
2721};
2722static const unsigned int msiof1_ss1_b_pins[] = {
2723 /* SS1 */
2724 RCAR_GP_PIN(5, 4),
2725};
2726static const unsigned int msiof1_ss1_b_mux[] = {
2727 MSIOF1_SS1_B_MARK,
2728};
2729static const unsigned int msiof1_ss2_b_pins[] = {
2730 /* SS2 */
2731 RCAR_GP_PIN(5, 0),
2732};
2733static const unsigned int msiof1_ss2_b_mux[] = {
2734 MSIOF1_SS2_B_MARK,
2735};
2736static const unsigned int msiof1_txd_b_pins[] = {
2737 /* TXD */
2738 RCAR_GP_PIN(5, 8),
2739};
2740static const unsigned int msiof1_txd_b_mux[] = {
2741 MSIOF1_TXD_B_MARK,
2742};
2743static const unsigned int msiof1_rxd_b_pins[] = {
2744 /* RXD */
2745 RCAR_GP_PIN(5, 7),
2746};
2747static const unsigned int msiof1_rxd_b_mux[] = {
2748 MSIOF1_RXD_B_MARK,
2749};
2750static const unsigned int msiof1_clk_c_pins[] = {
2751 /* SCK */
2752 RCAR_GP_PIN(6, 17),
2753};
2754static const unsigned int msiof1_clk_c_mux[] = {
2755 MSIOF1_SCK_C_MARK,
2756};
2757static const unsigned int msiof1_sync_c_pins[] = {
2758 /* SYNC */
2759 RCAR_GP_PIN(6, 18),
2760};
2761static const unsigned int msiof1_sync_c_mux[] = {
2762 MSIOF1_SYNC_C_MARK,
2763};
2764static const unsigned int msiof1_ss1_c_pins[] = {
2765 /* SS1 */
2766 RCAR_GP_PIN(6, 21),
2767};
2768static const unsigned int msiof1_ss1_c_mux[] = {
2769 MSIOF1_SS1_C_MARK,
2770};
2771static const unsigned int msiof1_ss2_c_pins[] = {
2772 /* SS2 */
2773 RCAR_GP_PIN(6, 27),
2774};
2775static const unsigned int msiof1_ss2_c_mux[] = {
2776 MSIOF1_SS2_C_MARK,
2777};
2778static const unsigned int msiof1_txd_c_pins[] = {
2779 /* TXD */
2780 RCAR_GP_PIN(6, 20),
2781};
2782static const unsigned int msiof1_txd_c_mux[] = {
2783 MSIOF1_TXD_C_MARK,
2784};
2785static const unsigned int msiof1_rxd_c_pins[] = {
2786 /* RXD */
2787 RCAR_GP_PIN(6, 19),
2788};
2789static const unsigned int msiof1_rxd_c_mux[] = {
2790 MSIOF1_RXD_C_MARK,
2791};
2792static const unsigned int msiof1_clk_d_pins[] = {
2793 /* SCK */
2794 RCAR_GP_PIN(5, 12),
2795};
2796static const unsigned int msiof1_clk_d_mux[] = {
2797 MSIOF1_SCK_D_MARK,
2798};
2799static const unsigned int msiof1_sync_d_pins[] = {
2800 /* SYNC */
2801 RCAR_GP_PIN(5, 15),
2802};
2803static const unsigned int msiof1_sync_d_mux[] = {
2804 MSIOF1_SYNC_D_MARK,
2805};
2806static const unsigned int msiof1_ss1_d_pins[] = {
2807 /* SS1 */
2808 RCAR_GP_PIN(5, 16),
2809};
2810static const unsigned int msiof1_ss1_d_mux[] = {
2811 MSIOF1_SS1_D_MARK,
2812};
2813static const unsigned int msiof1_ss2_d_pins[] = {
2814 /* SS2 */
2815 RCAR_GP_PIN(5, 21),
2816};
2817static const unsigned int msiof1_ss2_d_mux[] = {
2818 MSIOF1_SS2_D_MARK,
2819};
2820static const unsigned int msiof1_txd_d_pins[] = {
2821 /* TXD */
2822 RCAR_GP_PIN(5, 14),
2823};
2824static const unsigned int msiof1_txd_d_mux[] = {
2825 MSIOF1_TXD_D_MARK,
2826};
2827static const unsigned int msiof1_rxd_d_pins[] = {
2828 /* RXD */
2829 RCAR_GP_PIN(5, 13),
2830};
2831static const unsigned int msiof1_rxd_d_mux[] = {
2832 MSIOF1_RXD_D_MARK,
2833};
2834static const unsigned int msiof1_clk_e_pins[] = {
2835 /* SCK */
2836 RCAR_GP_PIN(3, 0),
2837};
2838static const unsigned int msiof1_clk_e_mux[] = {
2839 MSIOF1_SCK_E_MARK,
2840};
2841static const unsigned int msiof1_sync_e_pins[] = {
2842 /* SYNC */
2843 RCAR_GP_PIN(3, 1),
2844};
2845static const unsigned int msiof1_sync_e_mux[] = {
2846 MSIOF1_SYNC_E_MARK,
2847};
2848static const unsigned int msiof1_ss1_e_pins[] = {
2849 /* SS1 */
2850 RCAR_GP_PIN(3, 4),
2851};
2852static const unsigned int msiof1_ss1_e_mux[] = {
2853 MSIOF1_SS1_E_MARK,
2854};
2855static const unsigned int msiof1_ss2_e_pins[] = {
2856 /* SS2 */
2857 RCAR_GP_PIN(3, 5),
2858};
2859static const unsigned int msiof1_ss2_e_mux[] = {
2860 MSIOF1_SS2_E_MARK,
2861};
2862static const unsigned int msiof1_txd_e_pins[] = {
2863 /* TXD */
2864 RCAR_GP_PIN(3, 3),
2865};
2866static const unsigned int msiof1_txd_e_mux[] = {
2867 MSIOF1_TXD_E_MARK,
2868};
2869static const unsigned int msiof1_rxd_e_pins[] = {
2870 /* RXD */
2871 RCAR_GP_PIN(3, 2),
2872};
2873static const unsigned int msiof1_rxd_e_mux[] = {
2874 MSIOF1_RXD_E_MARK,
2875};
2876static const unsigned int msiof1_clk_f_pins[] = {
2877 /* SCK */
2878 RCAR_GP_PIN(5, 23),
2879};
2880static const unsigned int msiof1_clk_f_mux[] = {
2881 MSIOF1_SCK_F_MARK,
2882};
2883static const unsigned int msiof1_sync_f_pins[] = {
2884 /* SYNC */
2885 RCAR_GP_PIN(5, 24),
2886};
2887static const unsigned int msiof1_sync_f_mux[] = {
2888 MSIOF1_SYNC_F_MARK,
2889};
2890static const unsigned int msiof1_ss1_f_pins[] = {
2891 /* SS1 */
2892 RCAR_GP_PIN(6, 1),
2893};
2894static const unsigned int msiof1_ss1_f_mux[] = {
2895 MSIOF1_SS1_F_MARK,
2896};
2897static const unsigned int msiof1_ss2_f_pins[] = {
2898 /* SS2 */
2899 RCAR_GP_PIN(6, 2),
2900};
2901static const unsigned int msiof1_ss2_f_mux[] = {
2902 MSIOF1_SS2_F_MARK,
2903};
2904static const unsigned int msiof1_txd_f_pins[] = {
2905 /* TXD */
2906 RCAR_GP_PIN(6, 0),
2907};
2908static const unsigned int msiof1_txd_f_mux[] = {
2909 MSIOF1_TXD_F_MARK,
2910};
2911static const unsigned int msiof1_rxd_f_pins[] = {
2912 /* RXD */
2913 RCAR_GP_PIN(5, 25),
2914};
2915static const unsigned int msiof1_rxd_f_mux[] = {
2916 MSIOF1_RXD_F_MARK,
2917};
2918static const unsigned int msiof1_clk_g_pins[] = {
2919 /* SCK */
2920 RCAR_GP_PIN(3, 6),
2921};
2922static const unsigned int msiof1_clk_g_mux[] = {
2923 MSIOF1_SCK_G_MARK,
2924};
2925static const unsigned int msiof1_sync_g_pins[] = {
2926 /* SYNC */
2927 RCAR_GP_PIN(3, 7),
2928};
2929static const unsigned int msiof1_sync_g_mux[] = {
2930 MSIOF1_SYNC_G_MARK,
2931};
2932static const unsigned int msiof1_ss1_g_pins[] = {
2933 /* SS1 */
2934 RCAR_GP_PIN(3, 10),
2935};
2936static const unsigned int msiof1_ss1_g_mux[] = {
2937 MSIOF1_SS1_G_MARK,
2938};
2939static const unsigned int msiof1_ss2_g_pins[] = {
2940 /* SS2 */
2941 RCAR_GP_PIN(3, 11),
2942};
2943static const unsigned int msiof1_ss2_g_mux[] = {
2944 MSIOF1_SS2_G_MARK,
2945};
2946static const unsigned int msiof1_txd_g_pins[] = {
2947 /* TXD */
2948 RCAR_GP_PIN(3, 9),
2949};
2950static const unsigned int msiof1_txd_g_mux[] = {
2951 MSIOF1_TXD_G_MARK,
2952};
2953static const unsigned int msiof1_rxd_g_pins[] = {
2954 /* RXD */
2955 RCAR_GP_PIN(3, 8),
2956};
2957static const unsigned int msiof1_rxd_g_mux[] = {
2958 MSIOF1_RXD_G_MARK,
2959};
2960/* - MSIOF2 ----------------------------------------------------------------- */
2961static const unsigned int msiof2_clk_a_pins[] = {
2962 /* SCK */
2963 RCAR_GP_PIN(1, 9),
2964};
2965static const unsigned int msiof2_clk_a_mux[] = {
2966 MSIOF2_SCK_A_MARK,
2967};
2968static const unsigned int msiof2_sync_a_pins[] = {
2969 /* SYNC */
2970 RCAR_GP_PIN(1, 8),
2971};
2972static const unsigned int msiof2_sync_a_mux[] = {
2973 MSIOF2_SYNC_A_MARK,
2974};
2975static const unsigned int msiof2_ss1_a_pins[] = {
2976 /* SS1 */
2977 RCAR_GP_PIN(1, 6),
2978};
2979static const unsigned int msiof2_ss1_a_mux[] = {
2980 MSIOF2_SS1_A_MARK,
2981};
2982static const unsigned int msiof2_ss2_a_pins[] = {
2983 /* SS2 */
2984 RCAR_GP_PIN(1, 7),
2985};
2986static const unsigned int msiof2_ss2_a_mux[] = {
2987 MSIOF2_SS2_A_MARK,
2988};
2989static const unsigned int msiof2_txd_a_pins[] = {
2990 /* TXD */
2991 RCAR_GP_PIN(1, 11),
2992};
2993static const unsigned int msiof2_txd_a_mux[] = {
2994 MSIOF2_TXD_A_MARK,
2995};
2996static const unsigned int msiof2_rxd_a_pins[] = {
2997 /* RXD */
2998 RCAR_GP_PIN(1, 10),
2999};
3000static const unsigned int msiof2_rxd_a_mux[] = {
3001 MSIOF2_RXD_A_MARK,
3002};
3003static const unsigned int msiof2_clk_b_pins[] = {
3004 /* SCK */
3005 RCAR_GP_PIN(0, 4),
3006};
3007static const unsigned int msiof2_clk_b_mux[] = {
3008 MSIOF2_SCK_B_MARK,
3009};
3010static const unsigned int msiof2_sync_b_pins[] = {
3011 /* SYNC */
3012 RCAR_GP_PIN(0, 5),
3013};
3014static const unsigned int msiof2_sync_b_mux[] = {
3015 MSIOF2_SYNC_B_MARK,
3016};
3017static const unsigned int msiof2_ss1_b_pins[] = {
3018 /* SS1 */
3019 RCAR_GP_PIN(0, 0),
3020};
3021static const unsigned int msiof2_ss1_b_mux[] = {
3022 MSIOF2_SS1_B_MARK,
3023};
3024static const unsigned int msiof2_ss2_b_pins[] = {
3025 /* SS2 */
3026 RCAR_GP_PIN(0, 1),
3027};
3028static const unsigned int msiof2_ss2_b_mux[] = {
3029 MSIOF2_SS2_B_MARK,
3030};
3031static const unsigned int msiof2_txd_b_pins[] = {
3032 /* TXD */
3033 RCAR_GP_PIN(0, 7),
3034};
3035static const unsigned int msiof2_txd_b_mux[] = {
3036 MSIOF2_TXD_B_MARK,
3037};
3038static const unsigned int msiof2_rxd_b_pins[] = {
3039 /* RXD */
3040 RCAR_GP_PIN(0, 6),
3041};
3042static const unsigned int msiof2_rxd_b_mux[] = {
3043 MSIOF2_RXD_B_MARK,
3044};
3045static const unsigned int msiof2_clk_c_pins[] = {
3046 /* SCK */
3047 RCAR_GP_PIN(2, 12),
3048};
3049static const unsigned int msiof2_clk_c_mux[] = {
3050 MSIOF2_SCK_C_MARK,
3051};
3052static const unsigned int msiof2_sync_c_pins[] = {
3053 /* SYNC */
3054 RCAR_GP_PIN(2, 11),
3055};
3056static const unsigned int msiof2_sync_c_mux[] = {
3057 MSIOF2_SYNC_C_MARK,
3058};
3059static const unsigned int msiof2_ss1_c_pins[] = {
3060 /* SS1 */
3061 RCAR_GP_PIN(2, 10),
3062};
3063static const unsigned int msiof2_ss1_c_mux[] = {
3064 MSIOF2_SS1_C_MARK,
3065};
3066static const unsigned int msiof2_ss2_c_pins[] = {
3067 /* SS2 */
3068 RCAR_GP_PIN(2, 9),
3069};
3070static const unsigned int msiof2_ss2_c_mux[] = {
3071 MSIOF2_SS2_C_MARK,
3072};
3073static const unsigned int msiof2_txd_c_pins[] = {
3074 /* TXD */
3075 RCAR_GP_PIN(2, 14),
3076};
3077static const unsigned int msiof2_txd_c_mux[] = {
3078 MSIOF2_TXD_C_MARK,
3079};
3080static const unsigned int msiof2_rxd_c_pins[] = {
3081 /* RXD */
3082 RCAR_GP_PIN(2, 13),
3083};
3084static const unsigned int msiof2_rxd_c_mux[] = {
3085 MSIOF2_RXD_C_MARK,
3086};
3087static const unsigned int msiof2_clk_d_pins[] = {
3088 /* SCK */
3089 RCAR_GP_PIN(0, 8),
3090};
3091static const unsigned int msiof2_clk_d_mux[] = {
3092 MSIOF2_SCK_D_MARK,
3093};
3094static const unsigned int msiof2_sync_d_pins[] = {
3095 /* SYNC */
3096 RCAR_GP_PIN(0, 9),
3097};
3098static const unsigned int msiof2_sync_d_mux[] = {
3099 MSIOF2_SYNC_D_MARK,
3100};
3101static const unsigned int msiof2_ss1_d_pins[] = {
3102 /* SS1 */
3103 RCAR_GP_PIN(0, 12),
3104};
3105static const unsigned int msiof2_ss1_d_mux[] = {
3106 MSIOF2_SS1_D_MARK,
3107};
3108static const unsigned int msiof2_ss2_d_pins[] = {
3109 /* SS2 */
3110 RCAR_GP_PIN(0, 13),
3111};
3112static const unsigned int msiof2_ss2_d_mux[] = {
3113 MSIOF2_SS2_D_MARK,
3114};
3115static const unsigned int msiof2_txd_d_pins[] = {
3116 /* TXD */
3117 RCAR_GP_PIN(0, 11),
3118};
3119static const unsigned int msiof2_txd_d_mux[] = {
3120 MSIOF2_TXD_D_MARK,
3121};
3122static const unsigned int msiof2_rxd_d_pins[] = {
3123 /* RXD */
3124 RCAR_GP_PIN(0, 10),
3125};
3126static const unsigned int msiof2_rxd_d_mux[] = {
3127 MSIOF2_RXD_D_MARK,
3128};
3129/* - MSIOF3 ----------------------------------------------------------------- */
3130static const unsigned int msiof3_clk_a_pins[] = {
3131 /* SCK */
3132 RCAR_GP_PIN(0, 0),
3133};
3134static const unsigned int msiof3_clk_a_mux[] = {
3135 MSIOF3_SCK_A_MARK,
3136};
3137static const unsigned int msiof3_sync_a_pins[] = {
3138 /* SYNC */
3139 RCAR_GP_PIN(0, 1),
3140};
3141static const unsigned int msiof3_sync_a_mux[] = {
3142 MSIOF3_SYNC_A_MARK,
3143};
3144static const unsigned int msiof3_ss1_a_pins[] = {
3145 /* SS1 */
3146 RCAR_GP_PIN(0, 14),
3147};
3148static const unsigned int msiof3_ss1_a_mux[] = {
3149 MSIOF3_SS1_A_MARK,
3150};
3151static const unsigned int msiof3_ss2_a_pins[] = {
3152 /* SS2 */
3153 RCAR_GP_PIN(0, 15),
3154};
3155static const unsigned int msiof3_ss2_a_mux[] = {
3156 MSIOF3_SS2_A_MARK,
3157};
3158static const unsigned int msiof3_txd_a_pins[] = {
3159 /* TXD */
3160 RCAR_GP_PIN(0, 3),
3161};
3162static const unsigned int msiof3_txd_a_mux[] = {
3163 MSIOF3_TXD_A_MARK,
3164};
3165static const unsigned int msiof3_rxd_a_pins[] = {
3166 /* RXD */
3167 RCAR_GP_PIN(0, 2),
3168};
3169static const unsigned int msiof3_rxd_a_mux[] = {
3170 MSIOF3_RXD_A_MARK,
3171};
3172static const unsigned int msiof3_clk_b_pins[] = {
3173 /* SCK */
3174 RCAR_GP_PIN(1, 2),
3175};
3176static const unsigned int msiof3_clk_b_mux[] = {
3177 MSIOF3_SCK_B_MARK,
3178};
3179static const unsigned int msiof3_sync_b_pins[] = {
3180 /* SYNC */
3181 RCAR_GP_PIN(1, 0),
3182};
3183static const unsigned int msiof3_sync_b_mux[] = {
3184 MSIOF3_SYNC_B_MARK,
3185};
3186static const unsigned int msiof3_ss1_b_pins[] = {
3187 /* SS1 */
3188 RCAR_GP_PIN(1, 4),
3189};
3190static const unsigned int msiof3_ss1_b_mux[] = {
3191 MSIOF3_SS1_B_MARK,
3192};
3193static const unsigned int msiof3_ss2_b_pins[] = {
3194 /* SS2 */
3195 RCAR_GP_PIN(1, 5),
3196};
3197static const unsigned int msiof3_ss2_b_mux[] = {
3198 MSIOF3_SS2_B_MARK,
3199};
3200static const unsigned int msiof3_txd_b_pins[] = {
3201 /* TXD */
3202 RCAR_GP_PIN(1, 1),
3203};
3204static const unsigned int msiof3_txd_b_mux[] = {
3205 MSIOF3_TXD_B_MARK,
3206};
3207static const unsigned int msiof3_rxd_b_pins[] = {
3208 /* RXD */
3209 RCAR_GP_PIN(1, 3),
3210};
3211static const unsigned int msiof3_rxd_b_mux[] = {
3212 MSIOF3_RXD_B_MARK,
3213};
3214static const unsigned int msiof3_clk_c_pins[] = {
3215 /* SCK */
3216 RCAR_GP_PIN(1, 12),
3217};
3218static const unsigned int msiof3_clk_c_mux[] = {
3219 MSIOF3_SCK_C_MARK,
3220};
3221static const unsigned int msiof3_sync_c_pins[] = {
3222 /* SYNC */
3223 RCAR_GP_PIN(1, 13),
3224};
3225static const unsigned int msiof3_sync_c_mux[] = {
3226 MSIOF3_SYNC_C_MARK,
3227};
3228static const unsigned int msiof3_txd_c_pins[] = {
3229 /* TXD */
3230 RCAR_GP_PIN(1, 15),
3231};
3232static const unsigned int msiof3_txd_c_mux[] = {
3233 MSIOF3_TXD_C_MARK,
3234};
3235static const unsigned int msiof3_rxd_c_pins[] = {
3236 /* RXD */
3237 RCAR_GP_PIN(1, 14),
3238};
3239static const unsigned int msiof3_rxd_c_mux[] = {
3240 MSIOF3_RXD_C_MARK,
3241};
3242static const unsigned int msiof3_clk_d_pins[] = {
3243 /* SCK */
3244 RCAR_GP_PIN(1, 22),
3245};
3246static const unsigned int msiof3_clk_d_mux[] = {
3247 MSIOF3_SCK_D_MARK,
3248};
3249static const unsigned int msiof3_sync_d_pins[] = {
3250 /* SYNC */
3251 RCAR_GP_PIN(1, 23),
3252};
3253static const unsigned int msiof3_sync_d_mux[] = {
3254 MSIOF3_SYNC_D_MARK,
3255};
3256static const unsigned int msiof3_ss1_d_pins[] = {
3257 /* SS1 */
3258 RCAR_GP_PIN(1, 26),
3259};
3260static const unsigned int msiof3_ss1_d_mux[] = {
3261 MSIOF3_SS1_D_MARK,
3262};
3263static const unsigned int msiof3_txd_d_pins[] = {
3264 /* TXD */
3265 RCAR_GP_PIN(1, 25),
3266};
3267static const unsigned int msiof3_txd_d_mux[] = {
3268 MSIOF3_TXD_D_MARK,
3269};
3270static const unsigned int msiof3_rxd_d_pins[] = {
3271 /* RXD */
3272 RCAR_GP_PIN(1, 24),
3273};
3274static const unsigned int msiof3_rxd_d_mux[] = {
3275 MSIOF3_RXD_D_MARK,
3276};
3277static const unsigned int msiof3_clk_e_pins[] = {
3278 /* SCK */
3279 RCAR_GP_PIN(2, 3),
3280};
3281static const unsigned int msiof3_clk_e_mux[] = {
3282 MSIOF3_SCK_E_MARK,
3283};
3284static const unsigned int msiof3_sync_e_pins[] = {
3285 /* SYNC */
3286 RCAR_GP_PIN(2, 2),
3287};
3288static const unsigned int msiof3_sync_e_mux[] = {
3289 MSIOF3_SYNC_E_MARK,
3290};
3291static const unsigned int msiof3_ss1_e_pins[] = {
3292 /* SS1 */
3293 RCAR_GP_PIN(2, 1),
3294};
3295static const unsigned int msiof3_ss1_e_mux[] = {
3296 MSIOF3_SS1_E_MARK,
3297};
3298static const unsigned int msiof3_ss2_e_pins[] = {
3299 /* SS2 */
3300 RCAR_GP_PIN(2, 0),
3301};
3302static const unsigned int msiof3_ss2_e_mux[] = {
3303 MSIOF3_SS2_E_MARK,
3304};
3305static const unsigned int msiof3_txd_e_pins[] = {
3306 /* TXD */
3307 RCAR_GP_PIN(2, 5),
3308};
3309static const unsigned int msiof3_txd_e_mux[] = {
3310 MSIOF3_TXD_E_MARK,
3311};
3312static const unsigned int msiof3_rxd_e_pins[] = {
3313 /* RXD */
3314 RCAR_GP_PIN(2, 4),
3315};
3316static const unsigned int msiof3_rxd_e_mux[] = {
3317 MSIOF3_RXD_E_MARK,
3318};
3319
3320/* - PWM0 --------------------------------------------------------------------*/
3321static const unsigned int pwm0_pins[] = {
3322 /* PWM */
3323 RCAR_GP_PIN(2, 6),
3324};
3325static const unsigned int pwm0_mux[] = {
3326 PWM0_MARK,
3327};
3328/* - PWM1 --------------------------------------------------------------------*/
3329static const unsigned int pwm1_a_pins[] = {
3330 /* PWM */
3331 RCAR_GP_PIN(2, 7),
3332};
3333static const unsigned int pwm1_a_mux[] = {
3334 PWM1_A_MARK,
3335};
3336static const unsigned int pwm1_b_pins[] = {
3337 /* PWM */
3338 RCAR_GP_PIN(1, 8),
3339};
3340static const unsigned int pwm1_b_mux[] = {
3341 PWM1_B_MARK,
3342};
3343/* - PWM2 --------------------------------------------------------------------*/
3344static const unsigned int pwm2_a_pins[] = {
3345 /* PWM */
3346 RCAR_GP_PIN(2, 8),
3347};
3348static const unsigned int pwm2_a_mux[] = {
3349 PWM2_A_MARK,
3350};
3351static const unsigned int pwm2_b_pins[] = {
3352 /* PWM */
3353 RCAR_GP_PIN(1, 11),
3354};
3355static const unsigned int pwm2_b_mux[] = {
3356 PWM2_B_MARK,
3357};
3358/* - PWM3 --------------------------------------------------------------------*/
3359static const unsigned int pwm3_a_pins[] = {
3360 /* PWM */
3361 RCAR_GP_PIN(1, 0),
3362};
3363static const unsigned int pwm3_a_mux[] = {
3364 PWM3_A_MARK,
3365};
3366static const unsigned int pwm3_b_pins[] = {
3367 /* PWM */
3368 RCAR_GP_PIN(2, 2),
3369};
3370static const unsigned int pwm3_b_mux[] = {
3371 PWM3_B_MARK,
3372};
3373/* - PWM4 --------------------------------------------------------------------*/
3374static const unsigned int pwm4_a_pins[] = {
3375 /* PWM */
3376 RCAR_GP_PIN(1, 1),
3377};
3378static const unsigned int pwm4_a_mux[] = {
3379 PWM4_A_MARK,
3380};
3381static const unsigned int pwm4_b_pins[] = {
3382 /* PWM */
3383 RCAR_GP_PIN(2, 3),
3384};
3385static const unsigned int pwm4_b_mux[] = {
3386 PWM4_B_MARK,
3387};
3388/* - PWM5 --------------------------------------------------------------------*/
3389static const unsigned int pwm5_a_pins[] = {
3390 /* PWM */
3391 RCAR_GP_PIN(1, 2),
3392};
3393static const unsigned int pwm5_a_mux[] = {
3394 PWM5_A_MARK,
3395};
3396static const unsigned int pwm5_b_pins[] = {
3397 /* PWM */
3398 RCAR_GP_PIN(2, 4),
3399};
3400static const unsigned int pwm5_b_mux[] = {
3401 PWM5_B_MARK,
3402};
3403/* - PWM6 --------------------------------------------------------------------*/
3404static const unsigned int pwm6_a_pins[] = {
3405 /* PWM */
3406 RCAR_GP_PIN(1, 3),
3407};
3408static const unsigned int pwm6_a_mux[] = {
3409 PWM6_A_MARK,
3410};
3411static const unsigned int pwm6_b_pins[] = {
3412 /* PWM */
3413 RCAR_GP_PIN(2, 5),
3414};
3415static const unsigned int pwm6_b_mux[] = {
3416 PWM6_B_MARK,
3417};
3418
3419/* - SATA --------------------------------------------------------------------*/
3420static const unsigned int sata0_devslp_a_pins[] = {
3421 /* DEVSLP */
3422 RCAR_GP_PIN(6, 16),
3423};
3424
3425static const unsigned int sata0_devslp_a_mux[] = {
3426 SATA_DEVSLP_A_MARK,
3427};
3428
3429static const unsigned int sata0_devslp_b_pins[] = {
3430 /* DEVSLP */
3431 RCAR_GP_PIN(4, 6),
3432};
3433
3434static const unsigned int sata0_devslp_b_mux[] = {
3435 SATA_DEVSLP_B_MARK,
3436};
3437
3438/* - SCIF0 ------------------------------------------------------------------ */
3439static const unsigned int scif0_data_pins[] = {
3440 /* RX, TX */
3441 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3442};
3443static const unsigned int scif0_data_mux[] = {
3444 RX0_MARK, TX0_MARK,
3445};
3446static const unsigned int scif0_clk_pins[] = {
3447 /* SCK */
3448 RCAR_GP_PIN(5, 0),
3449};
3450static const unsigned int scif0_clk_mux[] = {
3451 SCK0_MARK,
3452};
3453static const unsigned int scif0_ctrl_pins[] = {
3454 /* RTS, CTS */
3455 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3456};
3457static const unsigned int scif0_ctrl_mux[] = {
3458 RTS0_N_MARK, CTS0_N_MARK,
3459};
3460/* - SCIF1 ------------------------------------------------------------------ */
3461static const unsigned int scif1_data_a_pins[] = {
3462 /* RX, TX */
3463 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3464};
3465static const unsigned int scif1_data_a_mux[] = {
3466 RX1_A_MARK, TX1_A_MARK,
3467};
3468static const unsigned int scif1_clk_pins[] = {
3469 /* SCK */
3470 RCAR_GP_PIN(6, 21),
3471};
3472static const unsigned int scif1_clk_mux[] = {
3473 SCK1_MARK,
3474};
3475static const unsigned int scif1_ctrl_pins[] = {
3476 /* RTS, CTS */
3477 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3478};
3479static const unsigned int scif1_ctrl_mux[] = {
3480 RTS1_N_MARK, CTS1_N_MARK,
3481};
3482static const unsigned int scif1_data_b_pins[] = {
3483 /* RX, TX */
3484 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3485};
3486static const unsigned int scif1_data_b_mux[] = {
3487 RX1_B_MARK, TX1_B_MARK,
3488};
3489/* - SCIF2 ------------------------------------------------------------------ */
3490static const unsigned int scif2_data_a_pins[] = {
3491 /* RX, TX */
3492 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3493};
3494static const unsigned int scif2_data_a_mux[] = {
3495 RX2_A_MARK, TX2_A_MARK,
3496};
3497static const unsigned int scif2_clk_pins[] = {
3498 /* SCK */
3499 RCAR_GP_PIN(5, 9),
3500};
3501static const unsigned int scif2_clk_mux[] = {
3502 SCK2_MARK,
3503};
3504static const unsigned int scif2_data_b_pins[] = {
3505 /* RX, TX */
3506 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3507};
3508static const unsigned int scif2_data_b_mux[] = {
3509 RX2_B_MARK, TX2_B_MARK,
3510};
3511/* - SCIF3 ------------------------------------------------------------------ */
3512static const unsigned int scif3_data_a_pins[] = {
3513 /* RX, TX */
3514 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3515};
3516static const unsigned int scif3_data_a_mux[] = {
3517 RX3_A_MARK, TX3_A_MARK,
3518};
3519static const unsigned int scif3_clk_pins[] = {
3520 /* SCK */
3521 RCAR_GP_PIN(1, 22),
3522};
3523static const unsigned int scif3_clk_mux[] = {
3524 SCK3_MARK,
3525};
3526static const unsigned int scif3_ctrl_pins[] = {
3527 /* RTS, CTS */
3528 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3529};
3530static const unsigned int scif3_ctrl_mux[] = {
3531 RTS3_N_MARK, CTS3_N_MARK,
3532};
3533static const unsigned int scif3_data_b_pins[] = {
3534 /* RX, TX */
3535 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3536};
3537static const unsigned int scif3_data_b_mux[] = {
3538 RX3_B_MARK, TX3_B_MARK,
3539};
3540/* - SCIF4 ------------------------------------------------------------------ */
3541static const unsigned int scif4_data_a_pins[] = {
3542 /* RX, TX */
3543 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3544};
3545static const unsigned int scif4_data_a_mux[] = {
3546 RX4_A_MARK, TX4_A_MARK,
3547};
3548static const unsigned int scif4_clk_a_pins[] = {
3549 /* SCK */
3550 RCAR_GP_PIN(2, 10),
3551};
3552static const unsigned int scif4_clk_a_mux[] = {
3553 SCK4_A_MARK,
3554};
3555static const unsigned int scif4_ctrl_a_pins[] = {
3556 /* RTS, CTS */
3557 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3558};
3559static const unsigned int scif4_ctrl_a_mux[] = {
3560 RTS4_N_A_MARK, CTS4_N_A_MARK,
3561};
3562static const unsigned int scif4_data_b_pins[] = {
3563 /* RX, TX */
3564 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3565};
3566static const unsigned int scif4_data_b_mux[] = {
3567 RX4_B_MARK, TX4_B_MARK,
3568};
3569static const unsigned int scif4_clk_b_pins[] = {
3570 /* SCK */
3571 RCAR_GP_PIN(1, 5),
3572};
3573static const unsigned int scif4_clk_b_mux[] = {
3574 SCK4_B_MARK,
3575};
3576static const unsigned int scif4_ctrl_b_pins[] = {
3577 /* RTS, CTS */
3578 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3579};
3580static const unsigned int scif4_ctrl_b_mux[] = {
3581 RTS4_N_B_MARK, CTS4_N_B_MARK,
3582};
3583static const unsigned int scif4_data_c_pins[] = {
3584 /* RX, TX */
3585 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3586};
3587static const unsigned int scif4_data_c_mux[] = {
3588 RX4_C_MARK, TX4_C_MARK,
3589};
3590static const unsigned int scif4_clk_c_pins[] = {
3591 /* SCK */
3592 RCAR_GP_PIN(0, 8),
3593};
3594static const unsigned int scif4_clk_c_mux[] = {
3595 SCK4_C_MARK,
3596};
3597static const unsigned int scif4_ctrl_c_pins[] = {
3598 /* RTS, CTS */
3599 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3600};
3601static const unsigned int scif4_ctrl_c_mux[] = {
3602 RTS4_N_C_MARK, CTS4_N_C_MARK,
3603};
3604/* - SCIF5 ------------------------------------------------------------------ */
3605static const unsigned int scif5_data_a_pins[] = {
3606 /* RX, TX */
3607 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3608};
3609static const unsigned int scif5_data_a_mux[] = {
3610 RX5_A_MARK, TX5_A_MARK,
3611};
3612static const unsigned int scif5_clk_a_pins[] = {
3613 /* SCK */
3614 RCAR_GP_PIN(6, 21),
3615};
3616static const unsigned int scif5_clk_a_mux[] = {
3617 SCK5_A_MARK,
3618};
3619static const unsigned int scif5_data_b_pins[] = {
3620 /* RX, TX */
3621 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3622};
3623static const unsigned int scif5_data_b_mux[] = {
3624 RX5_B_MARK, TX5_B_MARK,
3625};
3626static const unsigned int scif5_clk_b_pins[] = {
3627 /* SCK */
3628 RCAR_GP_PIN(5, 0),
3629};
3630static const unsigned int scif5_clk_b_mux[] = {
3631 SCK5_B_MARK,
3632};
3633/* - SCIF Clock ------------------------------------------------------------- */
3634static const unsigned int scif_clk_a_pins[] = {
3635 /* SCIF_CLK */
3636 RCAR_GP_PIN(6, 23),
3637};
3638static const unsigned int scif_clk_a_mux[] = {
3639 SCIF_CLK_A_MARK,
3640};
3641static const unsigned int scif_clk_b_pins[] = {
3642 /* SCIF_CLK */
3643 RCAR_GP_PIN(5, 9),
3644};
3645static const unsigned int scif_clk_b_mux[] = {
3646 SCIF_CLK_B_MARK,
3647};
3648
3649/* - SDHI0 ------------------------------------------------------------------ */
3650static const unsigned int sdhi0_data1_pins[] = {
3651 /* D0 */
3652 RCAR_GP_PIN(3, 2),
3653};
3654
3655static const unsigned int sdhi0_data1_mux[] = {
3656 SD0_DAT0_MARK,
3657};
3658
3659static const unsigned int sdhi0_data4_pins[] = {
3660 /* D[0:3] */
3661 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3662 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3663};
3664
3665static const unsigned int sdhi0_data4_mux[] = {
3666 SD0_DAT0_MARK, SD0_DAT1_MARK,
3667 SD0_DAT2_MARK, SD0_DAT3_MARK,
3668};
3669
3670static const unsigned int sdhi0_ctrl_pins[] = {
3671 /* CLK, CMD */
3672 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3673};
3674
3675static const unsigned int sdhi0_ctrl_mux[] = {
3676 SD0_CLK_MARK, SD0_CMD_MARK,
3677};
3678
3679static const unsigned int sdhi0_cd_pins[] = {
3680 /* CD */
3681 RCAR_GP_PIN(3, 12),
3682};
3683
3684static const unsigned int sdhi0_cd_mux[] = {
3685 SD0_CD_MARK,
3686};
3687
3688static const unsigned int sdhi0_wp_pins[] = {
3689 /* WP */
3690 RCAR_GP_PIN(3, 13),
3691};
3692
3693static const unsigned int sdhi0_wp_mux[] = {
3694 SD0_WP_MARK,
3695};
3696
3697/* - SDHI1 ------------------------------------------------------------------ */
3698static const unsigned int sdhi1_data1_pins[] = {
3699 /* D0 */
3700 RCAR_GP_PIN(3, 8),
3701};
3702
3703static const unsigned int sdhi1_data1_mux[] = {
3704 SD1_DAT0_MARK,
3705};
3706
3707static const unsigned int sdhi1_data4_pins[] = {
3708 /* D[0:3] */
3709 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3710 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3711};
3712
3713static const unsigned int sdhi1_data4_mux[] = {
3714 SD1_DAT0_MARK, SD1_DAT1_MARK,
3715 SD1_DAT2_MARK, SD1_DAT3_MARK,
3716};
3717
3718static const unsigned int sdhi1_ctrl_pins[] = {
3719 /* CLK, CMD */
3720 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3721};
3722
3723static const unsigned int sdhi1_ctrl_mux[] = {
3724 SD1_CLK_MARK, SD1_CMD_MARK,
3725};
3726
3727static const unsigned int sdhi1_cd_pins[] = {
3728 /* CD */
3729 RCAR_GP_PIN(3, 14),
3730};
3731
3732static const unsigned int sdhi1_cd_mux[] = {
3733 SD1_CD_MARK,
3734};
3735
3736static const unsigned int sdhi1_wp_pins[] = {
3737 /* WP */
3738 RCAR_GP_PIN(3, 15),
3739};
3740
3741static const unsigned int sdhi1_wp_mux[] = {
3742 SD1_WP_MARK,
3743};
3744
3745/* - SDHI2 ------------------------------------------------------------------ */
3746static const unsigned int sdhi2_data1_pins[] = {
3747 /* D0 */
3748 RCAR_GP_PIN(4, 2),
3749};
3750
3751static const unsigned int sdhi2_data1_mux[] = {
3752 SD2_DAT0_MARK,
3753};
3754
3755static const unsigned int sdhi2_data4_pins[] = {
3756 /* D[0:3] */
3757 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3758 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3759};
3760
3761static const unsigned int sdhi2_data4_mux[] = {
3762 SD2_DAT0_MARK, SD2_DAT1_MARK,
3763 SD2_DAT2_MARK, SD2_DAT3_MARK,
3764};
3765
3766static const unsigned int sdhi2_data8_pins[] = {
3767 /* D[0:7] */
3768 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3769 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3770 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3771 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3772};
3773
3774static const unsigned int sdhi2_data8_mux[] = {
3775 SD2_DAT0_MARK, SD2_DAT1_MARK,
3776 SD2_DAT2_MARK, SD2_DAT3_MARK,
3777 SD2_DAT4_MARK, SD2_DAT5_MARK,
3778 SD2_DAT6_MARK, SD2_DAT7_MARK,
3779};
3780
3781static const unsigned int sdhi2_ctrl_pins[] = {
3782 /* CLK, CMD */
3783 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3784};
3785
3786static const unsigned int sdhi2_ctrl_mux[] = {
3787 SD2_CLK_MARK, SD2_CMD_MARK,
3788};
3789
3790static const unsigned int sdhi2_cd_a_pins[] = {
3791 /* CD */
3792 RCAR_GP_PIN(4, 13),
3793};
3794
3795static const unsigned int sdhi2_cd_a_mux[] = {
3796 SD2_CD_A_MARK,
3797};
3798
3799static const unsigned int sdhi2_cd_b_pins[] = {
3800 /* CD */
3801 RCAR_GP_PIN(5, 10),
3802};
3803
3804static const unsigned int sdhi2_cd_b_mux[] = {
3805 SD2_CD_B_MARK,
3806};
3807
3808static const unsigned int sdhi2_wp_a_pins[] = {
3809 /* WP */
3810 RCAR_GP_PIN(4, 14),
3811};
3812
3813static const unsigned int sdhi2_wp_a_mux[] = {
3814 SD2_WP_A_MARK,
3815};
3816
3817static const unsigned int sdhi2_wp_b_pins[] = {
3818 /* WP */
3819 RCAR_GP_PIN(5, 11),
3820};
3821
3822static const unsigned int sdhi2_wp_b_mux[] = {
3823 SD2_WP_B_MARK,
3824};
3825
3826static const unsigned int sdhi2_ds_pins[] = {
3827 /* DS */
3828 RCAR_GP_PIN(4, 6),
3829};
3830
3831static const unsigned int sdhi2_ds_mux[] = {
3832 SD2_DS_MARK,
3833};
3834
3835/* - SDHI3 ------------------------------------------------------------------ */
3836static const unsigned int sdhi3_data1_pins[] = {
3837 /* D0 */
3838 RCAR_GP_PIN(4, 9),
3839};
3840
3841static const unsigned int sdhi3_data1_mux[] = {
3842 SD3_DAT0_MARK,
3843};
3844
3845static const unsigned int sdhi3_data4_pins[] = {
3846 /* D[0:3] */
3847 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3848 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3849};
3850
3851static const unsigned int sdhi3_data4_mux[] = {
3852 SD3_DAT0_MARK, SD3_DAT1_MARK,
3853 SD3_DAT2_MARK, SD3_DAT3_MARK,
3854};
3855
3856static const unsigned int sdhi3_data8_pins[] = {
3857 /* D[0:7] */
3858 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3859 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3860 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3861 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3862};
3863
3864static const unsigned int sdhi3_data8_mux[] = {
3865 SD3_DAT0_MARK, SD3_DAT1_MARK,
3866 SD3_DAT2_MARK, SD3_DAT3_MARK,
3867 SD3_DAT4_MARK, SD3_DAT5_MARK,
3868 SD3_DAT6_MARK, SD3_DAT7_MARK,
3869};
3870
3871static const unsigned int sdhi3_ctrl_pins[] = {
3872 /* CLK, CMD */
3873 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3874};
3875
3876static const unsigned int sdhi3_ctrl_mux[] = {
3877 SD3_CLK_MARK, SD3_CMD_MARK,
3878};
3879
3880static const unsigned int sdhi3_cd_pins[] = {
3881 /* CD */
3882 RCAR_GP_PIN(4, 15),
3883};
3884
3885static const unsigned int sdhi3_cd_mux[] = {
3886 SD3_CD_MARK,
3887};
3888
3889static const unsigned int sdhi3_wp_pins[] = {
3890 /* WP */
3891 RCAR_GP_PIN(4, 16),
3892};
3893
3894static const unsigned int sdhi3_wp_mux[] = {
3895 SD3_WP_MARK,
3896};
3897
3898static const unsigned int sdhi3_ds_pins[] = {
3899 /* DS */
3900 RCAR_GP_PIN(4, 17),
3901};
3902
3903static const unsigned int sdhi3_ds_mux[] = {
3904 SD3_DS_MARK,
3905};
3906
3907/* - SSI -------------------------------------------------------------------- */
3908static const unsigned int ssi0_data_pins[] = {
3909 /* SDATA */
3910 RCAR_GP_PIN(6, 2),
3911};
3912static const unsigned int ssi0_data_mux[] = {
3913 SSI_SDATA0_MARK,
3914};
3915static const unsigned int ssi01239_ctrl_pins[] = {
3916 /* SCK, WS */
3917 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3918};
3919static const unsigned int ssi01239_ctrl_mux[] = {
3920 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3921};
3922static const unsigned int ssi1_data_a_pins[] = {
3923 /* SDATA */
3924 RCAR_GP_PIN(6, 3),
3925};
3926static const unsigned int ssi1_data_a_mux[] = {
3927 SSI_SDATA1_A_MARK,
3928};
3929static const unsigned int ssi1_data_b_pins[] = {
3930 /* SDATA */
3931 RCAR_GP_PIN(5, 12),
3932};
3933static const unsigned int ssi1_data_b_mux[] = {
3934 SSI_SDATA1_B_MARK,
3935};
3936static const unsigned int ssi1_ctrl_a_pins[] = {
3937 /* SCK, WS */
3938 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3939};
3940static const unsigned int ssi1_ctrl_a_mux[] = {
3941 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3942};
3943static const unsigned int ssi1_ctrl_b_pins[] = {
3944 /* SCK, WS */
3945 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3946};
3947static const unsigned int ssi1_ctrl_b_mux[] = {
3948 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3949};
3950static const unsigned int ssi2_data_a_pins[] = {
3951 /* SDATA */
3952 RCAR_GP_PIN(6, 4),
3953};
3954static const unsigned int ssi2_data_a_mux[] = {
3955 SSI_SDATA2_A_MARK,
3956};
3957static const unsigned int ssi2_data_b_pins[] = {
3958 /* SDATA */
3959 RCAR_GP_PIN(5, 13),
3960};
3961static const unsigned int ssi2_data_b_mux[] = {
3962 SSI_SDATA2_B_MARK,
3963};
3964static const unsigned int ssi2_ctrl_a_pins[] = {
3965 /* SCK, WS */
3966 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3967};
3968static const unsigned int ssi2_ctrl_a_mux[] = {
3969 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3970};
3971static const unsigned int ssi2_ctrl_b_pins[] = {
3972 /* SCK, WS */
3973 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3974};
3975static const unsigned int ssi2_ctrl_b_mux[] = {
3976 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3977};
3978static const unsigned int ssi3_data_pins[] = {
3979 /* SDATA */
3980 RCAR_GP_PIN(6, 7),
3981};
3982static const unsigned int ssi3_data_mux[] = {
3983 SSI_SDATA3_MARK,
3984};
3985static const unsigned int ssi349_ctrl_pins[] = {
3986 /* SCK, WS */
3987 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3988};
3989static const unsigned int ssi349_ctrl_mux[] = {
3990 SSI_SCK349_MARK, SSI_WS349_MARK,
3991};
3992static const unsigned int ssi4_data_pins[] = {
3993 /* SDATA */
3994 RCAR_GP_PIN(6, 10),
3995};
3996static const unsigned int ssi4_data_mux[] = {
3997 SSI_SDATA4_MARK,
3998};
3999static const unsigned int ssi4_ctrl_pins[] = {
4000 /* SCK, WS */
4001 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
4002};
4003static const unsigned int ssi4_ctrl_mux[] = {
4004 SSI_SCK4_MARK, SSI_WS4_MARK,
4005};
4006static const unsigned int ssi5_data_pins[] = {
4007 /* SDATA */
4008 RCAR_GP_PIN(6, 13),
4009};
4010static const unsigned int ssi5_data_mux[] = {
4011 SSI_SDATA5_MARK,
4012};
4013static const unsigned int ssi5_ctrl_pins[] = {
4014 /* SCK, WS */
4015 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
4016};
4017static const unsigned int ssi5_ctrl_mux[] = {
4018 SSI_SCK5_MARK, SSI_WS5_MARK,
4019};
4020static const unsigned int ssi6_data_pins[] = {
4021 /* SDATA */
4022 RCAR_GP_PIN(6, 16),
4023};
4024static const unsigned int ssi6_data_mux[] = {
4025 SSI_SDATA6_MARK,
4026};
4027static const unsigned int ssi6_ctrl_pins[] = {
4028 /* SCK, WS */
4029 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4030};
4031static const unsigned int ssi6_ctrl_mux[] = {
4032 SSI_SCK6_MARK, SSI_WS6_MARK,
4033};
4034static const unsigned int ssi7_data_pins[] = {
4035 /* SDATA */
4036 RCAR_GP_PIN(6, 19),
4037};
4038static const unsigned int ssi7_data_mux[] = {
4039 SSI_SDATA7_MARK,
4040};
4041static const unsigned int ssi78_ctrl_pins[] = {
4042 /* SCK, WS */
4043 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4044};
4045static const unsigned int ssi78_ctrl_mux[] = {
4046 SSI_SCK78_MARK, SSI_WS78_MARK,
4047};
4048static const unsigned int ssi8_data_pins[] = {
4049 /* SDATA */
4050 RCAR_GP_PIN(6, 20),
4051};
4052static const unsigned int ssi8_data_mux[] = {
4053 SSI_SDATA8_MARK,
4054};
4055static const unsigned int ssi9_data_a_pins[] = {
4056 /* SDATA */
4057 RCAR_GP_PIN(6, 21),
4058};
4059static const unsigned int ssi9_data_a_mux[] = {
4060 SSI_SDATA9_A_MARK,
4061};
4062static const unsigned int ssi9_data_b_pins[] = {
4063 /* SDATA */
4064 RCAR_GP_PIN(5, 14),
4065};
4066static const unsigned int ssi9_data_b_mux[] = {
4067 SSI_SDATA9_B_MARK,
4068};
4069static const unsigned int ssi9_ctrl_a_pins[] = {
4070 /* SCK, WS */
4071 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4072};
4073static const unsigned int ssi9_ctrl_a_mux[] = {
4074 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4075};
4076static const unsigned int ssi9_ctrl_b_pins[] = {
4077 /* SCK, WS */
4078 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4079};
4080static const unsigned int ssi9_ctrl_b_mux[] = {
4081 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4082};
4083
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]4084/* - TMU -------------------------------------------------------------------- */
4085static const unsigned int tmu_tclk1_a_pins[] = {
4086 /* TCLK */
4087 RCAR_GP_PIN(6, 23),
4088};
4089
4090static const unsigned int tmu_tclk1_a_mux[] = {
4091 TCLK1_A_MARK,
4092};
4093
4094static const unsigned int tmu_tclk1_b_pins[] = {
4095 /* TCLK */
4096 RCAR_GP_PIN(5, 19),
4097};
4098
4099static const unsigned int tmu_tclk1_b_mux[] = {
4100 TCLK1_B_MARK,
4101};
4102
4103static const unsigned int tmu_tclk2_a_pins[] = {
4104 /* TCLK */
4105 RCAR_GP_PIN(6, 19),
4106};
4107
4108static const unsigned int tmu_tclk2_a_mux[] = {
4109 TCLK2_A_MARK,
4110};
4111
4112static const unsigned int tmu_tclk2_b_pins[] = {
4113 /* TCLK */
4114 RCAR_GP_PIN(6, 28),
4115};
4116
4117static const unsigned int tmu_tclk2_b_mux[] = {
4118 TCLK2_B_MARK,
4119};
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]4120
4121/* - USB0 ------------------------------------------------------------------- */
4122static const unsigned int usb0_pins[] = {
4123 /* PWEN, OVC */
4124 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4125};
4126
4127static const unsigned int usb0_mux[] = {
4128 USB0_PWEN_MARK, USB0_OVC_MARK,
4129};
4130
4131/* - USB1 ------------------------------------------------------------------- */
4132static const unsigned int usb1_pins[] = {
4133 /* PWEN, OVC */
4134 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4135};
4136
4137static const unsigned int usb1_mux[] = {
4138 USB1_PWEN_MARK, USB1_OVC_MARK,
4139};
4140
4141/* - USB30 ------------------------------------------------------------------ */
4142static const unsigned int usb30_pins[] = {
4143 /* PWEN, OVC */
4144 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4145};
4146
4147static const unsigned int usb30_mux[] = {
4148 USB30_PWEN_MARK, USB30_OVC_MARK,
4149};
4150
4151/* - VIN4 ------------------------------------------------------------------- */
4152static const unsigned int vin4_data18_a_pins[] = {
4153 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4154 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4155 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4156 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4157 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4158 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4159 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4160 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4161 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4162};
4163
4164static const unsigned int vin4_data18_a_mux[] = {
4165 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4166 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4167 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4168 VI4_DATA10_MARK, VI4_DATA11_MARK,
4169 VI4_DATA12_MARK, VI4_DATA13_MARK,
4170 VI4_DATA14_MARK, VI4_DATA15_MARK,
4171 VI4_DATA18_MARK, VI4_DATA19_MARK,
4172 VI4_DATA20_MARK, VI4_DATA21_MARK,
4173 VI4_DATA22_MARK, VI4_DATA23_MARK,
4174};
4175
4176static const union vin_data vin4_data_a_pins = {
4177 .data24 = {
4178 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4179 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4180 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4181 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4182 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4183 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4184 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4185 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4186 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4187 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4188 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4189 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4190 },
4191};
4192
4193static const union vin_data vin4_data_a_mux = {
4194 .data24 = {
4195 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4196 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4197 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4198 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4199 VI4_DATA8_MARK, VI4_DATA9_MARK,
4200 VI4_DATA10_MARK, VI4_DATA11_MARK,
4201 VI4_DATA12_MARK, VI4_DATA13_MARK,
4202 VI4_DATA14_MARK, VI4_DATA15_MARK,
4203 VI4_DATA16_MARK, VI4_DATA17_MARK,
4204 VI4_DATA18_MARK, VI4_DATA19_MARK,
4205 VI4_DATA20_MARK, VI4_DATA21_MARK,
4206 VI4_DATA22_MARK, VI4_DATA23_MARK,
4207 },
4208};
4209
4210static const unsigned int vin4_data18_b_pins[] = {
4211 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4212 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4213 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4214 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4215 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4216 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4217 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4218 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4219 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4220};
4221
4222static const unsigned int vin4_data18_b_mux[] = {
4223 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4224 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4225 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4226 VI4_DATA10_MARK, VI4_DATA11_MARK,
4227 VI4_DATA12_MARK, VI4_DATA13_MARK,
4228 VI4_DATA14_MARK, VI4_DATA15_MARK,
4229 VI4_DATA18_MARK, VI4_DATA19_MARK,
4230 VI4_DATA20_MARK, VI4_DATA21_MARK,
4231 VI4_DATA22_MARK, VI4_DATA23_MARK,
4232};
4233
4234static const union vin_data vin4_data_b_pins = {
4235 .data24 = {
4236 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4237 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4238 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4239 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4240 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4241 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4242 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4243 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4244 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4245 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4246 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4247 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4248 },
4249};
4250
4251static const union vin_data vin4_data_b_mux = {
4252 .data24 = {
4253 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4254 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4255 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4256 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4257 VI4_DATA8_MARK, VI4_DATA9_MARK,
4258 VI4_DATA10_MARK, VI4_DATA11_MARK,
4259 VI4_DATA12_MARK, VI4_DATA13_MARK,
4260 VI4_DATA14_MARK, VI4_DATA15_MARK,
4261 VI4_DATA16_MARK, VI4_DATA17_MARK,
4262 VI4_DATA18_MARK, VI4_DATA19_MARK,
4263 VI4_DATA20_MARK, VI4_DATA21_MARK,
4264 VI4_DATA22_MARK, VI4_DATA23_MARK,
4265 },
4266};
4267
4268static const unsigned int vin4_sync_pins[] = {
4269 /* VSYNC_N, HSYNC_N */
4270 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4271};
4272
4273static const unsigned int vin4_sync_mux[] = {
4274 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4275};
4276
4277static const unsigned int vin4_field_pins[] = {
4278 RCAR_GP_PIN(1, 16),
4279};
4280
4281static const unsigned int vin4_field_mux[] = {
4282 VI4_FIELD_MARK,
4283};
4284
4285static const unsigned int vin4_clkenb_pins[] = {
4286 RCAR_GP_PIN(1, 19),
4287};
4288
4289static const unsigned int vin4_clkenb_mux[] = {
4290 VI4_CLKENB_MARK,
4291};
4292
4293static const unsigned int vin4_clk_pins[] = {
4294 RCAR_GP_PIN(1, 27),
4295};
4296
4297static const unsigned int vin4_clk_mux[] = {
4298 VI4_CLK_MARK,
4299};
4300
4301/* - VIN5 ------------------------------------------------------------------- */
4302static const union vin_data16 vin5_data_pins = {
4303 .data16 = {
4304 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4305 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4306 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4307 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4308 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4309 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4310 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4311 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4312 },
4313};
4314
4315static const union vin_data16 vin5_data_mux = {
4316 .data16 = {
4317 VI5_DATA0_MARK, VI5_DATA1_MARK,
4318 VI5_DATA2_MARK, VI5_DATA3_MARK,
4319 VI5_DATA4_MARK, VI5_DATA5_MARK,
4320 VI5_DATA6_MARK, VI5_DATA7_MARK,
4321 VI5_DATA8_MARK, VI5_DATA9_MARK,
4322 VI5_DATA10_MARK, VI5_DATA11_MARK,
4323 VI5_DATA12_MARK, VI5_DATA13_MARK,
4324 VI5_DATA14_MARK, VI5_DATA15_MARK,
4325 },
4326};
4327
4328static const unsigned int vin5_sync_pins[] = {
4329 /* VSYNC_N, HSYNC_N */
4330 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4331};
4332
4333static const unsigned int vin5_sync_mux[] = {
4334 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4335};
4336
4337static const unsigned int vin5_field_pins[] = {
4338 RCAR_GP_PIN(1, 11),
4339};
4340
4341static const unsigned int vin5_field_mux[] = {
4342 VI5_FIELD_MARK,
4343};
4344
4345static const unsigned int vin5_clkenb_pins[] = {
4346 RCAR_GP_PIN(1, 20),
4347};
4348
4349static const unsigned int vin5_clkenb_mux[] = {
4350 VI5_CLKENB_MARK,
4351};
4352
4353static const unsigned int vin5_clk_pins[] = {
4354 RCAR_GP_PIN(1, 21),
4355};
4356
4357static const unsigned int vin5_clk_mux[] = {
4358 VI5_CLK_MARK,
4359};
4360
4361static const struct sh_pfc_pin_group pinmux_groups[] = {
4362 SH_PFC_PIN_GROUP(audio_clk_a_a),
4363 SH_PFC_PIN_GROUP(audio_clk_a_b),
4364 SH_PFC_PIN_GROUP(audio_clk_a_c),
4365 SH_PFC_PIN_GROUP(audio_clk_b_a),
4366 SH_PFC_PIN_GROUP(audio_clk_b_b),
4367 SH_PFC_PIN_GROUP(audio_clk_c_a),
4368 SH_PFC_PIN_GROUP(audio_clk_c_b),
4369 SH_PFC_PIN_GROUP(audio_clkout_a),
4370 SH_PFC_PIN_GROUP(audio_clkout_b),
4371 SH_PFC_PIN_GROUP(audio_clkout_c),
4372 SH_PFC_PIN_GROUP(audio_clkout_d),
4373 SH_PFC_PIN_GROUP(audio_clkout1_a),
4374 SH_PFC_PIN_GROUP(audio_clkout1_b),
4375 SH_PFC_PIN_GROUP(audio_clkout2_a),
4376 SH_PFC_PIN_GROUP(audio_clkout2_b),
4377 SH_PFC_PIN_GROUP(audio_clkout3_a),
4378 SH_PFC_PIN_GROUP(audio_clkout3_b),
4379 SH_PFC_PIN_GROUP(avb_link),
4380 SH_PFC_PIN_GROUP(avb_magic),
4381 SH_PFC_PIN_GROUP(avb_phy_int),
4382 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4383 SH_PFC_PIN_GROUP(avb_mdio),
4384 SH_PFC_PIN_GROUP(avb_mii),
4385 SH_PFC_PIN_GROUP(avb_avtp_pps),
4386 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4387 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4388 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4389 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4390 SH_PFC_PIN_GROUP(can0_data_a),
4391 SH_PFC_PIN_GROUP(can0_data_b),
4392 SH_PFC_PIN_GROUP(can1_data),
4393 SH_PFC_PIN_GROUP(can_clk),
4394 SH_PFC_PIN_GROUP(canfd0_data_a),
4395 SH_PFC_PIN_GROUP(canfd0_data_b),
4396 SH_PFC_PIN_GROUP(canfd1_data),
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]4397 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4398 SH_PFC_PIN_GROUP(drif0_data0_a),
4399 SH_PFC_PIN_GROUP(drif0_data1_a),
4400 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4401 SH_PFC_PIN_GROUP(drif0_data0_b),
4402 SH_PFC_PIN_GROUP(drif0_data1_b),
4403 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4404 SH_PFC_PIN_GROUP(drif0_data0_c),
4405 SH_PFC_PIN_GROUP(drif0_data1_c),
4406 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4407 SH_PFC_PIN_GROUP(drif1_data0_a),
4408 SH_PFC_PIN_GROUP(drif1_data1_a),
4409 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4410 SH_PFC_PIN_GROUP(drif1_data0_b),
4411 SH_PFC_PIN_GROUP(drif1_data1_b),
4412 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4413 SH_PFC_PIN_GROUP(drif1_data0_c),
4414 SH_PFC_PIN_GROUP(drif1_data1_c),
4415 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4416 SH_PFC_PIN_GROUP(drif2_data0_a),
4417 SH_PFC_PIN_GROUP(drif2_data1_a),
4418 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4419 SH_PFC_PIN_GROUP(drif2_data0_b),
4420 SH_PFC_PIN_GROUP(drif2_data1_b),
4421 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4422 SH_PFC_PIN_GROUP(drif3_data0_a),
4423 SH_PFC_PIN_GROUP(drif3_data1_a),
4424 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4425 SH_PFC_PIN_GROUP(drif3_data0_b),
4426 SH_PFC_PIN_GROUP(drif3_data1_b),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]4427 SH_PFC_PIN_GROUP(du_rgb666),
4428 SH_PFC_PIN_GROUP(du_rgb888),
4429 SH_PFC_PIN_GROUP(du_clk_out_0),
4430 SH_PFC_PIN_GROUP(du_clk_out_1),
4431 SH_PFC_PIN_GROUP(du_sync),
4432 SH_PFC_PIN_GROUP(du_oddf),
4433 SH_PFC_PIN_GROUP(du_cde),
4434 SH_PFC_PIN_GROUP(du_disp),
4435 SH_PFC_PIN_GROUP(hscif0_data),
4436 SH_PFC_PIN_GROUP(hscif0_clk),
4437 SH_PFC_PIN_GROUP(hscif0_ctrl),
4438 SH_PFC_PIN_GROUP(hscif1_data_a),
4439 SH_PFC_PIN_GROUP(hscif1_clk_a),
4440 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4441 SH_PFC_PIN_GROUP(hscif1_data_b),
4442 SH_PFC_PIN_GROUP(hscif1_clk_b),
4443 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4444 SH_PFC_PIN_GROUP(hscif2_data_a),
4445 SH_PFC_PIN_GROUP(hscif2_clk_a),
4446 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4447 SH_PFC_PIN_GROUP(hscif2_data_b),
4448 SH_PFC_PIN_GROUP(hscif2_clk_b),
4449 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4450 SH_PFC_PIN_GROUP(hscif2_data_c),
4451 SH_PFC_PIN_GROUP(hscif2_clk_c),
4452 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4453 SH_PFC_PIN_GROUP(hscif3_data_a),
4454 SH_PFC_PIN_GROUP(hscif3_clk),
4455 SH_PFC_PIN_GROUP(hscif3_ctrl),
4456 SH_PFC_PIN_GROUP(hscif3_data_b),
4457 SH_PFC_PIN_GROUP(hscif3_data_c),
4458 SH_PFC_PIN_GROUP(hscif3_data_d),
4459 SH_PFC_PIN_GROUP(hscif4_data_a),
4460 SH_PFC_PIN_GROUP(hscif4_clk),
4461 SH_PFC_PIN_GROUP(hscif4_ctrl),
4462 SH_PFC_PIN_GROUP(hscif4_data_b),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]4463 SH_PFC_PIN_GROUP(i2c0),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]4464 SH_PFC_PIN_GROUP(i2c1_a),
4465 SH_PFC_PIN_GROUP(i2c1_b),
4466 SH_PFC_PIN_GROUP(i2c2_a),
4467 SH_PFC_PIN_GROUP(i2c2_b),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]4468 SH_PFC_PIN_GROUP(i2c3),
4469 SH_PFC_PIN_GROUP(i2c5),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]4470 SH_PFC_PIN_GROUP(i2c6_a),
4471 SH_PFC_PIN_GROUP(i2c6_b),
4472 SH_PFC_PIN_GROUP(i2c6_c),
4473 SH_PFC_PIN_GROUP(intc_ex_irq0),
4474 SH_PFC_PIN_GROUP(intc_ex_irq1),
4475 SH_PFC_PIN_GROUP(intc_ex_irq2),
4476 SH_PFC_PIN_GROUP(intc_ex_irq3),
4477 SH_PFC_PIN_GROUP(intc_ex_irq4),
4478 SH_PFC_PIN_GROUP(intc_ex_irq5),
4479 SH_PFC_PIN_GROUP(msiof0_clk),
4480 SH_PFC_PIN_GROUP(msiof0_sync),
4481 SH_PFC_PIN_GROUP(msiof0_ss1),
4482 SH_PFC_PIN_GROUP(msiof0_ss2),
4483 SH_PFC_PIN_GROUP(msiof0_txd),
4484 SH_PFC_PIN_GROUP(msiof0_rxd),
4485 SH_PFC_PIN_GROUP(msiof1_clk_a),
4486 SH_PFC_PIN_GROUP(msiof1_sync_a),
4487 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4488 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4489 SH_PFC_PIN_GROUP(msiof1_txd_a),
4490 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4491 SH_PFC_PIN_GROUP(msiof1_clk_b),
4492 SH_PFC_PIN_GROUP(msiof1_sync_b),
4493 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4494 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4495 SH_PFC_PIN_GROUP(msiof1_txd_b),
4496 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4497 SH_PFC_PIN_GROUP(msiof1_clk_c),
4498 SH_PFC_PIN_GROUP(msiof1_sync_c),
4499 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4500 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4501 SH_PFC_PIN_GROUP(msiof1_txd_c),
4502 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4503 SH_PFC_PIN_GROUP(msiof1_clk_d),
4504 SH_PFC_PIN_GROUP(msiof1_sync_d),
4505 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4506 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4507 SH_PFC_PIN_GROUP(msiof1_txd_d),
4508 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4509 SH_PFC_PIN_GROUP(msiof1_clk_e),
4510 SH_PFC_PIN_GROUP(msiof1_sync_e),
4511 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4512 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4513 SH_PFC_PIN_GROUP(msiof1_txd_e),
4514 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4515 SH_PFC_PIN_GROUP(msiof1_clk_f),
4516 SH_PFC_PIN_GROUP(msiof1_sync_f),
4517 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4518 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4519 SH_PFC_PIN_GROUP(msiof1_txd_f),
4520 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4521 SH_PFC_PIN_GROUP(msiof1_clk_g),
4522 SH_PFC_PIN_GROUP(msiof1_sync_g),
4523 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4524 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4525 SH_PFC_PIN_GROUP(msiof1_txd_g),
4526 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4527 SH_PFC_PIN_GROUP(msiof2_clk_a),
4528 SH_PFC_PIN_GROUP(msiof2_sync_a),
4529 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4530 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4531 SH_PFC_PIN_GROUP(msiof2_txd_a),
4532 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4533 SH_PFC_PIN_GROUP(msiof2_clk_b),
4534 SH_PFC_PIN_GROUP(msiof2_sync_b),
4535 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4536 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4537 SH_PFC_PIN_GROUP(msiof2_txd_b),
4538 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4539 SH_PFC_PIN_GROUP(msiof2_clk_c),
4540 SH_PFC_PIN_GROUP(msiof2_sync_c),
4541 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4542 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4543 SH_PFC_PIN_GROUP(msiof2_txd_c),
4544 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4545 SH_PFC_PIN_GROUP(msiof2_clk_d),
4546 SH_PFC_PIN_GROUP(msiof2_sync_d),
4547 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4548 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4549 SH_PFC_PIN_GROUP(msiof2_txd_d),
4550 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4551 SH_PFC_PIN_GROUP(msiof3_clk_a),
4552 SH_PFC_PIN_GROUP(msiof3_sync_a),
4553 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4554 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4555 SH_PFC_PIN_GROUP(msiof3_txd_a),
4556 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4557 SH_PFC_PIN_GROUP(msiof3_clk_b),
4558 SH_PFC_PIN_GROUP(msiof3_sync_b),
4559 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4560 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4561 SH_PFC_PIN_GROUP(msiof3_txd_b),
4562 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4563 SH_PFC_PIN_GROUP(msiof3_clk_c),
4564 SH_PFC_PIN_GROUP(msiof3_sync_c),
4565 SH_PFC_PIN_GROUP(msiof3_txd_c),
4566 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4567 SH_PFC_PIN_GROUP(msiof3_clk_d),
4568 SH_PFC_PIN_GROUP(msiof3_sync_d),
4569 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4570 SH_PFC_PIN_GROUP(msiof3_txd_d),
4571 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4572 SH_PFC_PIN_GROUP(msiof3_clk_e),
4573 SH_PFC_PIN_GROUP(msiof3_sync_e),
4574 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4575 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4576 SH_PFC_PIN_GROUP(msiof3_txd_e),
4577 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4578 SH_PFC_PIN_GROUP(pwm0),
4579 SH_PFC_PIN_GROUP(pwm1_a),
4580 SH_PFC_PIN_GROUP(pwm1_b),
4581 SH_PFC_PIN_GROUP(pwm2_a),
4582 SH_PFC_PIN_GROUP(pwm2_b),
4583 SH_PFC_PIN_GROUP(pwm3_a),
4584 SH_PFC_PIN_GROUP(pwm3_b),
4585 SH_PFC_PIN_GROUP(pwm4_a),
4586 SH_PFC_PIN_GROUP(pwm4_b),
4587 SH_PFC_PIN_GROUP(pwm5_a),
4588 SH_PFC_PIN_GROUP(pwm5_b),
4589 SH_PFC_PIN_GROUP(pwm6_a),
4590 SH_PFC_PIN_GROUP(pwm6_b),
4591 SH_PFC_PIN_GROUP(sata0_devslp_a),
4592 SH_PFC_PIN_GROUP(sata0_devslp_b),
4593 SH_PFC_PIN_GROUP(scif0_data),
4594 SH_PFC_PIN_GROUP(scif0_clk),
4595 SH_PFC_PIN_GROUP(scif0_ctrl),
4596 SH_PFC_PIN_GROUP(scif1_data_a),
4597 SH_PFC_PIN_GROUP(scif1_clk),
4598 SH_PFC_PIN_GROUP(scif1_ctrl),
4599 SH_PFC_PIN_GROUP(scif1_data_b),
4600 SH_PFC_PIN_GROUP(scif2_data_a),
4601 SH_PFC_PIN_GROUP(scif2_clk),
4602 SH_PFC_PIN_GROUP(scif2_data_b),
4603 SH_PFC_PIN_GROUP(scif3_data_a),
4604 SH_PFC_PIN_GROUP(scif3_clk),
4605 SH_PFC_PIN_GROUP(scif3_ctrl),
4606 SH_PFC_PIN_GROUP(scif3_data_b),
4607 SH_PFC_PIN_GROUP(scif4_data_a),
4608 SH_PFC_PIN_GROUP(scif4_clk_a),
4609 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4610 SH_PFC_PIN_GROUP(scif4_data_b),
4611 SH_PFC_PIN_GROUP(scif4_clk_b),
4612 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4613 SH_PFC_PIN_GROUP(scif4_data_c),
4614 SH_PFC_PIN_GROUP(scif4_clk_c),
4615 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4616 SH_PFC_PIN_GROUP(scif5_data_a),
4617 SH_PFC_PIN_GROUP(scif5_clk_a),
4618 SH_PFC_PIN_GROUP(scif5_data_b),
4619 SH_PFC_PIN_GROUP(scif5_clk_b),
4620 SH_PFC_PIN_GROUP(scif_clk_a),
4621 SH_PFC_PIN_GROUP(scif_clk_b),
4622 SH_PFC_PIN_GROUP(sdhi0_data1),
4623 SH_PFC_PIN_GROUP(sdhi0_data4),
4624 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4625 SH_PFC_PIN_GROUP(sdhi0_cd),
4626 SH_PFC_PIN_GROUP(sdhi0_wp),
4627 SH_PFC_PIN_GROUP(sdhi1_data1),
4628 SH_PFC_PIN_GROUP(sdhi1_data4),
4629 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4630 SH_PFC_PIN_GROUP(sdhi1_cd),
4631 SH_PFC_PIN_GROUP(sdhi1_wp),
4632 SH_PFC_PIN_GROUP(sdhi2_data1),
4633 SH_PFC_PIN_GROUP(sdhi2_data4),
4634 SH_PFC_PIN_GROUP(sdhi2_data8),
4635 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4636 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4637 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4638 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4639 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4640 SH_PFC_PIN_GROUP(sdhi2_ds),
4641 SH_PFC_PIN_GROUP(sdhi3_data1),
4642 SH_PFC_PIN_GROUP(sdhi3_data4),
4643 SH_PFC_PIN_GROUP(sdhi3_data8),
4644 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4645 SH_PFC_PIN_GROUP(sdhi3_cd),
4646 SH_PFC_PIN_GROUP(sdhi3_wp),
4647 SH_PFC_PIN_GROUP(sdhi3_ds),
4648 SH_PFC_PIN_GROUP(ssi0_data),
4649 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4650 SH_PFC_PIN_GROUP(ssi1_data_a),
4651 SH_PFC_PIN_GROUP(ssi1_data_b),
4652 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4653 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4654 SH_PFC_PIN_GROUP(ssi2_data_a),
4655 SH_PFC_PIN_GROUP(ssi2_data_b),
4656 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4657 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4658 SH_PFC_PIN_GROUP(ssi3_data),
4659 SH_PFC_PIN_GROUP(ssi349_ctrl),
4660 SH_PFC_PIN_GROUP(ssi4_data),
4661 SH_PFC_PIN_GROUP(ssi4_ctrl),
4662 SH_PFC_PIN_GROUP(ssi5_data),
4663 SH_PFC_PIN_GROUP(ssi5_ctrl),
4664 SH_PFC_PIN_GROUP(ssi6_data),
4665 SH_PFC_PIN_GROUP(ssi6_ctrl),
4666 SH_PFC_PIN_GROUP(ssi7_data),
4667 SH_PFC_PIN_GROUP(ssi78_ctrl),
4668 SH_PFC_PIN_GROUP(ssi8_data),
4669 SH_PFC_PIN_GROUP(ssi9_data_a),
4670 SH_PFC_PIN_GROUP(ssi9_data_b),
4671 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4672 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]4673 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4674 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4675 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4676 SH_PFC_PIN_GROUP(tmu_tclk2_b),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]4677 SH_PFC_PIN_GROUP(usb0),
4678 SH_PFC_PIN_GROUP(usb1),
4679 SH_PFC_PIN_GROUP(usb30),
4680 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4681 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4682 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4683 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4684 SH_PFC_PIN_GROUP(vin4_data18_a),
4685 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4686 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4687 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4688 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4689 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4690 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4691 SH_PFC_PIN_GROUP(vin4_data18_b),
4692 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4693 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4694 SH_PFC_PIN_GROUP(vin4_sync),
4695 SH_PFC_PIN_GROUP(vin4_field),
4696 SH_PFC_PIN_GROUP(vin4_clkenb),
4697 SH_PFC_PIN_GROUP(vin4_clk),
4698 VIN_DATA_PIN_GROUP(vin5_data, 8),
4699 VIN_DATA_PIN_GROUP(vin5_data, 10),
4700 VIN_DATA_PIN_GROUP(vin5_data, 12),
4701 VIN_DATA_PIN_GROUP(vin5_data, 16),
4702 SH_PFC_PIN_GROUP(vin5_sync),
4703 SH_PFC_PIN_GROUP(vin5_field),
4704 SH_PFC_PIN_GROUP(vin5_clkenb),
4705 SH_PFC_PIN_GROUP(vin5_clk),
4706};
4707
4708static const char * const audio_clk_groups[] = {
4709 "audio_clk_a_a",
4710 "audio_clk_a_b",
4711 "audio_clk_a_c",
4712 "audio_clk_b_a",
4713 "audio_clk_b_b",
4714 "audio_clk_c_a",
4715 "audio_clk_c_b",
4716 "audio_clkout_a",
4717 "audio_clkout_b",
4718 "audio_clkout_c",
4719 "audio_clkout_d",
4720 "audio_clkout1_a",
4721 "audio_clkout1_b",
4722 "audio_clkout2_a",
4723 "audio_clkout2_b",
4724 "audio_clkout3_a",
4725 "audio_clkout3_b",
4726};
4727
4728static const char * const avb_groups[] = {
4729 "avb_link",
4730 "avb_magic",
4731 "avb_phy_int",
4732 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4733 "avb_mdio",
4734 "avb_mii",
4735 "avb_avtp_pps",
4736 "avb_avtp_match_a",
4737 "avb_avtp_capture_a",
4738 "avb_avtp_match_b",
4739 "avb_avtp_capture_b",
4740};
4741
4742static const char * const can0_groups[] = {
4743 "can0_data_a",
4744 "can0_data_b",
4745};
4746
4747static const char * const can1_groups[] = {
4748 "can1_data",
4749};
4750
4751static const char * const can_clk_groups[] = {
4752 "can_clk",
4753};
4754
4755static const char * const canfd0_groups[] = {
4756 "canfd0_data_a",
4757 "canfd0_data_b",
4758};
4759
4760static const char * const canfd1_groups[] = {
4761 "canfd1_data",
4762};
4763
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]4764static const char * const drif0_groups[] = {
4765 "drif0_ctrl_a",
4766 "drif0_data0_a",
4767 "drif0_data1_a",
4768 "drif0_ctrl_b",
4769 "drif0_data0_b",
4770 "drif0_data1_b",
4771 "drif0_ctrl_c",
4772 "drif0_data0_c",
4773 "drif0_data1_c",
4774};
4775
4776static const char * const drif1_groups[] = {
4777 "drif1_ctrl_a",
4778 "drif1_data0_a",
4779 "drif1_data1_a",
4780 "drif1_ctrl_b",
4781 "drif1_data0_b",
4782 "drif1_data1_b",
4783 "drif1_ctrl_c",
4784 "drif1_data0_c",
4785 "drif1_data1_c",
4786};
4787
4788static const char * const drif2_groups[] = {
4789 "drif2_ctrl_a",
4790 "drif2_data0_a",
4791 "drif2_data1_a",
4792 "drif2_ctrl_b",
4793 "drif2_data0_b",
4794 "drif2_data1_b",
4795};
4796
4797static const char * const drif3_groups[] = {
4798 "drif3_ctrl_a",
4799 "drif3_data0_a",
4800 "drif3_data1_a",
4801 "drif3_ctrl_b",
4802 "drif3_data0_b",
4803 "drif3_data1_b",
4804};
4805
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]4806static const char * const du_groups[] = {
4807 "du_rgb666",
4808 "du_rgb888",
4809 "du_clk_out_0",
4810 "du_clk_out_1",
4811 "du_sync",
4812 "du_oddf",
4813 "du_cde",
4814 "du_disp",
4815};
4816
4817static const char * const hscif0_groups[] = {
4818 "hscif0_data",
4819 "hscif0_clk",
4820 "hscif0_ctrl",
4821};
4822
4823static const char * const hscif1_groups[] = {
4824 "hscif1_data_a",
4825 "hscif1_clk_a",
4826 "hscif1_ctrl_a",
4827 "hscif1_data_b",
4828 "hscif1_clk_b",
4829 "hscif1_ctrl_b",
4830};
4831
4832static const char * const hscif2_groups[] = {
4833 "hscif2_data_a",
4834 "hscif2_clk_a",
4835 "hscif2_ctrl_a",
4836 "hscif2_data_b",
4837 "hscif2_clk_b",
4838 "hscif2_ctrl_b",
4839 "hscif2_data_c",
4840 "hscif2_clk_c",
4841 "hscif2_ctrl_c",
4842};
4843
4844static const char * const hscif3_groups[] = {
4845 "hscif3_data_a",
4846 "hscif3_clk",
4847 "hscif3_ctrl",
4848 "hscif3_data_b",
4849 "hscif3_data_c",
4850 "hscif3_data_d",
4851};
4852
4853static const char * const hscif4_groups[] = {
4854 "hscif4_data_a",
4855 "hscif4_clk",
4856 "hscif4_ctrl",
4857 "hscif4_data_b",
4858};
4859
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]4860static const char * const i2c0_groups[] = {
4861 "i2c0",
4862};
4863
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]4864static const char * const i2c1_groups[] = {
4865 "i2c1_a",
4866 "i2c1_b",
4867};
4868
4869static const char * const i2c2_groups[] = {
4870 "i2c2_a",
4871 "i2c2_b",
4872};
4873
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]4874static const char * const i2c3_groups[] = {
4875 "i2c3",
4876};
4877
4878static const char * const i2c5_groups[] = {
4879 "i2c5",
4880};
4881
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]4882static const char * const i2c6_groups[] = {
4883 "i2c6_a",
4884 "i2c6_b",
4885 "i2c6_c",
4886};
4887
4888static const char * const intc_ex_groups[] = {
4889 "intc_ex_irq0",
4890 "intc_ex_irq1",
4891 "intc_ex_irq2",
4892 "intc_ex_irq3",
4893 "intc_ex_irq4",
4894 "intc_ex_irq5",
4895};
4896
4897static const char * const msiof0_groups[] = {
4898 "msiof0_clk",
4899 "msiof0_sync",
4900 "msiof0_ss1",
4901 "msiof0_ss2",
4902 "msiof0_txd",
4903 "msiof0_rxd",
4904};
4905
4906static const char * const msiof1_groups[] = {
4907 "msiof1_clk_a",
4908 "msiof1_sync_a",
4909 "msiof1_ss1_a",
4910 "msiof1_ss2_a",
4911 "msiof1_txd_a",
4912 "msiof1_rxd_a",
4913 "msiof1_clk_b",
4914 "msiof1_sync_b",
4915 "msiof1_ss1_b",
4916 "msiof1_ss2_b",
4917 "msiof1_txd_b",
4918 "msiof1_rxd_b",
4919 "msiof1_clk_c",
4920 "msiof1_sync_c",
4921 "msiof1_ss1_c",
4922 "msiof1_ss2_c",
4923 "msiof1_txd_c",
4924 "msiof1_rxd_c",
4925 "msiof1_clk_d",
4926 "msiof1_sync_d",
4927 "msiof1_ss1_d",
4928 "msiof1_ss2_d",
4929 "msiof1_txd_d",
4930 "msiof1_rxd_d",
4931 "msiof1_clk_e",
4932 "msiof1_sync_e",
4933 "msiof1_ss1_e",
4934 "msiof1_ss2_e",
4935 "msiof1_txd_e",
4936 "msiof1_rxd_e",
4937 "msiof1_clk_f",
4938 "msiof1_sync_f",
4939 "msiof1_ss1_f",
4940 "msiof1_ss2_f",
4941 "msiof1_txd_f",
4942 "msiof1_rxd_f",
4943 "msiof1_clk_g",
4944 "msiof1_sync_g",
4945 "msiof1_ss1_g",
4946 "msiof1_ss2_g",
4947 "msiof1_txd_g",
4948 "msiof1_rxd_g",
4949};
4950
4951static const char * const msiof2_groups[] = {
4952 "msiof2_clk_a",
4953 "msiof2_sync_a",
4954 "msiof2_ss1_a",
4955 "msiof2_ss2_a",
4956 "msiof2_txd_a",
4957 "msiof2_rxd_a",
4958 "msiof2_clk_b",
4959 "msiof2_sync_b",
4960 "msiof2_ss1_b",
4961 "msiof2_ss2_b",
4962 "msiof2_txd_b",
4963 "msiof2_rxd_b",
4964 "msiof2_clk_c",
4965 "msiof2_sync_c",
4966 "msiof2_ss1_c",
4967 "msiof2_ss2_c",
4968 "msiof2_txd_c",
4969 "msiof2_rxd_c",
4970 "msiof2_clk_d",
4971 "msiof2_sync_d",
4972 "msiof2_ss1_d",
4973 "msiof2_ss2_d",
4974 "msiof2_txd_d",
4975 "msiof2_rxd_d",
4976};
4977
4978static const char * const msiof3_groups[] = {
4979 "msiof3_clk_a",
4980 "msiof3_sync_a",
4981 "msiof3_ss1_a",
4982 "msiof3_ss2_a",
4983 "msiof3_txd_a",
4984 "msiof3_rxd_a",
4985 "msiof3_clk_b",
4986 "msiof3_sync_b",
4987 "msiof3_ss1_b",
4988 "msiof3_ss2_b",
4989 "msiof3_txd_b",
4990 "msiof3_rxd_b",
4991 "msiof3_clk_c",
4992 "msiof3_sync_c",
4993 "msiof3_txd_c",
4994 "msiof3_rxd_c",
4995 "msiof3_clk_d",
4996 "msiof3_sync_d",
4997 "msiof3_ss1_d",
4998 "msiof3_txd_d",
4999 "msiof3_rxd_d",
5000 "msiof3_clk_e",
5001 "msiof3_sync_e",
5002 "msiof3_ss1_e",
5003 "msiof3_ss2_e",
5004 "msiof3_txd_e",
5005 "msiof3_rxd_e",
5006};
5007
5008static const char * const pwm0_groups[] = {
5009 "pwm0",
5010};
5011
5012static const char * const pwm1_groups[] = {
5013 "pwm1_a",
5014 "pwm1_b",
5015};
5016
5017static const char * const pwm2_groups[] = {
5018 "pwm2_a",
5019 "pwm2_b",
5020};
5021
5022static const char * const pwm3_groups[] = {
5023 "pwm3_a",
5024 "pwm3_b",
5025};
5026
5027static const char * const pwm4_groups[] = {
5028 "pwm4_a",
5029 "pwm4_b",
5030};
5031
5032static const char * const pwm5_groups[] = {
5033 "pwm5_a",
5034 "pwm5_b",
5035};
5036
5037static const char * const pwm6_groups[] = {
5038 "pwm6_a",
5039 "pwm6_b",
5040};
5041
5042static const char * const sata0_groups[] = {
5043 "sata0_devslp_a",
5044 "sata0_devslp_b",
5045};
5046
5047static const char * const scif0_groups[] = {
5048 "scif0_data",
5049 "scif0_clk",
5050 "scif0_ctrl",
5051};
5052
5053static const char * const scif1_groups[] = {
5054 "scif1_data_a",
5055 "scif1_clk",
5056 "scif1_ctrl",
5057 "scif1_data_b",
5058};
5059static const char * const scif2_groups[] = {
5060 "scif2_data_a",
5061 "scif2_clk",
5062 "scif2_data_b",
5063};
5064
5065static const char * const scif3_groups[] = {
5066 "scif3_data_a",
5067 "scif3_clk",
5068 "scif3_ctrl",
5069 "scif3_data_b",
5070};
5071
5072static const char * const scif4_groups[] = {
5073 "scif4_data_a",
5074 "scif4_clk_a",
5075 "scif4_ctrl_a",
5076 "scif4_data_b",
5077 "scif4_clk_b",
5078 "scif4_ctrl_b",
5079 "scif4_data_c",
5080 "scif4_clk_c",
5081 "scif4_ctrl_c",
5082};
5083
5084static const char * const scif5_groups[] = {
5085 "scif5_data_a",
5086 "scif5_clk_a",
5087 "scif5_data_b",
5088 "scif5_clk_b",
5089};
5090
5091static const char * const scif_clk_groups[] = {
5092 "scif_clk_a",
5093 "scif_clk_b",
5094};
5095
5096static const char * const sdhi0_groups[] = {
5097 "sdhi0_data1",
5098 "sdhi0_data4",
5099 "sdhi0_ctrl",
5100 "sdhi0_cd",
5101 "sdhi0_wp",
5102};
5103
5104static const char * const sdhi1_groups[] = {
5105 "sdhi1_data1",
5106 "sdhi1_data4",
5107 "sdhi1_ctrl",
5108 "sdhi1_cd",
5109 "sdhi1_wp",
5110};
5111
5112static const char * const sdhi2_groups[] = {
5113 "sdhi2_data1",
5114 "sdhi2_data4",
5115 "sdhi2_data8",
5116 "sdhi2_ctrl",
5117 "sdhi2_cd_a",
5118 "sdhi2_wp_a",
5119 "sdhi2_cd_b",
5120 "sdhi2_wp_b",
5121 "sdhi2_ds",
5122};
5123
5124static const char * const sdhi3_groups[] = {
5125 "sdhi3_data1",
5126 "sdhi3_data4",
5127 "sdhi3_data8",
5128 "sdhi3_ctrl",
5129 "sdhi3_cd",
5130 "sdhi3_wp",
5131 "sdhi3_ds",
5132};
5133
5134static const char * const ssi_groups[] = {
5135 "ssi0_data",
5136 "ssi01239_ctrl",
5137 "ssi1_data_a",
5138 "ssi1_data_b",
5139 "ssi1_ctrl_a",
5140 "ssi1_ctrl_b",
5141 "ssi2_data_a",
5142 "ssi2_data_b",
5143 "ssi2_ctrl_a",
5144 "ssi2_ctrl_b",
5145 "ssi3_data",
5146 "ssi349_ctrl",
5147 "ssi4_data",
5148 "ssi4_ctrl",
5149 "ssi5_data",
5150 "ssi5_ctrl",
5151 "ssi6_data",
5152 "ssi6_ctrl",
5153 "ssi7_data",
5154 "ssi78_ctrl",
5155 "ssi8_data",
5156 "ssi9_data_a",
5157 "ssi9_data_b",
5158 "ssi9_ctrl_a",
5159 "ssi9_ctrl_b",
5160};
5161
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]5162static const char * const tmu_groups[] = {
5163 "tmu_tclk1_a",
5164 "tmu_tclk1_b",
5165 "tmu_tclk2_a",
5166 "tmu_tclk2_b",
5167};
5168
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5169static const char * const usb0_groups[] = {
5170 "usb0",
5171};
5172
5173static const char * const usb1_groups[] = {
5174 "usb1",
5175};
5176
5177static const char * const usb30_groups[] = {
5178 "usb30",
5179};
5180
5181static const char * const vin4_groups[] = {
5182 "vin4_data8_a",
5183 "vin4_data10_a",
5184 "vin4_data12_a",
5185 "vin4_data16_a",
5186 "vin4_data18_a",
5187 "vin4_data20_a",
5188 "vin4_data24_a",
5189 "vin4_data8_b",
5190 "vin4_data10_b",
5191 "vin4_data12_b",
5192 "vin4_data16_b",
5193 "vin4_data18_b",
5194 "vin4_data20_b",
5195 "vin4_data24_b",
5196 "vin4_sync",
5197 "vin4_field",
5198 "vin4_clkenb",
5199 "vin4_clk",
5200};
5201
5202static const char * const vin5_groups[] = {
5203 "vin5_data8",
5204 "vin5_data10",
5205 "vin5_data12",
5206 "vin5_data16",
5207 "vin5_sync",
5208 "vin5_field",
5209 "vin5_clkenb",
5210 "vin5_clk",
5211};
5212
5213static const struct sh_pfc_function pinmux_functions[] = {
5214 SH_PFC_FUNCTION(audio_clk),
5215 SH_PFC_FUNCTION(avb),
5216 SH_PFC_FUNCTION(can0),
5217 SH_PFC_FUNCTION(can1),
5218 SH_PFC_FUNCTION(can_clk),
5219 SH_PFC_FUNCTION(canfd0),
5220 SH_PFC_FUNCTION(canfd1),
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]5221 SH_PFC_FUNCTION(drif0),
5222 SH_PFC_FUNCTION(drif1),
5223 SH_PFC_FUNCTION(drif2),
5224 SH_PFC_FUNCTION(drif3),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5225 SH_PFC_FUNCTION(du),
5226 SH_PFC_FUNCTION(hscif0),
5227 SH_PFC_FUNCTION(hscif1),
5228 SH_PFC_FUNCTION(hscif2),
5229 SH_PFC_FUNCTION(hscif3),
5230 SH_PFC_FUNCTION(hscif4),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5231 SH_PFC_FUNCTION(i2c0),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5232 SH_PFC_FUNCTION(i2c1),
5233 SH_PFC_FUNCTION(i2c2),
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5234 SH_PFC_FUNCTION(i2c3),
5235 SH_PFC_FUNCTION(i2c5),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5236 SH_PFC_FUNCTION(i2c6),
5237 SH_PFC_FUNCTION(intc_ex),
5238 SH_PFC_FUNCTION(msiof0),
5239 SH_PFC_FUNCTION(msiof1),
5240 SH_PFC_FUNCTION(msiof2),
5241 SH_PFC_FUNCTION(msiof3),
5242 SH_PFC_FUNCTION(pwm0),
5243 SH_PFC_FUNCTION(pwm1),
5244 SH_PFC_FUNCTION(pwm2),
5245 SH_PFC_FUNCTION(pwm3),
5246 SH_PFC_FUNCTION(pwm4),
5247 SH_PFC_FUNCTION(pwm5),
5248 SH_PFC_FUNCTION(pwm6),
5249 SH_PFC_FUNCTION(sata0),
5250 SH_PFC_FUNCTION(scif0),
5251 SH_PFC_FUNCTION(scif1),
5252 SH_PFC_FUNCTION(scif2),
5253 SH_PFC_FUNCTION(scif3),
5254 SH_PFC_FUNCTION(scif4),
5255 SH_PFC_FUNCTION(scif5),
5256 SH_PFC_FUNCTION(scif_clk),
5257 SH_PFC_FUNCTION(sdhi0),
5258 SH_PFC_FUNCTION(sdhi1),
5259 SH_PFC_FUNCTION(sdhi2),
5260 SH_PFC_FUNCTION(sdhi3),
5261 SH_PFC_FUNCTION(ssi),
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]5262 SH_PFC_FUNCTION(tmu),
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5263 SH_PFC_FUNCTION(usb0),
5264 SH_PFC_FUNCTION(usb1),
5265 SH_PFC_FUNCTION(usb30),
5266 SH_PFC_FUNCTION(vin4),
5267 SH_PFC_FUNCTION(vin5),
5268};
5269
5270static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5271#define F_(x, y) FN_##y
5272#define FM(x) FN_##x
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5273 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5274 0, 0,
5275 0, 0,
5276 0, 0,
5277 0, 0,
5278 0, 0,
5279 0, 0,
5280 0, 0,
5281 0, 0,
5282 0, 0,
5283 0, 0,
5284 0, 0,
5285 0, 0,
5286 0, 0,
5287 0, 0,
5288 0, 0,
5289 0, 0,
5290 GP_0_15_FN, GPSR0_15,
5291 GP_0_14_FN, GPSR0_14,
5292 GP_0_13_FN, GPSR0_13,
5293 GP_0_12_FN, GPSR0_12,
5294 GP_0_11_FN, GPSR0_11,
5295 GP_0_10_FN, GPSR0_10,
5296 GP_0_9_FN, GPSR0_9,
5297 GP_0_8_FN, GPSR0_8,
5298 GP_0_7_FN, GPSR0_7,
5299 GP_0_6_FN, GPSR0_6,
5300 GP_0_5_FN, GPSR0_5,
5301 GP_0_4_FN, GPSR0_4,
5302 GP_0_3_FN, GPSR0_3,
5303 GP_0_2_FN, GPSR0_2,
5304 GP_0_1_FN, GPSR0_1,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5305 GP_0_0_FN, GPSR0_0, ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5306 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5307 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5308 0, 0,
5309 0, 0,
5310 0, 0,
5311 GP_1_28_FN, GPSR1_28,
5312 GP_1_27_FN, GPSR1_27,
5313 GP_1_26_FN, GPSR1_26,
5314 GP_1_25_FN, GPSR1_25,
5315 GP_1_24_FN, GPSR1_24,
5316 GP_1_23_FN, GPSR1_23,
5317 GP_1_22_FN, GPSR1_22,
5318 GP_1_21_FN, GPSR1_21,
5319 GP_1_20_FN, GPSR1_20,
5320 GP_1_19_FN, GPSR1_19,
5321 GP_1_18_FN, GPSR1_18,
5322 GP_1_17_FN, GPSR1_17,
5323 GP_1_16_FN, GPSR1_16,
5324 GP_1_15_FN, GPSR1_15,
5325 GP_1_14_FN, GPSR1_14,
5326 GP_1_13_FN, GPSR1_13,
5327 GP_1_12_FN, GPSR1_12,
5328 GP_1_11_FN, GPSR1_11,
5329 GP_1_10_FN, GPSR1_10,
5330 GP_1_9_FN, GPSR1_9,
5331 GP_1_8_FN, GPSR1_8,
5332 GP_1_7_FN, GPSR1_7,
5333 GP_1_6_FN, GPSR1_6,
5334 GP_1_5_FN, GPSR1_5,
5335 GP_1_4_FN, GPSR1_4,
5336 GP_1_3_FN, GPSR1_3,
5337 GP_1_2_FN, GPSR1_2,
5338 GP_1_1_FN, GPSR1_1,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5339 GP_1_0_FN, GPSR1_0, ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5340 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5341 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5342 0, 0,
5343 0, 0,
5344 0, 0,
5345 0, 0,
5346 0, 0,
5347 0, 0,
5348 0, 0,
5349 0, 0,
5350 0, 0,
5351 0, 0,
5352 0, 0,
5353 0, 0,
5354 0, 0,
5355 0, 0,
5356 0, 0,
5357 0, 0,
5358 0, 0,
5359 GP_2_14_FN, GPSR2_14,
5360 GP_2_13_FN, GPSR2_13,
5361 GP_2_12_FN, GPSR2_12,
5362 GP_2_11_FN, GPSR2_11,
5363 GP_2_10_FN, GPSR2_10,
5364 GP_2_9_FN, GPSR2_9,
5365 GP_2_8_FN, GPSR2_8,
5366 GP_2_7_FN, GPSR2_7,
5367 GP_2_6_FN, GPSR2_6,
5368 GP_2_5_FN, GPSR2_5,
5369 GP_2_4_FN, GPSR2_4,
5370 GP_2_3_FN, GPSR2_3,
5371 GP_2_2_FN, GPSR2_2,
5372 GP_2_1_FN, GPSR2_1,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5373 GP_2_0_FN, GPSR2_0, ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5374 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5375 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5376 0, 0,
5377 0, 0,
5378 0, 0,
5379 0, 0,
5380 0, 0,
5381 0, 0,
5382 0, 0,
5383 0, 0,
5384 0, 0,
5385 0, 0,
5386 0, 0,
5387 0, 0,
5388 0, 0,
5389 0, 0,
5390 0, 0,
5391 0, 0,
5392 GP_3_15_FN, GPSR3_15,
5393 GP_3_14_FN, GPSR3_14,
5394 GP_3_13_FN, GPSR3_13,
5395 GP_3_12_FN, GPSR3_12,
5396 GP_3_11_FN, GPSR3_11,
5397 GP_3_10_FN, GPSR3_10,
5398 GP_3_9_FN, GPSR3_9,
5399 GP_3_8_FN, GPSR3_8,
5400 GP_3_7_FN, GPSR3_7,
5401 GP_3_6_FN, GPSR3_6,
5402 GP_3_5_FN, GPSR3_5,
5403 GP_3_4_FN, GPSR3_4,
5404 GP_3_3_FN, GPSR3_3,
5405 GP_3_2_FN, GPSR3_2,
5406 GP_3_1_FN, GPSR3_1,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5407 GP_3_0_FN, GPSR3_0, ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5408 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5409 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5410 0, 0,
5411 0, 0,
5412 0, 0,
5413 0, 0,
5414 0, 0,
5415 0, 0,
5416 0, 0,
5417 0, 0,
5418 0, 0,
5419 0, 0,
5420 0, 0,
5421 0, 0,
5422 0, 0,
5423 0, 0,
5424 GP_4_17_FN, GPSR4_17,
5425 GP_4_16_FN, GPSR4_16,
5426 GP_4_15_FN, GPSR4_15,
5427 GP_4_14_FN, GPSR4_14,
5428 GP_4_13_FN, GPSR4_13,
5429 GP_4_12_FN, GPSR4_12,
5430 GP_4_11_FN, GPSR4_11,
5431 GP_4_10_FN, GPSR4_10,
5432 GP_4_9_FN, GPSR4_9,
5433 GP_4_8_FN, GPSR4_8,
5434 GP_4_7_FN, GPSR4_7,
5435 GP_4_6_FN, GPSR4_6,
5436 GP_4_5_FN, GPSR4_5,
5437 GP_4_4_FN, GPSR4_4,
5438 GP_4_3_FN, GPSR4_3,
5439 GP_4_2_FN, GPSR4_2,
5440 GP_4_1_FN, GPSR4_1,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5441 GP_4_0_FN, GPSR4_0, ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5442 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5443 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5444 0, 0,
5445 0, 0,
5446 0, 0,
5447 0, 0,
5448 0, 0,
5449 0, 0,
5450 GP_5_25_FN, GPSR5_25,
5451 GP_5_24_FN, GPSR5_24,
5452 GP_5_23_FN, GPSR5_23,
5453 GP_5_22_FN, GPSR5_22,
5454 GP_5_21_FN, GPSR5_21,
5455 GP_5_20_FN, GPSR5_20,
5456 GP_5_19_FN, GPSR5_19,
5457 GP_5_18_FN, GPSR5_18,
5458 GP_5_17_FN, GPSR5_17,
5459 GP_5_16_FN, GPSR5_16,
5460 GP_5_15_FN, GPSR5_15,
5461 GP_5_14_FN, GPSR5_14,
5462 GP_5_13_FN, GPSR5_13,
5463 GP_5_12_FN, GPSR5_12,
5464 GP_5_11_FN, GPSR5_11,
5465 GP_5_10_FN, GPSR5_10,
5466 GP_5_9_FN, GPSR5_9,
5467 GP_5_8_FN, GPSR5_8,
5468 GP_5_7_FN, GPSR5_7,
5469 GP_5_6_FN, GPSR5_6,
5470 GP_5_5_FN, GPSR5_5,
5471 GP_5_4_FN, GPSR5_4,
5472 GP_5_3_FN, GPSR5_3,
5473 GP_5_2_FN, GPSR5_2,
5474 GP_5_1_FN, GPSR5_1,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5475 GP_5_0_FN, GPSR5_0, ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5476 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5477 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5478 GP_6_31_FN, GPSR6_31,
5479 GP_6_30_FN, GPSR6_30,
5480 GP_6_29_FN, GPSR6_29,
5481 GP_6_28_FN, GPSR6_28,
5482 GP_6_27_FN, GPSR6_27,
5483 GP_6_26_FN, GPSR6_26,
5484 GP_6_25_FN, GPSR6_25,
5485 GP_6_24_FN, GPSR6_24,
5486 GP_6_23_FN, GPSR6_23,
5487 GP_6_22_FN, GPSR6_22,
5488 GP_6_21_FN, GPSR6_21,
5489 GP_6_20_FN, GPSR6_20,
5490 GP_6_19_FN, GPSR6_19,
5491 GP_6_18_FN, GPSR6_18,
5492 GP_6_17_FN, GPSR6_17,
5493 GP_6_16_FN, GPSR6_16,
5494 GP_6_15_FN, GPSR6_15,
5495 GP_6_14_FN, GPSR6_14,
5496 GP_6_13_FN, GPSR6_13,
5497 GP_6_12_FN, GPSR6_12,
5498 GP_6_11_FN, GPSR6_11,
5499 GP_6_10_FN, GPSR6_10,
5500 GP_6_9_FN, GPSR6_9,
5501 GP_6_8_FN, GPSR6_8,
5502 GP_6_7_FN, GPSR6_7,
5503 GP_6_6_FN, GPSR6_6,
5504 GP_6_5_FN, GPSR6_5,
5505 GP_6_4_FN, GPSR6_4,
5506 GP_6_3_FN, GPSR6_3,
5507 GP_6_2_FN, GPSR6_2,
5508 GP_6_1_FN, GPSR6_1,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5509 GP_6_0_FN, GPSR6_0, ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5510 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5511 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5512 0, 0,
5513 0, 0,
5514 0, 0,
5515 0, 0,
5516 0, 0,
5517 0, 0,
5518 0, 0,
5519 0, 0,
5520 0, 0,
5521 0, 0,
5522 0, 0,
5523 0, 0,
5524 0, 0,
5525 0, 0,
5526 0, 0,
5527 0, 0,
5528 0, 0,
5529 0, 0,
5530 0, 0,
5531 0, 0,
5532 0, 0,
5533 0, 0,
5534 0, 0,
5535 0, 0,
5536 0, 0,
5537 0, 0,
5538 0, 0,
5539 0, 0,
5540 GP_7_3_FN, GPSR7_3,
5541 GP_7_2_FN, GPSR7_2,
5542 GP_7_1_FN, GPSR7_1,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5543 GP_7_0_FN, GPSR7_0, ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5544 },
5545#undef F_
5546#undef FM
5547
5548#define F_(x, y) x,
5549#define FM(x) FN_##x,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5550 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5551 IP0_31_28
5552 IP0_27_24
5553 IP0_23_20
5554 IP0_19_16
5555 IP0_15_12
5556 IP0_11_8
5557 IP0_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5558 IP0_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5559 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5560 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5561 IP1_31_28
5562 IP1_27_24
5563 IP1_23_20
5564 IP1_19_16
5565 IP1_15_12
5566 IP1_11_8
5567 IP1_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5568 IP1_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5569 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5570 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5571 IP2_31_28
5572 IP2_27_24
5573 IP2_23_20
5574 IP2_19_16
5575 IP2_15_12
5576 IP2_11_8
5577 IP2_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5578 IP2_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5579 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5580 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5581 IP3_31_28
5582 IP3_27_24
5583 IP3_23_20
5584 IP3_19_16
5585 IP3_15_12
5586 IP3_11_8
5587 IP3_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5588 IP3_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5589 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5590 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5591 IP4_31_28
5592 IP4_27_24
5593 IP4_23_20
5594 IP4_19_16
5595 IP4_15_12
5596 IP4_11_8
5597 IP4_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5598 IP4_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5599 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5600 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5601 IP5_31_28
5602 IP5_27_24
5603 IP5_23_20
5604 IP5_19_16
5605 IP5_15_12
5606 IP5_11_8
5607 IP5_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5608 IP5_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5609 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5610 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5611 IP6_31_28
5612 IP6_27_24
5613 IP6_23_20
5614 IP6_19_16
5615 IP6_15_12
5616 IP6_11_8
5617 IP6_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5618 IP6_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5619 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5620 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5621 IP7_31_28
5622 IP7_27_24
5623 IP7_23_20
5624 IP7_19_16
5625 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5626 IP7_11_8
5627 IP7_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5628 IP7_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5629 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5630 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5631 IP8_31_28
5632 IP8_27_24
5633 IP8_23_20
5634 IP8_19_16
5635 IP8_15_12
5636 IP8_11_8
5637 IP8_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5638 IP8_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5639 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5640 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5641 IP9_31_28
5642 IP9_27_24
5643 IP9_23_20
5644 IP9_19_16
5645 IP9_15_12
5646 IP9_11_8
5647 IP9_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5648 IP9_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5649 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5650 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5651 IP10_31_28
5652 IP10_27_24
5653 IP10_23_20
5654 IP10_19_16
5655 IP10_15_12
5656 IP10_11_8
5657 IP10_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5658 IP10_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5659 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5660 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5661 IP11_31_28
5662 IP11_27_24
5663 IP11_23_20
5664 IP11_19_16
5665 IP11_15_12
5666 IP11_11_8
5667 IP11_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5668 IP11_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5669 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5670 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5671 IP12_31_28
5672 IP12_27_24
5673 IP12_23_20
5674 IP12_19_16
5675 IP12_15_12
5676 IP12_11_8
5677 IP12_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5678 IP12_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5679 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5680 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5681 IP13_31_28
5682 IP13_27_24
5683 IP13_23_20
5684 IP13_19_16
5685 IP13_15_12
5686 IP13_11_8
5687 IP13_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5688 IP13_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5689 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5690 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5691 IP14_31_28
5692 IP14_27_24
5693 IP14_23_20
5694 IP14_19_16
5695 IP14_15_12
5696 IP14_11_8
5697 IP14_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5698 IP14_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5699 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5700 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5701 IP15_31_28
5702 IP15_27_24
5703 IP15_23_20
5704 IP15_19_16
5705 IP15_15_12
5706 IP15_11_8
5707 IP15_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5708 IP15_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5709 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5710 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5711 IP16_31_28
5712 IP16_27_24
5713 IP16_23_20
5714 IP16_19_16
5715 IP16_15_12
5716 IP16_11_8
5717 IP16_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5718 IP16_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5719 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5720 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5721 IP17_31_28
5722 IP17_27_24
5723 IP17_23_20
5724 IP17_19_16
5725 IP17_15_12
5726 IP17_11_8
5727 IP17_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5728 IP17_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5729 },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5730 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5731 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5732 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5733 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5734 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5735 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5736 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5737 IP18_7_4
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5738 IP18_3_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5739 },
5740#undef F_
5741#undef FM
5742
5743#define F_(x, y) x,
5744#define FM(x) FN_##x,
5745 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5746 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5747 1, 1, 1, 2, 2, 1, 2, 3),
5748 GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5749 MOD_SEL0_31_30_29
5750 MOD_SEL0_28_27
5751 MOD_SEL0_26_25_24
5752 MOD_SEL0_23
5753 MOD_SEL0_22
5754 MOD_SEL0_21
5755 MOD_SEL0_20
5756 MOD_SEL0_19
5757 MOD_SEL0_18_17
5758 MOD_SEL0_16
5759 0, 0, /* RESERVED 15 */
5760 MOD_SEL0_14_13
5761 MOD_SEL0_12
5762 MOD_SEL0_11
5763 MOD_SEL0_10
5764 MOD_SEL0_9_8
5765 MOD_SEL0_7_6
5766 MOD_SEL0_5
5767 MOD_SEL0_4_3
5768 /* RESERVED 2, 1, 0 */
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5769 0, 0, 0, 0, 0, 0, 0, 0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5770 },
5771 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5772 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5773 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5774 GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5775 MOD_SEL1_31_30
5776 MOD_SEL1_29_28_27
5777 MOD_SEL1_26
5778 MOD_SEL1_25_24
5779 MOD_SEL1_23_22_21
5780 MOD_SEL1_20
5781 MOD_SEL1_19
5782 MOD_SEL1_18_17
5783 MOD_SEL1_16
5784 MOD_SEL1_15_14
5785 MOD_SEL1_13
5786 MOD_SEL1_12
5787 MOD_SEL1_11
5788 MOD_SEL1_10
5789 MOD_SEL1_9
5790 0, 0, 0, 0, /* RESERVED 8, 7 */
5791 MOD_SEL1_6
5792 MOD_SEL1_5
5793 MOD_SEL1_4
5794 MOD_SEL1_3
5795 MOD_SEL1_2
5796 MOD_SEL1_1
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5797 MOD_SEL1_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5798 },
5799 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5800 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5801 1, 4, 4, 4, 3, 1),
5802 GROUP(
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5803 MOD_SEL2_31
5804 MOD_SEL2_30
5805 MOD_SEL2_29
5806 MOD_SEL2_28_27
5807 MOD_SEL2_26
5808 MOD_SEL2_25_24_23
5809 MOD_SEL2_22
5810 MOD_SEL2_21
5811 MOD_SEL2_20
5812 MOD_SEL2_19
5813 MOD_SEL2_18
5814 MOD_SEL2_17
5815 /* RESERVED 16 */
5816 0, 0,
5817 /* RESERVED 15, 14, 13, 12 */
5818 0, 0, 0, 0, 0, 0, 0, 0,
5819 0, 0, 0, 0, 0, 0, 0, 0,
5820 /* RESERVED 11, 10, 9, 8 */
5821 0, 0, 0, 0, 0, 0, 0, 0,
5822 0, 0, 0, 0, 0, 0, 0, 0,
5823 /* RESERVED 7, 6, 5, 4 */
5824 0, 0, 0, 0, 0, 0, 0, 0,
5825 0, 0, 0, 0, 0, 0, 0, 0,
5826 /* RESERVED 3, 2, 1 */
5827 0, 0, 0, 0, 0, 0, 0, 0,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5828 MOD_SEL2_0 ))
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5829 },
5830 { },
5831};
5832
5833static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5834 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5835 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5836 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5837 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5838 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5839 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5840 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5841 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5842 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5843 } },
5844 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5845 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5846 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5847 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5848 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5849 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5850 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5851 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5852 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5853 } },
5854 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5855 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5856 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5857 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5858 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5859 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5860 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5861 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5862 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5863 } },
5864 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5865 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5866 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5867 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5868 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5869 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5870 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5871 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5872 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5873 } },
5874 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5875 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5876 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5877 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5878 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5879 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5880 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5881 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5882 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5883 } },
5884 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5885 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5886 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5887 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5888 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5889 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5890 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5891 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5892 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5893 } },
5894 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5895 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5896 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5897 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5898 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5899 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5900 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5901 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5902 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5903 } },
5904 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5905 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5906 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5907 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5908 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5909 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5910 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5911 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5912 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5913 } },
5914 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5915 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5916 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5917 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5918 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5919 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5920 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5921 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5922 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5923 } },
5924 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5925 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5926 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5927 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5928 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5929 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5930 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5931 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5932 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5933 } },
5934 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5935 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5936 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5937 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5938 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5939 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5940 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5941 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5942 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5943 } },
5944 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5945 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5946 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5947 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5948 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]5949 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]5950 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5951 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5952 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5953 } },
5954 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5955 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
5956 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5957 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5958 } },
5959 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5960 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5961 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5962 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5963 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5964 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5965 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5966 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5967 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5968 } },
5969 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5970 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5971 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5972 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5973 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5974 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5975 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5976 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5977 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5978 } },
5979 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5980 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5981 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5982 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5983 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5984 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5985 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5986 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5987 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5988 } },
5989 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5990 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5991 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5992 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5993 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5994 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5995 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5996 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5997 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5998 } },
5999 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
6000 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
6001 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
6002 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
6003 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
6004 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
6005 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
6006 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
6007 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
6008 } },
6009 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
6010 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
6011 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
6012 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
6013 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
6014 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
6015 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
6016 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
6017 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
6018 } },
6019 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
6020 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
6021 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
6022 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
6023 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
6024 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
6025 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
6026 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
6027 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
6028 } },
6029 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6030 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
6031 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
6032 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
6033 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
6034 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
6035 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
6036 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
6037 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
6038 } },
6039 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6040 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
6041 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
6042 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
6043 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
6044 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
6045 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
6046 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
6047 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
6048 } },
6049 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6050 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
6051 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
6052 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
6053 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
6054 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
6055 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
6056 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
6057 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
6058 } },
6059 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6060 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
6061 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
6062 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
6063 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
6064 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
6065 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
6066 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
6067 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
6068 } },
6069 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6070 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
6071 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
6072 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
6073 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
6074 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
6075 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
6076 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
6077 } },
6078 { },
6079};
6080
6081enum ioctrl_regs {
6082 POCCTRL,
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]6083 TDSELCTRL,
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]6084};
6085
6086static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6087 [POCCTRL] = { 0xe6060380, },
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]6088 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]6089 { /* sentinel */ },
6090};
6091
6092static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6093{
6094 int bit = -EINVAL;
6095
6096 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6097
6098 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6099 bit = pin & 0x1f;
6100
6101 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6102 bit = (pin & 0x1f) + 12;
6103
6104 return bit;
6105}
6106
6107static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6108 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6109 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
6110 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
6111 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
6112 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
6113 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
6114 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
6115 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
6116 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
6117 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
6118 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
6119 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
6120 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
6121 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
6122 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
6123 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
6124 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
6125 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
6126 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
6127 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
6128 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
6129 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
6130 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
6131 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
6132 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
6133 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
6134 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
6135 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
6136 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
6137 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
6138 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6139 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6140 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6141 } },
6142 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6143 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6144 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6145 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6146 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6147 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6148 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6149 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6150 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6151 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6152 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6153 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6154 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6155 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6156 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6157 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6158 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6159 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6160 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6161 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6162 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6163 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6164 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6165 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6166 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6167 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6168 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6169 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6170 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6171 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6172 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6173 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6174 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6175 } },
6176 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6177 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6178 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6179 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6180 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6181 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6182 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6183 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6184 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6185 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6186 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
6187 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6188 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6189 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6190 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6191 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6192 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6193 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6194 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6195 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6196 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6197 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6198 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6199 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6200 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6201 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6202 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6203 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6204 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Rosca7f2e60f2019-07-09 18:27:11 +0200[diff] [blame^]6205 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]6206 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6207 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6208 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6209 } },
6210 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut8719ca82019-03-04 22:39:51 +0100[diff] [blame]6211 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
Marek Vasutc6435c32019-03-04 01:32:44 +0100[diff] [blame]6212 [ 1] = PIN_NONE,
6213 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
6214 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6215 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6216 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6217 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6218 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6219 [ 8] = PIN_NONE,
6220 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6221 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6222 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6223 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6224 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6225 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6226 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6227 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6228 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6229 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6230 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6231 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6232 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6233 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6234 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6235 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6236 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6237 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6238 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6239 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6240 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6241 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6242 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6243 } },
6244 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6245 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6246 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6247 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6248 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6249 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6250 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6251 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6252 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6253 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6254 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6255 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6256 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6257 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6258 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6259 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6260 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6261 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6262 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6263 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6264 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6265 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6266 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6267 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6268 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6269 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6270 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6271 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6272 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6273 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6274 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6275 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6276 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6277 } },
6278 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6279 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6280 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6281 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6282 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6283 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6284 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6285 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6286 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6287 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6288 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6289 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6290 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6291 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6292 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6293 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6294 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6295 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6296 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6297 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6298 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6299 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6300 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6301 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6302 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6303 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6304 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6305 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6306 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6307 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6308 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6309 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6310 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6311 } },
6312 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6313 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6314 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6315 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6316 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6317 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6318 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6319 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6320 [ 7] = PIN_NONE,
6321 [ 8] = PIN_NONE,
6322 [ 9] = PIN_NONE,
6323 [10] = PIN_NONE,
6324 [11] = PIN_NONE,
6325 [12] = PIN_NONE,
6326 [13] = PIN_NONE,
6327 [14] = PIN_NONE,
6328 [15] = PIN_NONE,
6329 [16] = PIN_NONE,
6330 [17] = PIN_NONE,
6331 [18] = PIN_NONE,
6332 [19] = PIN_NONE,
6333 [20] = PIN_NONE,
6334 [21] = PIN_NONE,
6335 [22] = PIN_NONE,
6336 [23] = PIN_NONE,
6337 [24] = PIN_NONE,
6338 [25] = PIN_NONE,
6339 [26] = PIN_NONE,
6340 [27] = PIN_NONE,
6341 [28] = PIN_NONE,
6342 [29] = PIN_NONE,
6343 [30] = PIN_NONE,
6344 [31] = PIN_NONE,
6345 } },
6346 { /* sentinel */ },
6347};
6348
6349static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
6350 unsigned int pin)
6351{
6352 const struct pinmux_bias_reg *reg;
6353 unsigned int bit;
6354
6355 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6356 if (!reg)
6357 return PIN_CONFIG_BIAS_DISABLE;
6358
6359 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6360 return PIN_CONFIG_BIAS_DISABLE;
6361 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6362 return PIN_CONFIG_BIAS_PULL_UP;
6363 else
6364 return PIN_CONFIG_BIAS_PULL_DOWN;
6365}
6366
6367static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6368 unsigned int bias)
6369{
6370 const struct pinmux_bias_reg *reg;
6371 u32 enable, updown;
6372 unsigned int bit;
6373
6374 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6375 if (!reg)
6376 return;
6377
6378 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6379 if (bias != PIN_CONFIG_BIAS_DISABLE)
6380 enable |= BIT(bit);
6381
6382 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6383 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6384 updown |= BIT(bit);
6385
6386 sh_pfc_write(pfc, reg->pud, updown);
6387 sh_pfc_write(pfc, reg->puen, enable);
6388}
6389
6390static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6391 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6392 .get_bias = r8a77965_pinmux_get_bias,
6393 .set_bias = r8a77965_pinmux_set_bias,
6394};
6395
6396const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6397 .name = "r8a77965_pfc",
6398 .ops = &r8a77965_pinmux_ops,
6399 .unlock_reg = 0xe6060000, /* PMMR */
6400
6401 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6402
6403 .pins = pinmux_pins,
6404 .nr_pins = ARRAY_SIZE(pinmux_pins),
6405 .groups = pinmux_groups,
6406 .nr_groups = ARRAY_SIZE(pinmux_groups),
6407 .functions = pinmux_functions,
6408 .nr_functions = ARRAY_SIZE(pinmux_functions),
6409
6410 .cfg_regs = pinmux_config_regs,
6411 .drive_regs = pinmux_drive_regs,
6412 .bias_regs = pinmux_bias_regs,
6413 .ioctrl_regs = pinmux_ioctrl_regs,
6414
6415 .pinmux_data = pinmux_data,
6416 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6417};