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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk0ac6f8b2004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * PCI Configuration space access support for MPC85xx PCI Bridge
27 */
28#include <common.h>
29#include <asm/cpm_85xx.h>
30#include <pci.h>
31
Matthew McClintock7376eb82006-10-11 15:13:01 -050032#if defined(CONFIG_OF_FLAT_TREE)
33#include <ft_build.h>
34#endif
wdenk0ac6f8b2004-07-09 23:27:13 +000035
wdenk42d1f032003-10-15 23:53:47 +000036#if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +000037
Matthew McClintock08745462006-06-28 10:45:17 -050038static struct pci_controller *pci_hose;
39
wdenk9aea9532004-08-01 23:02:45 +000040void
Matthew McClintock08745462006-06-28 10:45:17 -050041pci_mpc85xx_init(struct pci_controller *board_hose)
wdenk42d1f032003-10-15 23:53:47 +000042{
Matthew McClintock08745462006-06-28 10:45:17 -050043 u16 reg16;
44 u32 dev;
45
wdenk9aea9532004-08-01 23:02:45 +000046 volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
wdenk0ac6f8b2004-07-09 23:27:13 +000047 volatile ccsr_pcix_t *pcix = &immap->im_pcix;
Matthew McClintock7376eb82006-10-11 15:13:01 -050048#ifdef CONFIG_MPC85XX_PCI2
Matthew McClintock08745462006-06-28 10:45:17 -050049 volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
Matthew McClintock7376eb82006-10-11 15:13:01 -050050#endif
Matthew McClintock08745462006-06-28 10:45:17 -050051 volatile ccsr_gur_t *gur = &immap->im_gur;
52 struct pci_controller * hose;
wdenk42d1f032003-10-15 23:53:47 +000053
Matthew McClintock08745462006-06-28 10:45:17 -050054 pci_hose = board_hose;
55
56 hose = &pci_hose[0];
wdenk42d1f032003-10-15 23:53:47 +000057
wdenk0ac6f8b2004-07-09 23:27:13 +000058 hose->first_busno = 0;
59 hose->last_busno = 0xff;
wdenk42d1f032003-10-15 23:53:47 +000060
Matthew McClintock08745462006-06-28 10:45:17 -050061 pci_setup_indirect(hose,
62 (CFG_IMMR+0x8000),
63 (CFG_IMMR+0x8004));
64
65 /*
66 * Hose scan.
67 */
68 dev = PCI_BDF(hose->first_busno, 0, 0);
69 pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
70 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
71 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
72
73 /*
74 * Clear non-reserved bits in status register.
75 */
76 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
77
78 if (!(gur->pordevsr & PORDEVSR_PCI)) {
79 /* PCI-X init */
Matthew McClintock38433cc2006-06-28 10:47:03 -050080 if (CONFIG_SYS_CLK_FREQ < 66000000)
81 printf("PCI-X will only work at 66 MHz\n");
82
Matthew McClintock08745462006-06-28 10:45:17 -050083 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
84 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
85 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
86 }
87
88 pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
89 pcix->potear1 = 0x00000000;
90 pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
91 pcix->powbear1 = 0x00000000;
92 pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
Andy Flemingffa621a2007-02-24 01:08:13 -060093 POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1));
Matthew McClintock08745462006-06-28 10:45:17 -050094
95 pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
96 pcix->potear2 = 0x00000000;
97 pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
98 pcix->powbear2 = 0x00000000;
99 pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
Andy Flemingffa621a2007-02-24 01:08:13 -0600100 POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1));
Matthew McClintock08745462006-06-28 10:45:17 -0500101
102 pcix->pitar1 = 0x00000000;
103 pcix->piwbar1 = 0x00000000;
104 pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
105 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
106
107 pcix->powar3 = 0;
108 pcix->powar4 = 0;
109 pcix->piwar2 = 0;
110 pcix->piwar3 = 0;
111
wdenk9aea9532004-08-01 23:02:45 +0000112 pci_set_region(hose->regions + 0,
113 CFG_PCI1_MEM_BASE,
114 CFG_PCI1_MEM_PHYS,
115 CFG_PCI1_MEM_SIZE,
116 PCI_REGION_MEM);
wdenk42d1f032003-10-15 23:53:47 +0000117
wdenk9aea9532004-08-01 23:02:45 +0000118 pci_set_region(hose->regions + 1,
119 CFG_PCI1_IO_BASE,
120 CFG_PCI1_IO_PHYS,
121 CFG_PCI1_IO_SIZE,
122 PCI_REGION_IO);
wdenk42d1f032003-10-15 23:53:47 +0000123
wdenk0ac6f8b2004-07-09 23:27:13 +0000124 hose->region_count = 2;
wdenk42d1f032003-10-15 23:53:47 +0000125
wdenk9aea9532004-08-01 23:02:45 +0000126 pci_register_hose(hose);
wdenkcf336782004-10-10 20:23:57 +0000127
128#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
129 /*
130 * This is a SW workaround for an apparent HW problem
131 * in the PCI controller on the MPC85555/41 CDS boards.
132 * The first config cycle must be to a valid, known
133 * device on the PCI bus in order to trick the PCI
134 * controller state machine into a known valid state.
135 * Without this, the first config cycle has the chance
136 * of hanging the controller permanently, just leaving
137 * it in a semi-working state, or leaving it working.
138 *
139 * Pick on the Tundra, Device 17, to get it right.
140 */
141 {
142 u8 header_type;
143
144 pci_hose_read_config_byte(hose,
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700145 PCI_BDF(0,BRIDGE_ID,0),
wdenkcf336782004-10-10 20:23:57 +0000146 PCI_HEADER_TYPE,
147 &header_type);
148 }
wdenkcf336782004-10-10 20:23:57 +0000149#endif
150
wdenk9aea9532004-08-01 23:02:45 +0000151 hose->last_busno = pci_hose_scan(hose);
Matthew McClintock08745462006-06-28 10:45:17 -0500152
153#ifdef CONFIG_MPC85XX_PCI2
154 hose = &pci_hose[1];
155
156 hose->first_busno = pci_hose[0].last_busno + 1;
157 hose->last_busno = 0xff;
158
159 pci_setup_indirect(hose,
160 (CFG_IMMR+0x9000),
161 (CFG_IMMR+0x9004));
162
163 dev = PCI_BDF(hose->first_busno, 0, 0);
164 pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
165 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
166 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
167
168 /*
169 * Clear non-reserved bits in status register.
170 */
171 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
172
173 pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
174 pcix2->potear1 = 0x00000000;
175 pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
176 pcix2->powbear1 = 0x00000000;
177 pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
Andy Flemingffa621a2007-02-24 01:08:13 -0600178 POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1));
Matthew McClintock08745462006-06-28 10:45:17 -0500179
180 pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
181 pcix2->potear2 = 0x00000000;
182 pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
183 pcix2->powbear2 = 0x00000000;
184 pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
Andy Flemingffa621a2007-02-24 01:08:13 -0600185 POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1));
Matthew McClintock08745462006-06-28 10:45:17 -0500186
187 pcix2->pitar1 = 0x00000000;
188 pcix2->piwbar1 = 0x00000000;
189 pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
190 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
191
192 pcix2->powar3 = 0;
193 pcix2->powar4 = 0;
194 pcix2->piwar2 = 0;
195 pcix2->piwar3 = 0;
196
197 pci_set_region(hose->regions + 0,
198 CFG_PCI2_MEM_BASE,
199 CFG_PCI2_MEM_PHYS,
200 CFG_PCI2_MEM_SIZE,
201 PCI_REGION_MEM);
202
203 pci_set_region(hose->regions + 1,
204 CFG_PCI2_IO_BASE,
205 CFG_PCI2_IO_PHYS,
206 CFG_PCI2_IO_SIZE,
207 PCI_REGION_IO);
208
209 hose->region_count = 2;
210
211 /*
212 * Hose scan.
213 */
214 pci_register_hose(hose);
215
216 hose->last_busno = pci_hose_scan(hose);
217#endif
wdenk42d1f032003-10-15 23:53:47 +0000218}
wdenk0ac6f8b2004-07-09 23:27:13 +0000219
Matthew McClintock08745462006-06-28 10:45:17 -0500220#ifdef CONFIG_OF_FLAT_TREE
221void
222ft_pci_setup(void *blob, bd_t *bd)
223{
224 u32 *p;
225 int len;
226
227 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
228 if (p != NULL) {
229 p[0] = pci_hose[0].first_busno;
230 p[1] = pci_hose[0].last_busno;
231 }
232
233#ifdef CONFIG_MPC85XX_PCI2
234 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
235 if (p != NULL) {
236 p[0] = pci_hose[1].first_busno;
237 p[1] = pci_hose[1].last_busno;
238 }
239#endif
240}
241#endif /* CONFIG_OF_FLAT_TREE */
wdenk42d1f032003-10-15 23:53:47 +0000242#endif /* CONFIG_PCI */