Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2011 The Chromium OS Authors. |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * The code in this file is based on the article "Writing a TPM Device Driver" |
| 8 | * published on http://ptgmedia.pearsoncmg.com. |
| 9 | * |
| 10 | * One principal difference is that in the simplest config the other than 0 |
| 11 | * TPM localities do not get mapped by some devices (for instance, by Infineon |
| 12 | * slb9635), so this driver provides access to locality 0 only. |
| 13 | */ |
| 14 | |
| 15 | #include <common.h> |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 16 | #include <dm.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 17 | #include <log.h> |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 18 | #include <mapmem.h> |
Miquel Raynal | d677bfe | 2018-05-15 11:57:06 +0200 | [diff] [blame] | 19 | #include <tpm-v1.h> |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 20 | #include <asm/io.h> |
Simon Glass | c05ed00 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 21 | #include <linux/delay.h> |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 22 | |
| 23 | #define PREFIX "lpc_tpm: " |
| 24 | |
George McCollister | a982b6f | 2016-10-17 09:24:32 -0500 | [diff] [blame] | 25 | enum i2c_chip_type { |
| 26 | SLB9635, |
| 27 | AT97SC3204, |
| 28 | }; |
| 29 | |
| 30 | static const char * const chip_name[] = { |
| 31 | [SLB9635] = "Infineon SLB9635 TT 1.2", |
| 32 | [AT97SC3204] = "Atmel AT97SC3204", |
| 33 | }; |
| 34 | |
| 35 | static const u32 chip_didvid[] = { |
| 36 | [SLB9635] = 0xb15d1, |
| 37 | [AT97SC3204] = 0x32041114, |
| 38 | }; |
| 39 | |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 40 | struct tpm_locality { |
| 41 | u32 access; |
| 42 | u8 padding0[4]; |
| 43 | u32 int_enable; |
| 44 | u8 vector; |
| 45 | u8 padding1[3]; |
| 46 | u32 int_status; |
| 47 | u32 int_capability; |
| 48 | u32 tpm_status; |
| 49 | u8 padding2[8]; |
| 50 | u8 data; |
| 51 | u8 padding3[3803]; |
| 52 | u32 did_vid; |
| 53 | u8 rid; |
| 54 | u8 padding4[251]; |
| 55 | }; |
| 56 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 57 | struct tpm_tis_lpc_priv { |
| 58 | struct tpm_locality *regs; |
| 59 | }; |
| 60 | |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 61 | /* |
| 62 | * This pointer refers to the TPM chip, 5 of its localities are mapped as an |
| 63 | * array. |
| 64 | */ |
| 65 | #define TPM_TOTAL_LOCALITIES 5 |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 66 | |
| 67 | /* Some registers' bit field definitions */ |
| 68 | #define TIS_STS_VALID (1 << 7) /* 0x80 */ |
| 69 | #define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ |
| 70 | #define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ |
| 71 | #define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ |
| 72 | #define TIS_STS_EXPECT (1 << 3) /* 0x08 */ |
| 73 | #define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */ |
| 74 | |
| 75 | #define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */ |
| 76 | #define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */ |
| 77 | #define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ |
| 78 | #define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ |
| 79 | #define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */ |
| 80 | #define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ |
| 81 | #define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */ |
| 82 | |
| 83 | #define TIS_STS_BURST_COUNT_MASK (0xffff) |
| 84 | #define TIS_STS_BURST_COUNT_SHIFT (8) |
| 85 | |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 86 | /* 1 second is plenty for anything TPM does. */ |
| 87 | #define MAX_DELAY_US (1000 * 1000) |
| 88 | |
| 89 | /* Retrieve burst count value out of the status register contents. */ |
| 90 | static u16 burst_count(u32 status) |
| 91 | { |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 92 | return (status >> TIS_STS_BURST_COUNT_SHIFT) & |
| 93 | TIS_STS_BURST_COUNT_MASK; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 94 | } |
| 95 | |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 96 | /* TPM access wrappers to support tracing */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 97 | static u8 tpm_read_byte(struct tpm_tis_lpc_priv *priv, const u8 *ptr) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 98 | { |
| 99 | u8 ret = readb(ptr); |
| 100 | debug(PREFIX "Read reg 0x%4.4x returns 0x%2.2x\n", |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 101 | (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, ret); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 102 | return ret; |
| 103 | } |
| 104 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 105 | static u32 tpm_read_word(struct tpm_tis_lpc_priv *priv, const u32 *ptr) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 106 | { |
| 107 | u32 ret = readl(ptr); |
| 108 | debug(PREFIX "Read reg 0x%4.4x returns 0x%8.8x\n", |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 109 | (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, ret); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 110 | return ret; |
| 111 | } |
| 112 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 113 | static void tpm_write_byte(struct tpm_tis_lpc_priv *priv, u8 value, u8 *ptr) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 114 | { |
| 115 | debug(PREFIX "Write reg 0x%4.4x with 0x%2.2x\n", |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 116 | (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, value); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 117 | writeb(value, ptr); |
| 118 | } |
| 119 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 120 | static void tpm_write_word(struct tpm_tis_lpc_priv *priv, u32 value, |
| 121 | u32 *ptr) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 122 | { |
| 123 | debug(PREFIX "Write reg 0x%4.4x with 0x%8.8x\n", |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 124 | (u32)(uintptr_t)ptr - (u32)(uintptr_t)priv->regs, value); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 125 | writel(value, ptr); |
| 126 | } |
| 127 | |
| 128 | /* |
| 129 | * tis_wait_reg() |
| 130 | * |
| 131 | * Wait for at least a second for a register to change its state to match the |
| 132 | * expected state. Normally the transition happens within microseconds. |
| 133 | * |
| 134 | * @reg - pointer to the TPM register |
| 135 | * @mask - bitmask for the bitfield(s) to watch |
| 136 | * @expected - value the field(s) are supposed to be set to |
| 137 | * |
| 138 | * Returns the register contents in case the expected value was found in the |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 139 | * appropriate register bits, or -ETIMEDOUT on timeout. |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 140 | */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 141 | static int tis_wait_reg(struct tpm_tis_lpc_priv *priv, u32 *reg, u8 mask, |
| 142 | u8 expected) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 143 | { |
| 144 | u32 time_us = MAX_DELAY_US; |
| 145 | |
| 146 | while (time_us > 0) { |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 147 | u32 value = tpm_read_word(priv, reg); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 148 | if ((value & mask) == expected) |
| 149 | return value; |
| 150 | udelay(1); /* 1 us */ |
| 151 | time_us--; |
| 152 | } |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 153 | |
| 154 | return -ETIMEDOUT; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | /* |
| 158 | * Probe the TPM device and try determining its manufacturer/device name. |
| 159 | * |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 160 | * Returns 0 on success, -ve on error |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 161 | */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 162 | static int tpm_tis_lpc_probe(struct udevice *dev) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 163 | { |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 164 | struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 165 | fdt_addr_t addr; |
| 166 | u32 didvid; |
George McCollister | a982b6f | 2016-10-17 09:24:32 -0500 | [diff] [blame] | 167 | ulong chip_type = dev_get_driver_data(dev); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 168 | |
Simon Glass | c89d32a | 2018-10-01 12:22:27 -0600 | [diff] [blame] | 169 | addr = dev_read_addr(dev); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 170 | if (addr == FDT_ADDR_T_NONE) |
| 171 | return -EINVAL; |
| 172 | priv->regs = map_sysmem(addr, 0); |
| 173 | didvid = tpm_read_word(priv, &priv->regs[0].did_vid); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 174 | |
George McCollister | a982b6f | 2016-10-17 09:24:32 -0500 | [diff] [blame] | 175 | if (didvid != chip_didvid[chip_type]) { |
| 176 | u32 vid, did; |
| 177 | vid = didvid & 0xffff; |
| 178 | did = (didvid >> 16) & 0xffff; |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 179 | debug("Invalid vendor/device ID %04x/%04x\n", vid, did); |
George McCollister | a982b6f | 2016-10-17 09:24:32 -0500 | [diff] [blame] | 180 | return -ENODEV; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 181 | } |
| 182 | |
George McCollister | a982b6f | 2016-10-17 09:24:32 -0500 | [diff] [blame] | 183 | debug("Found TPM: %s\n", chip_name[chip_type]); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 184 | |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | /* |
| 189 | * tis_senddata() |
| 190 | * |
| 191 | * send the passed in data to the TPM device. |
| 192 | * |
| 193 | * @data - address of the data to send, byte by byte |
| 194 | * @len - length of the data to send |
| 195 | * |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 196 | * Returns 0 on success, -ve on error (in case the device does not accept |
| 197 | * the entire command). |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 198 | */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 199 | static int tis_senddata(struct udevice *dev, const u8 *data, size_t len) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 200 | { |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 201 | struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); |
| 202 | struct tpm_locality *regs = priv->regs; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 203 | u32 offset = 0; |
| 204 | u16 burst = 0; |
| 205 | u32 max_cycles = 0; |
| 206 | u8 locality = 0; |
| 207 | u32 value; |
| 208 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 209 | value = tis_wait_reg(priv, ®s[locality].tpm_status, |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 210 | TIS_STS_COMMAND_READY, TIS_STS_COMMAND_READY); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 211 | if (value == -ETIMEDOUT) { |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 212 | printf("%s:%d - failed to get 'command_ready' status\n", |
| 213 | __FILE__, __LINE__); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 214 | return value; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 215 | } |
| 216 | burst = burst_count(value); |
| 217 | |
| 218 | while (1) { |
| 219 | unsigned count; |
| 220 | |
| 221 | /* Wait till the device is ready to accept more data. */ |
| 222 | while (!burst) { |
| 223 | if (max_cycles++ == MAX_DELAY_US) { |
Simon Glass | 22230e9 | 2016-09-25 21:33:20 -0600 | [diff] [blame] | 224 | printf("%s:%d failed to feed %zd bytes of %zd\n", |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 225 | __FILE__, __LINE__, len - offset, len); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 226 | return -ETIMEDOUT; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 227 | } |
| 228 | udelay(1); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 229 | burst = burst_count(tpm_read_word(priv, |
| 230 | ®s[locality].tpm_status)); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | max_cycles = 0; |
| 234 | |
| 235 | /* |
| 236 | * Calculate number of bytes the TPM is ready to accept in one |
| 237 | * shot. |
| 238 | * |
| 239 | * We want to send the last byte outside of the loop (hence |
| 240 | * the -1 below) to make sure that the 'expected' status bit |
| 241 | * changes to zero exactly after the last byte is fed into the |
| 242 | * FIFO. |
| 243 | */ |
Simon Glass | 22230e9 | 2016-09-25 21:33:20 -0600 | [diff] [blame] | 244 | count = min((size_t)burst, len - offset - 1); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 245 | while (count--) |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 246 | tpm_write_byte(priv, data[offset++], |
| 247 | ®s[locality].data); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 248 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 249 | value = tis_wait_reg(priv, ®s[locality].tpm_status, |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 250 | TIS_STS_VALID, TIS_STS_VALID); |
| 251 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 252 | if ((value == -ETIMEDOUT) || !(value & TIS_STS_EXPECT)) { |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 253 | printf("%s:%d TPM command feed overflow\n", |
| 254 | __FILE__, __LINE__); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 255 | return value == -ETIMEDOUT ? value : -EIO; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | burst = burst_count(value); |
| 259 | if ((offset == (len - 1)) && burst) { |
| 260 | /* |
| 261 | * We need to be able to send the last byte to the |
| 262 | * device, so burst size must be nonzero before we |
| 263 | * break out. |
| 264 | */ |
| 265 | break; |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | /* Send the last byte. */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 270 | tpm_write_byte(priv, data[offset++], ®s[locality].data); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 271 | /* |
| 272 | * Verify that TPM does not expect any more data as part of this |
| 273 | * command. |
| 274 | */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 275 | value = tis_wait_reg(priv, ®s[locality].tpm_status, |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 276 | TIS_STS_VALID, TIS_STS_VALID); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 277 | if ((value == -ETIMEDOUT) || (value & TIS_STS_EXPECT)) { |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 278 | printf("%s:%d unexpected TPM status 0x%x\n", |
| 279 | __FILE__, __LINE__, value); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 280 | return value == -ETIMEDOUT ? value : -EIO; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 281 | } |
| 282 | |
| 283 | /* OK, sitting pretty, let's start the command execution. */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 284 | tpm_write_word(priv, TIS_STS_TPM_GO, ®s[locality].tpm_status); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | /* |
| 289 | * tis_readresponse() |
| 290 | * |
| 291 | * read the TPM device response after a command was issued. |
| 292 | * |
| 293 | * @buffer - address where to read the response, byte by byte. |
| 294 | * @len - pointer to the size of buffer |
| 295 | * |
| 296 | * On success stores the number of received bytes to len and returns 0. On |
| 297 | * errors (misformatted TPM data or synchronization problems) returns |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 298 | * -ve value. |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 299 | */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 300 | static int tis_readresponse(struct udevice *dev, u8 *buffer, size_t len) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 301 | { |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 302 | struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); |
| 303 | struct tpm_locality *regs = priv->regs; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 304 | u16 burst; |
| 305 | u32 value; |
| 306 | u32 offset = 0; |
| 307 | u8 locality = 0; |
| 308 | const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID; |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 309 | u32 expected_count = len; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 310 | int max_cycles = 0; |
| 311 | |
| 312 | /* Wait for the TPM to process the command. */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 313 | value = tis_wait_reg(priv, ®s[locality].tpm_status, |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 314 | has_data, has_data); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 315 | if (value == -ETIMEDOUT) { |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 316 | printf("%s:%d failed processing command\n", |
| 317 | __FILE__, __LINE__); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 318 | return value; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | do { |
| 322 | while ((burst = burst_count(value)) == 0) { |
| 323 | if (max_cycles++ == MAX_DELAY_US) { |
| 324 | printf("%s:%d TPM stuck on read\n", |
| 325 | __FILE__, __LINE__); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 326 | return -EIO; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 327 | } |
| 328 | udelay(1); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 329 | value = tpm_read_word(priv, ®s[locality].tpm_status); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | max_cycles = 0; |
| 333 | |
| 334 | while (burst-- && (offset < expected_count)) { |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 335 | buffer[offset++] = tpm_read_byte(priv, |
| 336 | ®s[locality].data); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 337 | |
| 338 | if (offset == 6) { |
| 339 | /* |
| 340 | * We got the first six bytes of the reply, |
| 341 | * let's figure out how many bytes to expect |
| 342 | * total - it is stored as a 4 byte number in |
| 343 | * network order, starting with offset 2 into |
| 344 | * the body of the reply. |
| 345 | */ |
| 346 | u32 real_length; |
| 347 | memcpy(&real_length, |
| 348 | buffer + 2, |
| 349 | sizeof(real_length)); |
| 350 | expected_count = be32_to_cpu(real_length); |
| 351 | |
| 352 | if ((expected_count < offset) || |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 353 | (expected_count > len)) { |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 354 | printf("%s:%d bad response size %d\n", |
| 355 | __FILE__, __LINE__, |
| 356 | expected_count); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 357 | return -ENOSPC; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 358 | } |
| 359 | } |
| 360 | } |
| 361 | |
| 362 | /* Wait for the next portion. */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 363 | value = tis_wait_reg(priv, ®s[locality].tpm_status, |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 364 | TIS_STS_VALID, TIS_STS_VALID); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 365 | if (value == -ETIMEDOUT) { |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 366 | printf("%s:%d failed to read response\n", |
| 367 | __FILE__, __LINE__); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 368 | return value; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 369 | } |
| 370 | |
| 371 | if (offset == expected_count) |
| 372 | break; /* We got all we needed. */ |
| 373 | |
| 374 | } while ((value & has_data) == has_data); |
| 375 | |
| 376 | /* |
| 377 | * Make sure we indeed read all there was. The TIS_STS_VALID bit is |
| 378 | * known to be set. |
| 379 | */ |
| 380 | if (value & TIS_STS_DATA_AVAILABLE) { |
| 381 | printf("%s:%d wrong receive status %x\n", |
| 382 | __FILE__, __LINE__, value); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 383 | return -EBADMSG; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | /* Tell the TPM that we are done. */ |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 387 | tpm_write_word(priv, TIS_STS_COMMAND_READY, |
| 388 | ®s[locality].tpm_status); |
| 389 | |
| 390 | return offset; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 391 | } |
| 392 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 393 | static int tpm_tis_lpc_close(struct udevice *dev) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 394 | { |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 395 | struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); |
| 396 | struct tpm_locality *regs = priv->regs; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 397 | u8 locality = 0; |
| 398 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 399 | if (tpm_read_word(priv, ®s[locality].access) & |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 400 | TIS_ACCESS_ACTIVE_LOCALITY) { |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 401 | tpm_write_word(priv, TIS_ACCESS_ACTIVE_LOCALITY, |
| 402 | ®s[locality].access); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 403 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 404 | if (tis_wait_reg(priv, ®s[locality].access, |
| 405 | TIS_ACCESS_ACTIVE_LOCALITY, 0) == -ETIMEDOUT) { |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 406 | printf("%s:%d - failed to release locality %d\n", |
| 407 | __FILE__, __LINE__, locality); |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 408 | return -ETIMEDOUT; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 409 | } |
| 410 | } |
| 411 | return 0; |
| 412 | } |
| 413 | |
Simon Glass | 51f00c1 | 2018-11-18 14:22:26 -0700 | [diff] [blame] | 414 | static int tpm_tis_lpc_open(struct udevice *dev) |
| 415 | { |
| 416 | struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); |
| 417 | struct tpm_locality *regs = priv->regs; |
| 418 | u8 locality = 0; /* we use locality zero for everything. */ |
| 419 | int ret; |
| 420 | |
| 421 | ret = tpm_tis_lpc_close(dev); |
| 422 | if (ret) { |
| 423 | printf("%s: Failed to close TPM\n", __func__); |
| 424 | return ret; |
| 425 | } |
| 426 | |
| 427 | /* now request access to locality. */ |
| 428 | tpm_write_word(priv, TIS_ACCESS_REQUEST_USE, ®s[locality].access); |
| 429 | |
| 430 | /* did we get a lock? */ |
| 431 | ret = tis_wait_reg(priv, ®s[locality].access, |
| 432 | TIS_ACCESS_ACTIVE_LOCALITY, |
| 433 | TIS_ACCESS_ACTIVE_LOCALITY); |
| 434 | if (ret == -ETIMEDOUT) { |
| 435 | printf("%s:%d - failed to lock locality %d\n", |
| 436 | __FILE__, __LINE__, locality); |
| 437 | return ret; |
| 438 | } |
| 439 | |
| 440 | tpm_write_word(priv, TIS_STS_COMMAND_READY, |
| 441 | ®s[locality].tpm_status); |
| 442 | |
| 443 | return 0; |
| 444 | } |
| 445 | |
Ilias Apalodimas | c9e6d9c | 2021-11-09 09:02:16 +0200 | [diff] [blame] | 446 | static int tpm_tis_lpc_get_desc(struct udevice *dev, char *buf, int size) |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 447 | { |
George McCollister | a982b6f | 2016-10-17 09:24:32 -0500 | [diff] [blame] | 448 | ulong chip_type = dev_get_driver_data(dev); |
| 449 | |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 450 | if (size < 50) |
| 451 | return -ENOSPC; |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 452 | |
George McCollister | a982b6f | 2016-10-17 09:24:32 -0500 | [diff] [blame] | 453 | return snprintf(buf, size, "1.2 TPM (%s)", |
| 454 | chip_name[chip_type]); |
Vadim Bendebury | 5e12472 | 2011-10-17 08:36:14 +0000 | [diff] [blame] | 455 | } |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 456 | |
| 457 | |
| 458 | static const struct tpm_ops tpm_tis_lpc_ops = { |
| 459 | .open = tpm_tis_lpc_open, |
| 460 | .close = tpm_tis_lpc_close, |
Ilias Apalodimas | c9e6d9c | 2021-11-09 09:02:16 +0200 | [diff] [blame] | 461 | .get_desc = tpm_tis_lpc_get_desc, |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 462 | .send = tis_senddata, |
| 463 | .recv = tis_readresponse, |
| 464 | }; |
| 465 | |
| 466 | static const struct udevice_id tpm_tis_lpc_ids[] = { |
George McCollister | a982b6f | 2016-10-17 09:24:32 -0500 | [diff] [blame] | 467 | { .compatible = "infineon,slb9635lpc", .data = SLB9635 }, |
| 468 | { .compatible = "atmel,at97sc3204", .data = AT97SC3204 }, |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 469 | { } |
| 470 | }; |
| 471 | |
| 472 | U_BOOT_DRIVER(tpm_tis_lpc) = { |
| 473 | .name = "tpm_tis_lpc", |
| 474 | .id = UCLASS_TPM, |
| 475 | .of_match = tpm_tis_lpc_ids, |
| 476 | .ops = &tpm_tis_lpc_ops, |
| 477 | .probe = tpm_tis_lpc_probe, |
Simon Glass | 41575d8 | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 478 | .priv_auto = sizeof(struct tpm_tis_lpc_priv), |
Simon Glass | d616ba5 | 2015-08-22 18:31:39 -0600 | [diff] [blame] | 479 | }; |