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wdenk3f85ce22004-02-23 16:11:30 +00001/*
2 * Copyright (c) 2004 Picture Elements, Inc.
3 * Stephen Williams (XXXXXXXXXXXXXXXX)
4 *
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 */
wdenk3f85ce22004-02-23 16:11:30 +000020
21/*
22 * The Xilinx SystemACE chip support is activated by defining
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023 * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE
wdenk3f85ce22004-02-23 16:11:30 +000024 * to set the base address of the device. This code currently
25 * assumes that the chip is connected via a byte-wide bus.
26 *
27 * The CONFIG_SYSTEMACE also adds to fat support the device class
28 * "ace" that allows the user to execute "fatls ace 0" and the
29 * like. This works by making the systemace_get_dev function
30 * available to cmd_fat.c:get_dev and filling in a block device
31 * description that has all the bits needed for FAT support to
32 * read sectors.
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +020033 *
Wolfgang Denkfe599e12005-08-07 23:55:50 +020034 * According to Xilinx technical support, before accessing the
35 * SystemACE CF you need to set the following control bits:
Grant Likely984618f2007-02-20 09:05:16 +010036 * FORCECFGMODE : 1
37 * CFGMODE : 0
38 * CFGSTART : 0
wdenk3f85ce22004-02-23 16:11:30 +000039 */
40
Grant Likely984618f2007-02-20 09:05:16 +010041#include <common.h>
42#include <command.h>
43#include <systemace.h>
44#include <part.h>
45#include <asm/io.h>
wdenk3f85ce22004-02-23 16:11:30 +000046
wdenk3f85ce22004-02-23 16:11:30 +000047/*
48 * The ace_readw and writew functions read/write 16bit words, but the
49 * offset value is the BYTE offset as most used in the Xilinx
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined
wdenk3f85ce22004-02-23 16:11:30 +000051 * to be the base address for the chip, usually in the local
52 * peripheral bus.
53 */
wdenk3f85ce22004-02-23 16:11:30 +000054
Michal Simek5340a7f2012-07-04 12:09:45 +020055static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
56static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
57
58static void ace_writew(u16 val, unsigned off)
59{
60 if (width == 8) {
61#if !defined(__BIG_ENDIAN)
62 writeb(val >> 8, base + off);
63 writeb(val, base + off + 1);
64#else
65 writeb(val, base + off);
66 writeb(val >> 8, base + off + 1);
67#endif
Alexey Brodkin7cde9f32013-01-03 13:35:23 +040068 } else
69 out16(base + off, val);
Michal Simek5340a7f2012-07-04 12:09:45 +020070}
71
72static u16 ace_readw(unsigned off)
73{
74 if (width == 8) {
75#if !defined(__BIG_ENDIAN)
76 return (readb(base + off) << 8) | readb(base + off + 1);
77#else
78 return readb(base + off) | (readb(base + off + 1) << 8);
79#endif
80 }
81
82 return in16(base + off);
83}
wdenk3f85ce22004-02-23 16:11:30 +000084
Grant Likely984618f2007-02-20 09:05:16 +010085static unsigned long systemace_read(int dev, unsigned long start,
Alexey Brodkinac1048a2013-01-03 01:02:46 +000086 lbaint_t blkcnt, void *buffer);
wdenk3f85ce22004-02-23 16:11:30 +000087
Grant Likely984618f2007-02-20 09:05:16 +010088static block_dev_desc_t systemace_dev = { 0 };
wdenk3f85ce22004-02-23 16:11:30 +000089
90static int get_cf_lock(void)
91{
Grant Likely984618f2007-02-20 09:05:16 +010092 int retry = 10;
wdenk3f85ce22004-02-23 16:11:30 +000093
94 /* CONTROLREG = LOCKREG */
Grant Likely984618f2007-02-20 09:05:16 +010095 unsigned val = ace_readw(0x18);
96 val |= 0x0002;
97 ace_writew((val & 0xffff), 0x18);
wdenk3f85ce22004-02-23 16:11:30 +000098
99 /* Wait for MPULOCK in STATUSREG[15:0] */
Grant Likely984618f2007-02-20 09:05:16 +0100100 while (!(ace_readw(0x04) & 0x0002)) {
wdenk3f85ce22004-02-23 16:11:30 +0000101
Grant Likely984618f2007-02-20 09:05:16 +0100102 if (retry < 0)
103 return -1;
wdenk3f85ce22004-02-23 16:11:30 +0000104
Grant Likely984618f2007-02-20 09:05:16 +0100105 udelay(100000);
106 retry -= 1;
107 }
wdenk3f85ce22004-02-23 16:11:30 +0000108
Grant Likely984618f2007-02-20 09:05:16 +0100109 return 0;
wdenk3f85ce22004-02-23 16:11:30 +0000110}
111
112static void release_cf_lock(void)
113{
Grant Likely984618f2007-02-20 09:05:16 +0100114 unsigned val = ace_readw(0x18);
115 val &= ~(0x0002);
116 ace_writew((val & 0xffff), 0x18);
wdenk3f85ce22004-02-23 16:11:30 +0000117}
118
Matthew McClintockdf3fc522011-05-24 05:31:19 +0000119#ifdef CONFIG_PARTITIONS
Grant Likely984618f2007-02-20 09:05:16 +0100120block_dev_desc_t *systemace_get_dev(int dev)
wdenk3f85ce22004-02-23 16:11:30 +0000121{
122 /* The first time through this, the systemace_dev object is
123 not yet initialized. In that case, fill it in. */
Grant Likely984618f2007-02-20 09:05:16 +0100124 if (systemace_dev.blksz == 0) {
125 systemace_dev.if_type = IF_TYPE_UNKNOWN;
126 systemace_dev.dev = 0;
127 systemace_dev.part_type = PART_TYPE_UNKNOWN;
128 systemace_dev.type = DEV_TYPE_HARDDISK;
129 systemace_dev.blksz = 512;
130 systemace_dev.removable = 1;
131 systemace_dev.block_read = systemace_read;
Wolfgang Denkfe599e12005-08-07 23:55:50 +0200132
Stefan Roesed93e2212007-02-20 13:17:42 +0100133 /*
Stefan Roese8274ec02007-02-22 07:40:23 +0100134 * Ensure the correct bus mode (8/16 bits) gets enabled
Stefan Roesed93e2212007-02-20 13:17:42 +0100135 */
Michal Simek5340a7f2012-07-04 12:09:45 +0200136 ace_writew(width == 8 ? 0 : 0x0001, 0);
Stefan Roesed93e2212007-02-20 13:17:42 +0100137
Grant Likely984618f2007-02-20 09:05:16 +0100138 init_part(&systemace_dev);
Wolfgang Denkfe599e12005-08-07 23:55:50 +0200139
Grant Likely984618f2007-02-20 09:05:16 +0100140 }
wdenk3f85ce22004-02-23 16:11:30 +0000141
Grant Likely984618f2007-02-20 09:05:16 +0100142 return &systemace_dev;
wdenk3f85ce22004-02-23 16:11:30 +0000143}
Matthew McClintockdf3fc522011-05-24 05:31:19 +0000144#endif
wdenk3f85ce22004-02-23 16:11:30 +0000145
146/*
147 * This function is called (by dereferencing the block_read pointer in
148 * the dev_desc) to read blocks of data. The return value is the
149 * number of blocks read. A zero return indicates an error.
150 */
Grant Likely984618f2007-02-20 09:05:16 +0100151static unsigned long systemace_read(int dev, unsigned long start,
Alexey Brodkinac1048a2013-01-03 01:02:46 +0000152 lbaint_t blkcnt, void *buffer)
wdenk3f85ce22004-02-23 16:11:30 +0000153{
Grant Likely984618f2007-02-20 09:05:16 +0100154 int retry;
155 unsigned blk_countdown;
Grant Likelyeb867a72007-02-20 09:05:45 +0100156 unsigned char *dp = buffer;
Grant Likely984618f2007-02-20 09:05:16 +0100157 unsigned val;
wdenk3f85ce22004-02-23 16:11:30 +0000158
Grant Likely984618f2007-02-20 09:05:16 +0100159 if (get_cf_lock() < 0) {
160 unsigned status = ace_readw(0x04);
wdenk3f85ce22004-02-23 16:11:30 +0000161
Grant Likely984618f2007-02-20 09:05:16 +0100162 /* If CFDETECT is false, card is missing. */
163 if (!(status & 0x0010)) {
164 printf("** CompactFlash card not present. **\n");
165 return 0;
166 }
wdenk3f85ce22004-02-23 16:11:30 +0000167
Grant Likely984618f2007-02-20 09:05:16 +0100168 printf("**** ACE locked away from me (STATUSREG=%04x)\n",
169 status);
170 return 0;
171 }
wdenke7c85682004-02-27 08:21:54 +0000172#ifdef DEBUG_SYSTEMACE
Grant Likely984618f2007-02-20 09:05:16 +0100173 printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
wdenke7c85682004-02-27 08:21:54 +0000174#endif
175
Grant Likely984618f2007-02-20 09:05:16 +0100176 retry = 2000;
177 for (;;) {
178 val = ace_readw(0x04);
wdenk3f85ce22004-02-23 16:11:30 +0000179
Grant Likely984618f2007-02-20 09:05:16 +0100180 /* If CFDETECT is false, card is missing. */
181 if (!(val & 0x0010)) {
182 printf("**** ACE CompactFlash not found.\n");
183 release_cf_lock();
184 return 0;
185 }
wdenk3f85ce22004-02-23 16:11:30 +0000186
Grant Likely984618f2007-02-20 09:05:16 +0100187 /* If RDYFORCMD, then we are ready to go. */
188 if (val & 0x0100)
189 break;
wdenk3f85ce22004-02-23 16:11:30 +0000190
Grant Likely984618f2007-02-20 09:05:16 +0100191 if (retry < 0) {
192 printf("**** SystemACE not ready.\n");
193 release_cf_lock();
194 return 0;
195 }
wdenk3f85ce22004-02-23 16:11:30 +0000196
Grant Likely984618f2007-02-20 09:05:16 +0100197 udelay(1000);
198 retry -= 1;
199 }
wdenk3f85ce22004-02-23 16:11:30 +0000200
wdenke7c85682004-02-27 08:21:54 +0000201 /* The SystemACE can only transfer 256 sectors at a time, so
202 limit the current chunk of sectors. The blk_countdown
203 variable is the number of sectors left to transfer. */
wdenk3f85ce22004-02-23 16:11:30 +0000204
Grant Likely984618f2007-02-20 09:05:16 +0100205 blk_countdown = blkcnt;
206 while (blk_countdown > 0) {
207 unsigned trans = blk_countdown;
wdenk3f85ce22004-02-23 16:11:30 +0000208
Grant Likely984618f2007-02-20 09:05:16 +0100209 if (trans > 256)
210 trans = 256;
wdenk3f85ce22004-02-23 16:11:30 +0000211
wdenke7c85682004-02-27 08:21:54 +0000212#ifdef DEBUG_SYSTEMACE
Grant Likely984618f2007-02-20 09:05:16 +0100213 printf("... transfer %lu sector in a chunk\n", trans);
wdenke7c85682004-02-27 08:21:54 +0000214#endif
Grant Likely984618f2007-02-20 09:05:16 +0100215 /* Write LBA block address */
216 ace_writew((start >> 0) & 0xffff, 0x10);
Stefan Roesed93e2212007-02-20 13:17:42 +0100217 ace_writew((start >> 16) & 0x0fff, 0x12);
wdenk3f85ce22004-02-23 16:11:30 +0000218
Grant Likely984618f2007-02-20 09:05:16 +0100219 /* NOTE: in the Write Sector count below, a count of 0
220 causes a transfer of 256, so &0xff gives the right
221 value for whatever transfer count we want. */
wdenke7c85682004-02-27 08:21:54 +0000222
Grant Likely984618f2007-02-20 09:05:16 +0100223 /* Write sector count | ReadMemCardData. */
224 ace_writew((trans & 0xff) | 0x0300, 0x14);
wdenke7c85682004-02-27 08:21:54 +0000225
Wolfgang Denkd62f64c2007-05-16 00:13:33 +0200226/*
Michal Simek32556442007-04-21 21:07:22 +0200227 * For FPGA configuration via SystemACE is reset unacceptable
228 * CFGDONE bit in STATUSREG is not set to 1.
229 */
230#ifndef SYSTEMACE_CONFIG_FPGA
Grant Likely984618f2007-02-20 09:05:16 +0100231 /* Reset the configruation controller */
232 val = ace_readw(0x18);
233 val |= 0x0080;
234 ace_writew(val, 0x18);
Michal Simek32556442007-04-21 21:07:22 +0200235#endif
Wolfgang Denkfe599e12005-08-07 23:55:50 +0200236
Grant Likely984618f2007-02-20 09:05:16 +0100237 retry = trans * 16;
238 while (retry > 0) {
239 int idx;
wdenke7c85682004-02-27 08:21:54 +0000240
Grant Likely984618f2007-02-20 09:05:16 +0100241 /* Wait for buffer to become ready. */
242 while (!(ace_readw(0x04) & 0x0020)) {
243 udelay(100);
244 }
wdenke7c85682004-02-27 08:21:54 +0000245
Grant Likely984618f2007-02-20 09:05:16 +0100246 /* Read 16 words of 2bytes from the sector buffer. */
247 for (idx = 0; idx < 16; idx += 1) {
248 unsigned short val = ace_readw(0x40);
249 *dp++ = val & 0xff;
250 *dp++ = (val >> 8) & 0xff;
251 }
wdenke7c85682004-02-27 08:21:54 +0000252
Grant Likely984618f2007-02-20 09:05:16 +0100253 retry -= 1;
254 }
wdenk3f85ce22004-02-23 16:11:30 +0000255
Grant Likely984618f2007-02-20 09:05:16 +0100256 /* Clear the configruation controller reset */
257 val = ace_readw(0x18);
258 val &= ~0x0080;
259 ace_writew(val, 0x18);
Wolfgang Denkfe599e12005-08-07 23:55:50 +0200260
Grant Likely984618f2007-02-20 09:05:16 +0100261 /* Count the blocks we transfer this time. */
262 start += trans;
263 blk_countdown -= trans;
264 }
wdenk3f85ce22004-02-23 16:11:30 +0000265
Grant Likely984618f2007-02-20 09:05:16 +0100266 release_cf_lock();
wdenk3f85ce22004-02-23 16:11:30 +0000267
Grant Likely984618f2007-02-20 09:05:16 +0100268 return blkcnt;
wdenk3f85ce22004-02-23 16:11:30 +0000269}