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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming9082eea2011-04-07 21:56:05 -05002/*
3 * RealTek PHY drivers
4 *
Codrin Ciubotariu3cee1382015-02-13 14:47:58 +02005 * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
Andy Fleming9082eea2011-04-07 21:56:05 -05006 * author Andy Fleming
Karsten Merker563d8d92016-03-21 20:29:07 +01007 * Copyright 2016 Karsten Merker <merker@debian.org>
Andy Fleming9082eea2011-04-07 21:56:05 -05008 */
Andy Fleming9082eea2011-04-07 21:56:05 -05009#include <common.h>
oliver@schinagl.nl020f6762016-11-08 17:38:57 +010010#include <linux/bitops.h>
Andy Fleming9082eea2011-04-07 21:56:05 -050011#include <phy.h>
12
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +010013#define PHY_RTL8211x_FORCE_MASTER BIT(1)
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -060014#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
Carlo Caioned47cfdb2019-01-24 08:54:37 +000015#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +010016
Andy Fleming9082eea2011-04-07 21:56:05 -050017#define PHY_AUTONEGOTIATE_TIMEOUT 5000
18
Michael Haas525d1872016-03-25 18:22:50 +010019/* RTL8211x 1000BASE-T Control Register */
oliver@schinagl.nl020f6762016-11-08 17:38:57 +010020#define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
oliver@schinagl.nlcbe40e12016-11-08 17:38:58 +010021#define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
Michael Haas525d1872016-03-25 18:22:50 +010022
Bhupesh Sharmac624d162013-07-18 13:58:20 +053023/* RTL8211x PHY Status Register */
24#define MIIM_RTL8211x_PHY_STATUS 0x11
25#define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
26#define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
27#define MIIM_RTL8211x_PHYSTAT_100 0x4000
28#define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
29#define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
30#define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
Andy Fleming9082eea2011-04-07 21:56:05 -050031
Codrin Ciubotariu3cee1382015-02-13 14:47:58 +020032/* RTL8211x PHY Interrupt Enable Register */
33#define MIIM_RTL8211x_PHY_INER 0x12
34#define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
35#define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
36
37/* RTL8211x PHY Interrupt Status Register */
38#define MIIM_RTL8211x_PHY_INSR 0x13
Andy Fleming9082eea2011-04-07 21:56:05 -050039
Shengzhou Liu3d6af742015-03-12 18:54:59 +080040/* RTL8211F PHY Status Register */
41#define MIIM_RTL8211F_PHY_STATUS 0x1a
42#define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000
43#define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030
44#define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020
45#define MIIM_RTL8211F_PHYSTAT_100 0x0010
46#define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008
47#define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
48#define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
49
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -060050#define MIIM_RTL8211E_CONFREG 0x1c
51#define MIIM_RTL8211E_CONFREG_TXD 0x0002
52#define MIIM_RTL8211E_CONFREG_RXD 0x0004
53#define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */
54
55#define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
56
Shengzhou Liu3d6af742015-03-12 18:54:59 +080057#define MIIM_RTL8211F_PAGE_SELECT 0x1f
Shengzhou Liu793ea942015-04-24 16:57:17 +080058#define MIIM_RTL8211F_TX_DELAY 0x100
Shengzhou Liu90712742015-05-21 18:07:35 +080059#define MIIM_RTL8211F_LCR 0x10
Shengzhou Liu3d6af742015-03-12 18:54:59 +080060
Carlo Caionee57c9fd2019-01-16 11:34:50 +000061static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
62 int devaddr, int regnum)
63{
64 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
65 MIIM_RTL8211F_PAGE_SELECT);
66 int val;
67
68 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
69 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
70 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
71
72 return val;
73}
74
75static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
76 int devaddr, int regnum, u16 val)
77{
78 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
79 MIIM_RTL8211F_PAGE_SELECT);
80
81 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
82 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
83 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
84
85 return 0;
86}
87
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +010088static int rtl8211b_probe(struct phy_device *phydev)
89{
90#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
91 phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
92#endif
93
94 return 0;
95}
96
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -060097static int rtl8211e_probe(struct phy_device *phydev)
98{
99#ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
100 phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
101#endif
102
103 return 0;
104}
105
Carlo Caioned47cfdb2019-01-24 08:54:37 +0000106static int rtl8211f_probe(struct phy_device *phydev)
107{
108#ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
109 phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
110#endif
111
112 return 0;
113}
114
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530115/* RealTek RTL8211x */
116static int rtl8211x_config(struct phy_device *phydev)
Andy Fleming9082eea2011-04-07 21:56:05 -0500117{
118 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
119
Codrin Ciubotariu3cee1382015-02-13 14:47:58 +0200120 /* mask interrupt at init; if the interrupt is
121 * needed indeed, it should be explicitly enabled
122 */
123 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
124 MIIM_RTL8211x_PHY_INTR_DIS);
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +0100125
126 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
127 unsigned int reg;
128
129 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
130 /* force manual master/slave configuration */
131 reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
132 /* force master mode */
133 reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
134 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
135 }
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -0600136 if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
137 unsigned int reg;
138
139 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
140 7);
141 phy_write(phydev, MDIO_DEVAD_NONE,
142 MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
143 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
144 /* Ensure both internal delays are turned off */
145 reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
146 /* Flip the magic undocumented bits */
147 reg |= MIIM_RTL8211E_CONFREG_MAGIC;
148 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
149 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
150 0);
151 }
Codrin Ciubotariu3cee1382015-02-13 14:47:58 +0200152 /* read interrupt status just to clear it */
153 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
154
Andy Fleming9082eea2011-04-07 21:56:05 -0500155 genphy_config_aneg(phydev);
156
157 return 0;
158}
159
Shengzhou Liu793ea942015-04-24 16:57:17 +0800160static int rtl8211f_config(struct phy_device *phydev)
161{
162 u16 reg;
163
Carlo Caioned47cfdb2019-01-24 08:54:37 +0000164 if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
165 unsigned int reg;
166
167 reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
168 reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
169 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
170 }
171
Shengzhou Liu793ea942015-04-24 16:57:17 +0800172 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
173
Madalin Bucur05b29aa2017-08-18 11:35:24 +0300174 phy_write(phydev, MDIO_DEVAD_NONE,
175 MIIM_RTL8211F_PAGE_SELECT, 0xd08);
176 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
177
178 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
179 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
180 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
Shengzhou Liu793ea942015-04-24 16:57:17 +0800181 reg |= MIIM_RTL8211F_TX_DELAY;
Madalin Bucur05b29aa2017-08-18 11:35:24 +0300182 else
183 reg &= ~MIIM_RTL8211F_TX_DELAY;
184
185 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
186 /* restore to default page 0 */
187 phy_write(phydev, MDIO_DEVAD_NONE,
188 MIIM_RTL8211F_PAGE_SELECT, 0x0);
Shengzhou Liu793ea942015-04-24 16:57:17 +0800189
Shengzhou Liu90712742015-05-21 18:07:35 +0800190 /* Set green LED for Link, yellow LED for Active */
191 phy_write(phydev, MDIO_DEVAD_NONE,
192 MIIM_RTL8211F_PAGE_SELECT, 0xd04);
193 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
194 phy_write(phydev, MDIO_DEVAD_NONE,
195 MIIM_RTL8211F_PAGE_SELECT, 0x0);
196
Shengzhou Liu793ea942015-04-24 16:57:17 +0800197 genphy_config_aneg(phydev);
198
199 return 0;
200}
201
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530202static int rtl8211x_parse_status(struct phy_device *phydev)
Andy Fleming9082eea2011-04-07 21:56:05 -0500203{
204 unsigned int speed;
205 unsigned int mii_reg;
206
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530207 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
Andy Fleming9082eea2011-04-07 21:56:05 -0500208
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530209 if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
Andy Fleming9082eea2011-04-07 21:56:05 -0500210 int i = 0;
211
212 /* in case of timeout ->link is cleared */
213 phydev->link = 1;
214 puts("Waiting for PHY realtime link");
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530215 while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
Andy Fleming9082eea2011-04-07 21:56:05 -0500216 /* Timeout reached ? */
217 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
218 puts(" TIMEOUT !\n");
219 phydev->link = 0;
220 break;
221 }
222
223 if ((i++ % 1000) == 0)
224 putc('.');
225 udelay(1000); /* 1 ms */
226 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530227 MIIM_RTL8211x_PHY_STATUS);
Andy Fleming9082eea2011-04-07 21:56:05 -0500228 }
229 puts(" done\n");
230 udelay(500000); /* another 500 ms (results in faster booting) */
231 } else {
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530232 if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
Andy Fleming9082eea2011-04-07 21:56:05 -0500233 phydev->link = 1;
234 else
235 phydev->link = 0;
236 }
237
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530238 if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
Andy Fleming9082eea2011-04-07 21:56:05 -0500239 phydev->duplex = DUPLEX_FULL;
240 else
241 phydev->duplex = DUPLEX_HALF;
242
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530243 speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
Andy Fleming9082eea2011-04-07 21:56:05 -0500244
245 switch (speed) {
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530246 case MIIM_RTL8211x_PHYSTAT_GBIT:
Andy Fleming9082eea2011-04-07 21:56:05 -0500247 phydev->speed = SPEED_1000;
248 break;
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530249 case MIIM_RTL8211x_PHYSTAT_100:
Andy Fleming9082eea2011-04-07 21:56:05 -0500250 phydev->speed = SPEED_100;
251 break;
252 default:
253 phydev->speed = SPEED_10;
254 }
255
256 return 0;
257}
258
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800259static int rtl8211f_parse_status(struct phy_device *phydev)
260{
261 unsigned int speed;
262 unsigned int mii_reg;
263 int i = 0;
264
265 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43);
266 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS);
267
268 phydev->link = 1;
269 while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) {
270 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
271 puts(" TIMEOUT !\n");
272 phydev->link = 0;
273 break;
274 }
275
276 if ((i++ % 1000) == 0)
277 putc('.');
278 udelay(1000);
279 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
280 MIIM_RTL8211F_PHY_STATUS);
281 }
282
283 if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX)
284 phydev->duplex = DUPLEX_FULL;
285 else
286 phydev->duplex = DUPLEX_HALF;
287
288 speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED);
289
290 switch (speed) {
291 case MIIM_RTL8211F_PHYSTAT_GBIT:
292 phydev->speed = SPEED_1000;
293 break;
294 case MIIM_RTL8211F_PHYSTAT_100:
295 phydev->speed = SPEED_100;
296 break;
297 default:
298 phydev->speed = SPEED_10;
299 }
300
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800301 return 0;
302}
303
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530304static int rtl8211x_startup(struct phy_device *phydev)
Andy Fleming9082eea2011-04-07 21:56:05 -0500305{
Michal Simekb733c272016-05-18 12:46:12 +0200306 int ret;
Andy Fleming9082eea2011-04-07 21:56:05 -0500307
Michal Simekb733c272016-05-18 12:46:12 +0200308 /* Read the Status (2x to make sure link is right) */
309 ret = genphy_update_link(phydev);
310 if (ret)
311 return ret;
312
313 return rtl8211x_parse_status(phydev);
Andy Fleming9082eea2011-04-07 21:56:05 -0500314}
315
Michal Simek6a10bc52016-02-13 10:31:32 +0100316static int rtl8211e_startup(struct phy_device *phydev)
317{
Michal Simekb733c272016-05-18 12:46:12 +0200318 int ret;
Michal Simek6a10bc52016-02-13 10:31:32 +0100319
Michal Simekb733c272016-05-18 12:46:12 +0200320 ret = genphy_update_link(phydev);
321 if (ret)
322 return ret;
323
324 return genphy_parse_link(phydev);
Michal Simek6a10bc52016-02-13 10:31:32 +0100325}
326
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800327static int rtl8211f_startup(struct phy_device *phydev)
328{
Michal Simekb733c272016-05-18 12:46:12 +0200329 int ret;
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800330
Michal Simekb733c272016-05-18 12:46:12 +0200331 /* Read the Status (2x to make sure link is right) */
332 ret = genphy_update_link(phydev);
333 if (ret)
334 return ret;
335 /* Read the Status (2x to make sure link is right) */
336
337 return rtl8211f_parse_status(phydev);
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800338}
339
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530340/* Support for RTL8211B PHY */
Andy Fleming9082eea2011-04-07 21:56:05 -0500341static struct phy_driver RTL8211B_driver = {
342 .name = "RealTek RTL8211B",
Karsten Merker563d8d92016-03-21 20:29:07 +0100343 .uid = 0x1cc912,
Bhupesh Sharma42205042013-09-01 04:40:52 +0530344 .mask = 0xffffff,
Andy Fleming9082eea2011-04-07 21:56:05 -0500345 .features = PHY_GBIT_FEATURES,
oliver@schinagl.nlcebf3f52016-11-08 17:38:59 +0100346 .probe = &rtl8211b_probe,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530347 .config = &rtl8211x_config,
348 .startup = &rtl8211x_startup,
349 .shutdown = &genphy_shutdown,
350};
351
352/* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
353static struct phy_driver RTL8211E_driver = {
354 .name = "RealTek RTL8211E",
355 .uid = 0x1cc915,
Bhupesh Sharma42205042013-09-01 04:40:52 +0530356 .mask = 0xffffff,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530357 .features = PHY_GBIT_FEATURES,
kevans@FreeBSD.org66526e72018-02-14 17:02:15 -0600358 .probe = &rtl8211e_probe,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530359 .config = &rtl8211x_config,
Michal Simek6a10bc52016-02-13 10:31:32 +0100360 .startup = &rtl8211e_startup,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530361 .shutdown = &genphy_shutdown,
362};
363
364/* Support for RTL8211DN PHY */
365static struct phy_driver RTL8211DN_driver = {
366 .name = "RealTek RTL8211DN",
367 .uid = 0x1cc914,
Bhupesh Sharma42205042013-09-01 04:40:52 +0530368 .mask = 0xffffff,
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530369 .features = PHY_GBIT_FEATURES,
370 .config = &rtl8211x_config,
371 .startup = &rtl8211x_startup,
Andy Fleming9082eea2011-04-07 21:56:05 -0500372 .shutdown = &genphy_shutdown,
373};
374
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800375/* Support for RTL8211F PHY */
376static struct phy_driver RTL8211F_driver = {
377 .name = "RealTek RTL8211F",
378 .uid = 0x1cc916,
379 .mask = 0xffffff,
380 .features = PHY_GBIT_FEATURES,
Carlo Caioned47cfdb2019-01-24 08:54:37 +0000381 .probe = &rtl8211f_probe,
Shengzhou Liu793ea942015-04-24 16:57:17 +0800382 .config = &rtl8211f_config,
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800383 .startup = &rtl8211f_startup,
384 .shutdown = &genphy_shutdown,
Carlo Caionee57c9fd2019-01-16 11:34:50 +0000385 .readext = &rtl8211f_phy_extread,
386 .writeext = &rtl8211f_phy_extwrite,
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800387};
388
Andy Fleming9082eea2011-04-07 21:56:05 -0500389int phy_realtek_init(void)
390{
391 phy_register(&RTL8211B_driver);
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530392 phy_register(&RTL8211E_driver);
Shengzhou Liu3d6af742015-03-12 18:54:59 +0800393 phy_register(&RTL8211F_driver);
Bhupesh Sharmac624d162013-07-18 13:58:20 +0530394 phy_register(&RTL8211DN_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -0500395
396 return 0;
397}