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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 8251ed2323bf6594560a3c0a620f4742f8c024dc / . / board / amcc / bamboo / init.S
blob: 5c7c839079e8cf1f731a380685b342f99a0f9dd2 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]8 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]9
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200[diff] [blame]10#include <asm-offsets.h>
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]11#include <ppc_asm.tmpl>
12#include <config.h>
Peter Tyser61f2b382010-04-12 22:28:07 -0500[diff] [blame]13#include <asm/mmu.h>
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]14
15/**************************************************************************
16 * TLB TABLE
17 *
18 * This table is used by the cpu boot code to setup the initial tlb
19 * entries. Rather than make broad assumptions in the cpu source tree,
20 * this table lets each board set things up however they like.
21 *
22 * Pointer to the table is returned in r1
23 *
24 *************************************************************************/
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]25 .section .bootpg,"ax"
26 .globl tlbtab
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]27
28tlbtab:
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]29 tlbtab_start
Stefan Roesec57c7982005-08-11 17:56:56 +0200[diff] [blame]30
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]31 /*
32 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
33 * speed up boot process. It is patched after relocation to enable SA_I
34 */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]35 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
Stefan Roesec57c7982005-08-11 17:56:56 +0200[diff] [blame]36
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]37 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]38 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
Stefan Roesec57c7982005-08-11 17:56:56 +0200[diff] [blame]39
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]40 /* PCI base & peripherals */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]41 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
Stefan Roese8a316c92005-08-01 16:49:12 +0200[diff] [blame]42
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]43 tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
44 tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
Stefan Roese8a316c92005-08-01 16:49:12 +0200[diff] [blame]45
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]46 /* PCI */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]47 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
48 tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
49 tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
50 tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]51
52 /* USB 2.0 Device */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]53 tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
Stefan Roesea471db02007-06-01 15:19:29 +0200[diff] [blame]54
55 tlbtab_end