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TsiChungLiew57a12722008-01-15 14:15:46 -06001/*
2 * Configuation settings for the Freescale MCF5475 board.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew57a12722008-01-15 14:15:46 -06008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5475EVB_H
15#define _M5475EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChungLiew57a12722008-01-15 14:15:46 -060021
Alison Wang1313db42015-02-12 18:33:15 +080022#define CONFIG_DISPLAY_BOARDINFO
23
TsiChungLiew57a12722008-01-15 14:15:46 -060024#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew57a12722008-01-15 14:15:46 -060026#define CONFIG_BAUDRATE 115200
TsiChungLiew57a12722008-01-15 14:15:46 -060027
Alison Wang1313db42015-02-12 18:33:15 +080028#undef CONFIG_HW_WATCHDOG
TsiChungLiew57a12722008-01-15 14:15:46 -060029#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
30
31/* Command line configuration */
TsiChungLiew57a12722008-01-15 14:15:46 -060032#define CONFIG_CMD_CACHE
33#undef CONFIG_CMD_DATE
34#define CONFIG_CMD_ELF
TsiChungLiew57a12722008-01-15 14:15:46 -060035#define CONFIG_CMD_I2C
TsiChungLiew57a12722008-01-15 14:15:46 -060036#define CONFIG_CMD_MII
TsiChungLiew57a12722008-01-15 14:15:46 -060037#define CONFIG_CMD_PCI
38#define CONFIG_CMD_PING
39#define CONFIG_CMD_REGINFO
40#define CONFIG_CMD_USB
41
42#define CONFIG_SLTTMR
43
44#define CONFIG_FSLDMAFEC
45#ifdef CONFIG_FSLDMAFEC
TsiChungLiew57a12722008-01-15 14:15:46 -060046# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050047# define CONFIG_MII_INIT 1
TsiChungLiew57a12722008-01-15 14:15:46 -060048# define CONFIG_HAS_ETH1
49
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050# define CONFIG_SYS_DMA_USE_INTSRAM 1
51# define CONFIG_SYS_DISCOVER_PHY
52# define CONFIG_SYS_RX_ETH_BUFFER 32
53# define CONFIG_SYS_TX_ETH_BUFFER 48
54# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew57a12722008-01-15 14:15:46 -060055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056# define CONFIG_SYS_FEC0_PINMUX 0
57# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
58# define CONFIG_SYS_FEC1_PINMUX 0
59# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChungLiew57a12722008-01-15 14:15:46 -060060
Wolfgang Denk53677ef2008-05-20 16:00:29 +020061# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
63# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew57a12722008-01-15 14:15:46 -060064# define FECDUPLEX FULL
65# define FECSPEED _100BASET
66# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
68# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew57a12722008-01-15 14:15:46 -060069# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew57a12722008-01-15 14:15:46 -060071
TsiChungLiew57a12722008-01-15 14:15:46 -060072# define CONFIG_IPADDR 192.162.1.2
73# define CONFIG_NETMASK 255.255.255.0
74# define CONFIG_SERVERIP 192.162.1.1
75# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiew57a12722008-01-15 14:15:46 -060076
77#endif
78
79#ifdef CONFIG_CMD_USB
80# define CONFIG_USB_OHCI_NEW
81# define CONFIG_USB_STORAGE
82
83# ifndef CONFIG_CMD_PCI
84# define CONFIG_CMD_PCI
85# endif
86# define CONFIG_PCI_OHCI
87# define CONFIG_DOS_PARTITION
88
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089# undef CONFIG_SYS_USB_OHCI_BOARD_INIT
90# undef CONFIG_SYS_USB_OHCI_CPU_INIT
91# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
92# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
93# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
TsiChungLiew57a12722008-01-15 14:15:46 -060094#endif
95
96/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020097#define CONFIG_SYS_I2C
98#define CONFIG_SYS_I2C_FSL
99#define CONFIG_SYS_FSL_I2C_SPEED 80000
100#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
101#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew57a12722008-01-15 14:15:46 -0600103
104/* PCI */
105#ifdef CONFIG_CMD_PCI
106#define CONFIG_PCI 1
107#define CONFIG_PCI_PNP 1
TsiChung Liewf33fca22008-03-30 01:19:06 -0500108#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
TsiChungLiew57a12722008-01-15 14:15:46 -0600109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
TsiChungLiew57a12722008-01-15 14:15:46 -0600111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
113#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
114#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_PCI_IO_BUS 0x71000000
117#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
118#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
121#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
122#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600123#endif
124
125#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
126#define CONFIG_UDP_CHECKSUM
127
128#ifdef CONFIG_MCFFEC
TsiChungLiew57a12722008-01-15 14:15:46 -0600129# define CONFIG_IPADDR 192.162.1.2
130# define CONFIG_NETMASK 255.255.255.0
131# define CONFIG_SERVERIP 192.162.1.1
132# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiew57a12722008-01-15 14:15:46 -0600133#endif /* FEC_ENET */
134
135#define CONFIG_HOSTNAME M547xEVB
136#define CONFIG_EXTRA_ENV_SETTINGS \
137 "netdev=eth0\0" \
138 "loadaddr=10000\0" \
139 "u-boot=u-boot.bin\0" \
140 "load=tftp ${loadaddr) ${u-boot}\0" \
141 "upd=run load; run prog\0" \
142 "prog=prot off bank 1;" \
Jason Jin09933fb2011-08-19 10:10:40 +0800143 "era ff800000 ff83ffff;" \
TsiChungLiew57a12722008-01-15 14:15:46 -0600144 "cp.b ${loadaddr} ff800000 ${filesize};"\
145 "save\0" \
146 ""
147
148#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_PROMPT "-> "
150#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiew57a12722008-01-15 14:15:46 -0600151
152#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiew57a12722008-01-15 14:15:46 -0600154#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiew57a12722008-01-15 14:15:46 -0600156#endif
157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
159#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
160#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
161#define CONFIG_SYS_LOAD_ADDR 0x00010000
TsiChungLiew57a12722008-01-15 14:15:46 -0600162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
164#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
TsiChungLiew57a12722008-01-15 14:15:46 -0600165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MBAR 0xF0000000
167#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
168#define CONFIG_SYS_INTSRAMSZ 0x8000
TsiChungLiew57a12722008-01-15 14:15:46 -0600169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
TsiChungLiew57a12722008-01-15 14:15:46 -0600171
172/*
173 * Low Level Configuration Settings
174 * (address mappings, register initial values, etc.)
175 * You should know what you are doing if you make changes here.
176 */
177/*-----------------------------------------------------------------------
178 * Definitions for initial stack pointer and data area (in DPRAM)
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200181#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_CTRL 0x21
Wolfgang Denk553f0982010-10-26 13:32:32 +0200183#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
185#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200186#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiew57a12722008-01-15 14:15:46 -0600188
189/*-----------------------------------------------------------------------
190 * Start addresses for the final memory configuration
191 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew57a12722008-01-15 14:15:46 -0600193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_SDRAM_BASE 0x00000000
195#define CONFIG_SYS_SDRAM_CFG1 0x73711630
196#define CONFIG_SYS_SDRAM_CFG2 0x46770000
197#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
198#define CONFIG_SYS_SDRAM_EMOD 0x40010000
199#define CONFIG_SYS_SDRAM_MODE 0x018D0000
200#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
201#ifdef CONFIG_SYS_DRAMSZ1
202# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
TsiChungLiew57a12722008-01-15 14:15:46 -0600203#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
TsiChungLiew57a12722008-01-15 14:15:46 -0600205#endif
206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
208#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew57a12722008-01-15 14:15:46 -0600209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
211#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiew57a12722008-01-15 14:15:46 -0600212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
TsiChungLiew57a12722008-01-15 14:15:46 -0600214
Jason Jin09933fb2011-08-19 10:10:40 +0800215/* Reserve 256 kB for malloc() */
216#define CONFIG_SYS_MALLOC_LEN (256 << 10)
TsiChungLiew57a12722008-01-15 14:15:46 -0600217/*
218 * For booting Linux, the board info and command line data
219 * have to be in the first 8 MB of memory, since this is
220 * the maximum mapped by the Linux kernel during initialization ??
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChungLiew57a12722008-01-15 14:15:46 -0600223
224/*-----------------------------------------------------------------------
225 * FLASH organization
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_FLASH_CFI
228#ifdef CONFIG_SYS_FLASH_CFI
229# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200230# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
232# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
233# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
234# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
235#ifdef CONFIG_SYS_NOR1SZ
236# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
237# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
238# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
TsiChungLiew57a12722008-01-15 14:15:46 -0600239#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
241# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
TsiChungLiew57a12722008-01-15 14:15:46 -0600242#endif
243#endif
244
245/* Configuration for environment
Jason Jin09933fb2011-08-19 10:10:40 +0800246 * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
247 * First time runing may have env crc error warning if there is
248 * no correct environment on the flash.
TsiChungLiew57a12722008-01-15 14:15:46 -0600249 */
Jason Jin09933fb2011-08-19 10:10:40 +0800250#define CONFIG_ENV_OFFSET 0x40000
251#define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200252#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiew57a12722008-01-15 14:15:46 -0600253
254/*-----------------------------------------------------------------------
255 * Cache Configuration
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew57a12722008-01-15 14:15:46 -0600258
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600259#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200260 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600261#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200262 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600263#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
264 CF_CACR_IDCM)
265#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
266#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
267 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
268 CF_ACR_EN | CF_ACR_SM_ALL)
269#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
270 CF_CACR_IEC | CF_CACR_ICINVA)
271#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
272 CF_CACR_DEC | CF_CACR_DDCM_P | \
273 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
274
TsiChungLiew57a12722008-01-15 14:15:46 -0600275/*-----------------------------------------------------------------------
276 * Chipselect bank definitions
277 */
278/*
279 * CS0 - NOR Flash 1, 2, 4, or 8MB
280 * CS1 - NOR Flash
281 * CS2 - Available
282 * CS3 - Available
283 * CS4 - Available
284 * CS5 - Available
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_CS0_BASE 0xFF800000
287#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
288#define CONFIG_SYS_CS0_CTRL 0x00101980
TsiChungLiew57a12722008-01-15 14:15:46 -0600289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#ifdef CONFIG_SYS_NOR1SZ
291#define CONFIG_SYS_CS1_BASE 0xE0000000
292#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
293#define CONFIG_SYS_CS1_CTRL 0x00101D80
TsiChungLiew57a12722008-01-15 14:15:46 -0600294#endif
295
296#endif /* _M5475EVB_H */