Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 2 | /* |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 3 | * armboot - Startup Code for XScale CPU-core |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> |
| 6 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> |
| 7 | * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 8 | * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 9 | * Copyright (C) 2001 Marius Groger <mag@sysgo.de> |
| 10 | * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> |
| 11 | * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 12 | * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> |
Wolfgang Denk | 951a954 | 2006-03-06 23:18:48 +0100 | [diff] [blame] | 13 | * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 14 | * Copyright (C) 2003 Kshitij <kshitij@ti.com> |
| 15 | * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> |
| 16 | * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> |
| 17 | * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> |
| 18 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 21 | #include <asm-offsets.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 22 | #include <config.h> |
Marek Vasut | 7f4cfcf | 2011-11-05 19:26:47 +0100 | [diff] [blame] | 23 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 24 | /* |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 25 | ************************************************************************* |
| 26 | * |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 27 | * Startup Code (reset vector) |
| 28 | * |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 29 | * do important init only if we don't start from memory! |
| 30 | * setup Memory and board specific bits prior to relocation. |
| 31 | * relocate armboot to ram |
| 32 | * setup stack |
| 33 | * |
| 34 | ************************************************************************* |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 35 | */ |
| 36 | |
Albert ARIBAUD | 41623c9 | 2014-04-15 16:13:51 +0200 | [diff] [blame] | 37 | .globl reset |
Heiko Schocher | 5347f68 | 2010-09-17 13:10:46 +0200 | [diff] [blame] | 38 | |
| 39 | reset: |
| 40 | /* |
| 41 | * set the cpu to SVC32 mode |
| 42 | */ |
| 43 | mrs r0,cpsr |
| 44 | bic r0,r0,#0x1f |
| 45 | orr r0,r0,#0xd3 |
| 46 | msr cpsr,r0 |
| 47 | |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 48 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 49 | bl cpu_init_crit |
| 50 | #endif |
Heiko Schocher | 5347f68 | 2010-09-17 13:10:46 +0200 | [diff] [blame] | 51 | |
Marek Vasut | abc20ab | 2011-11-26 07:20:07 +0100 | [diff] [blame] | 52 | #ifdef CONFIG_CPU_PXA25X |
Marek Vasut | 7f4cfcf | 2011-11-05 19:26:47 +0100 | [diff] [blame] | 53 | bl lock_cache_for_stack |
| 54 | #endif |
Vasily Khoruzhick | 9ddde3e | 2016-03-20 18:37:06 -0700 | [diff] [blame] | 55 | #ifdef CONFIG_CPU_PXA27X |
| 56 | /* |
| 57 | * enable clock for SRAM |
| 58 | */ |
| 59 | ldr r0,=CKEN |
| 60 | ldr r1,[r0] |
| 61 | orr r1,r1,#(1 << 20) |
| 62 | str r1,[r0] |
| 63 | #endif |
Albert ARIBAUD | e05e5de | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 64 | bl _main |
Heiko Schocher | 5347f68 | 2010-09-17 13:10:46 +0200 | [diff] [blame] | 65 | |
| 66 | /*------------------------------------------------------------------------------*/ |
Albert ARIBAUD | e05e5de | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 67 | |
| 68 | .globl c_runtime_cpu_setup |
| 69 | c_runtime_cpu_setup: |
| 70 | |
Albert ARIBAUD | 3da0e57 | 2013-05-19 01:48:15 +0000 | [diff] [blame] | 71 | #ifdef CONFIG_CPU_PXA25X |
| 72 | /* |
| 73 | * Unlock (actually, disable) the cache now that board_init_f |
| 74 | * is done. We could do this earlier but we would need to add |
| 75 | * a new C runtime hook, whereas c_runtime_cpu_setup already |
| 76 | * exists. |
| 77 | * As this routine is just a call to cpu_init_crit, let us |
| 78 | * tail-optimize and do a simple branch here. |
| 79 | */ |
| 80 | b cpu_init_crit |
| 81 | #else |
Albert ARIBAUD | e05e5de | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 82 | bx lr |
Albert ARIBAUD | 3da0e57 | 2013-05-19 01:48:15 +0000 | [diff] [blame] | 83 | #endif |
Albert ARIBAUD | e05e5de | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 84 | |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 85 | /* |
| 86 | ************************************************************************* |
| 87 | * |
| 88 | * CPU_init_critical registers |
| 89 | * |
| 90 | * setup important registers |
| 91 | * setup memory timing |
| 92 | * |
| 93 | ************************************************************************* |
| 94 | */ |
Marek Vasut | abc20ab | 2011-11-26 07:20:07 +0100 | [diff] [blame] | 95 | #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 96 | cpu_init_crit: |
| 97 | /* |
| 98 | * flush v4 I/D caches |
| 99 | */ |
| 100 | mov r0, #0 |
| 101 | mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ |
| 102 | mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ |
Marek Vasut | 2cad92f | 2010-09-28 15:44:10 +0200 | [diff] [blame] | 103 | |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 104 | /* |
| 105 | * disable MMU stuff and caches |
| 106 | */ |
| 107 | mrc p15, 0, r0, c1, c0, 0 |
Mike Dunn | 097d86d | 2013-06-17 10:47:28 -0700 | [diff] [blame] | 108 | bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 109 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) |
Yuichiro Goto | ba10b85 | 2016-02-25 10:23:34 +0900 | [diff] [blame] | 110 | orr r0, r0, #0x00000002 @ set bit 1 (A) Align |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 111 | mcr p15, 0, r0, c1, c0, 0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 112 | |
Marek Vasut | 20f7b1b | 2011-10-31 14:12:39 +0100 | [diff] [blame] | 113 | mov pc, lr /* back to my caller */ |
Marek Vasut | abc20ab | 2011-11-26 07:20:07 +0100 | [diff] [blame] | 114 | #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 115 | |
Marek Vasut | 7f4cfcf | 2011-11-05 19:26:47 +0100 | [diff] [blame] | 116 | /* |
| 117 | * Enable MMU to use DCache as DRAM. |
| 118 | * |
| 119 | * This is useful on PXA25x and PXA26x in early bootstages, where there is no |
| 120 | * other possible memory available to hold stack. |
| 121 | */ |
Marek Vasut | abc20ab | 2011-11-26 07:20:07 +0100 | [diff] [blame] | 122 | #ifdef CONFIG_CPU_PXA25X |
Marek Vasut | 7f4cfcf | 2011-11-05 19:26:47 +0100 | [diff] [blame] | 123 | .macro CPWAIT reg |
| 124 | mrc p15, 0, \reg, c2, c0, 0 |
| 125 | mov \reg, \reg |
| 126 | sub pc, pc, #4 |
| 127 | .endm |
| 128 | lock_cache_for_stack: |
| 129 | /* Domain access -- enable for all CPs */ |
| 130 | ldr r0, =0x0000ffff |
| 131 | mcr p15, 0, r0, c3, c0, 0 |
| 132 | |
| 133 | /* Point TTBR to MMU table */ |
| 134 | ldr r0, =mmutable |
| 135 | mcr p15, 0, r0, c2, c0, 0 |
| 136 | |
| 137 | /* Kick in MMU, ICache, DCache, BTB */ |
| 138 | mrc p15, 0, r0, c1, c0, 0 |
| 139 | bic r0, #0x1b00 |
| 140 | bic r0, #0x0087 |
| 141 | orr r0, #0x1800 |
| 142 | orr r0, #0x0005 |
| 143 | mcr p15, 0, r0, c1, c0, 0 |
| 144 | CPWAIT r0 |
| 145 | |
| 146 | /* Unlock Icache, Dcache */ |
| 147 | mcr p15, 0, r0, c9, c1, 1 |
| 148 | mcr p15, 0, r0, c9, c2, 1 |
| 149 | |
| 150 | /* Flush Icache, Dcache, BTB */ |
| 151 | mcr p15, 0, r0, c7, c7, 0 |
| 152 | |
| 153 | /* Unlock I-TLB, D-TLB */ |
| 154 | mcr p15, 0, r0, c10, c4, 1 |
| 155 | mcr p15, 0, r0, c10, c8, 1 |
| 156 | |
| 157 | /* Flush TLB */ |
| 158 | mcr p15, 0, r0, c8, c7, 0 |
| 159 | |
| 160 | /* Allocate 4096 bytes of Dcache as RAM */ |
| 161 | |
| 162 | /* Drain pending loads and stores */ |
| 163 | mcr p15, 0, r0, c7, c10, 4 |
| 164 | |
| 165 | mov r4, #0x00 |
| 166 | mov r5, #0x00 |
| 167 | mov r2, #0x01 |
| 168 | mcr p15, 0, r0, c9, c2, 0 |
| 169 | CPWAIT r0 |
| 170 | |
| 171 | /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ |
| 172 | mov r0, #128 |
| 173 | ldr r1, =0xfffff000 |
| 174 | |
| 175 | alloc: |
| 176 | mcr p15, 0, r1, c7, c2, 5 |
| 177 | /* Drain pending loads and stores */ |
| 178 | mcr p15, 0, r0, c7, c10, 4 |
| 179 | strd r4, [r1], #8 |
| 180 | strd r4, [r1], #8 |
| 181 | strd r4, [r1], #8 |
| 182 | strd r4, [r1], #8 |
| 183 | subs r0, #0x01 |
| 184 | bne alloc |
| 185 | /* Drain pending loads and stores */ |
| 186 | mcr p15, 0, r0, c7, c10, 4 |
| 187 | mov r2, #0x00 |
| 188 | mcr p15, 0, r2, c9, c2, 0 |
| 189 | CPWAIT r0 |
| 190 | |
| 191 | mov pc, lr |
| 192 | |
| 193 | .section .mmutable, "a" |
| 194 | mmutable: |
| 195 | .align 14 |
| 196 | /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ |
| 197 | .set __base, 0 |
| 198 | .rept 0xfff |
| 199 | .word (__base << 20) | 0xc12 |
| 200 | .set __base, __base + 1 |
| 201 | .endr |
| 202 | |
| 203 | /* 0xfff00000 : 1:1, cached mapping */ |
| 204 | .word (0xfff << 20) | 0x1c1e |
Marek Vasut | abc20ab | 2011-11-26 07:20:07 +0100 | [diff] [blame] | 205 | #endif /* CONFIG_CPU_PXA25X */ |