blob: 89e75fb65b646ce3d2689f90e22778d8789bfdcf [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Beniamino Galvanibfcef282016-05-08 08:30:16 +02002/*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
Beniamino Galvanibfcef282016-05-08 08:30:16 +02004 */
5
6#include <common.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +09007#include <linux/libfdt.h>
Beniamino Galvanibfcef282016-05-08 08:30:16 +02008#include <linux/err.h>
9#include <asm/arch/gxbb.h>
Beniamino Galvanic7757d42016-05-08 08:30:17 +020010#include <asm/arch/sm.h>
Beniamino Galvanibfcef282016-05-08 08:30:16 +020011#include <asm/armv8/mmu.h>
12#include <asm/unaligned.h>
Neil Armstrongc7be3e52017-11-27 10:35:46 +010013#include <linux/sizes.h>
14#include <efi_loader.h>
15#include <asm/io.h>
Beniamino Galvanibfcef282016-05-08 08:30:16 +020016
17DECLARE_GLOBAL_DATA_PTR;
18
19int dram_init(void)
20{
21 const fdt64_t *val;
22 int offset;
23 int len;
24
25 offset = fdt_path_offset(gd->fdt_blob, "/memory");
26 if (offset < 0)
27 return -EINVAL;
28
29 val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
30 if (len < sizeof(*val) * 2)
31 return -EINVAL;
32
33 /* Use unaligned access since cache is still disabled */
34 gd->ram_size = get_unaligned_be64(&val[1]);
35
36 return 0;
37}
38
Neil Armstrongc7be3e52017-11-27 10:35:46 +010039phys_size_t get_effective_memsize(void)
Beniamino Galvanibfcef282016-05-08 08:30:16 +020040{
Neil Armstrongc7be3e52017-11-27 10:35:46 +010041 /* Size is reported in MiB, convert it in bytes */
42 return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK)
43 >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M;
44}
45
46static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
47{
48 int ret;
49
50 ret = fdt_add_mem_rsv(fdt, start, size);
51 if (ret)
52 printf("Could not reserve zone @ 0x%llx\n", start);
53
54 if (IS_ENABLED(CONFIG_EFI_LOADER)) {
55 efi_add_memory_map(start,
56 ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
57 EFI_RESERVED_MEMORY_TYPE, false);
58 }
59}
60
61void meson_gx_init_reserved_memory(void *fdt)
62{
63 u64 bl31_size, bl31_start;
64 u64 bl32_size, bl32_start;
65 u32 reg;
66
67 /*
68 * Get ARM Trusted Firmware reserved memory zones in :
69 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
70 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
71 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
72 */
73
74 reg = readl(GXBB_AO_SEC_GP_CFG3);
75
76 bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK)
77 >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
78 bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
79
80 bl31_start = readl(GXBB_AO_SEC_GP_CFG5);
81 bl32_start = readl(GXBB_AO_SEC_GP_CFG4);
82
83 /*
84 * Early Meson GXBB Firmware revisions did not provide the reserved
85 * memory zones in the registers, keep fixed memory zone handling.
86 */
87 if (IS_ENABLED(CONFIG_MESON_GXBB) &&
88 !reg && !bl31_start && !bl32_start) {
89 bl31_start = 0x10000000;
90 bl31_size = 0x200000;
91 }
92
93 /* Add first 16MiB reserved zone */
94 meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE);
95
96 /* Add BL31 reserved zone */
97 if (bl31_start && bl31_size)
98 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
99
100 /* Add BL32 reserved zone */
101 if (bl32_start && bl32_size)
102 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200103}
104
105void reset_cpu(ulong addr)
106{
Alexander Graf51bfb5b2016-08-16 21:08:46 +0200107 psci_system_reset();
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200108}
109
110static struct mm_region gxbb_mem_map[] = {
111 {
York Suncd4b0c52016-06-24 16:46:22 -0700112 .virt = 0x0UL,
113 .phys = 0x0UL,
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200114 .size = 0x80000000UL,
115 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
116 PTE_BLOCK_INNER_SHARE
117 }, {
York Suncd4b0c52016-06-24 16:46:22 -0700118 .virt = 0x80000000UL,
119 .phys = 0x80000000UL,
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200120 .size = 0x80000000UL,
121 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
122 PTE_BLOCK_NON_SHARE |
123 PTE_BLOCK_PXN | PTE_BLOCK_UXN
124 }, {
125 /* List terminator */
126 0,
127 }
128};
129
130struct mm_region *mem_map = gxbb_mem_map;