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stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_VOH405 1 /* ...on a VOH405 board */
stroese13fdf8a2003-09-12 08:55:18 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000042
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000044
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000049#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000050
stroesea20b27a2004-12-16 18:05:42 +000051#define CONFIG_PREBOOT /* enable preboot variable */
52
stroese13fdf8a2003-09-12 08:55:18 +000053#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
54
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +010055#define CONFIG_NET_MULTI 1
56#undef CONFIG_HAS_ETH1
57
stroese13fdf8a2003-09-12 08:55:18 +000058#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000059#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000060#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +010061#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
stroesea20b27a2004-12-16 18:05:42 +000062
63#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroese13fdf8a2003-09-12 08:55:18 +000064
Jon Loeligera5562902007-07-08 15:31:57 -050065
66/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050067 * BOOTP options
68 */
69#define CONFIG_BOOTP_BOOTFILESIZE
70#define CONFIG_BOOTP_BOOTPATH
71#define CONFIG_BOOTP_GATEWAY
72#define CONFIG_BOOTP_HOSTNAME
73
74
75/*
Jon Loeligera5562902007-07-08 15:31:57 -050076 * Command line configuration.
77 */
78#include <config_cmd_default.h>
79
80#define CONFIG_CMD_DHCP
81#define CONFIG_CMD_PCI
82#define CONFIG_CMD_IRQ
83#define CONFIG_CMD_IDE
84#define CONFIG_CMD_FAT
85#define CONFIG_CMD_ELF
86#define CONFIG_CMD_NAND
87#define CONFIG_CMD_DATE
88#define CONFIG_CMD_I2C
89#define CONFIG_CMD_MII
90#define CONFIG_CMD_PING
91#define CONFIG_CMD_EEPROM
92
stroese13fdf8a2003-09-12 08:55:18 +000093
94#define CONFIG_MAC_PARTITION
95#define CONFIG_DOS_PARTITION
96
stroesea20b27a2004-12-16 18:05:42 +000097#define CONFIG_SUPPORT_VFAT
98
wdenkc837dcb2004-01-20 23:12:12 +000099#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +0000100
wdenkc837dcb2004-01-20 23:12:12 +0000101#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
102#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000103
wdenkc837dcb2004-01-20 23:12:12 +0000104#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +0000105
106/*
107 * Miscellaneous configurable options
108 */
109#define CFG_LONGHELP /* undef to save memory */
110#define CFG_PROMPT "=> " /* Monitor Command Prompt */
111
112#undef CFG_HUSH_PARSER /* use "hush" command parser */
113#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +0000114#define CFG_PROMPT_HUSH_PS2 "> "
stroese13fdf8a2003-09-12 08:55:18 +0000115#endif
116
Jon Loeligera5562902007-07-08 15:31:57 -0500117#if defined(CONFIG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000118#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000119#else
wdenkc837dcb2004-01-20 23:12:12 +0000120#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000121#endif
122#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
123#define CFG_MAXARGS 16 /* max number of command args */
124#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
125
wdenkc837dcb2004-01-20 23:12:12 +0000126#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +0000127
wdenkc837dcb2004-01-20 23:12:12 +0000128#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +0000129
stroesea20b27a2004-12-16 18:05:42 +0000130#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
131
stroese13fdf8a2003-09-12 08:55:18 +0000132#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
133#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
134
stroesea20b27a2004-12-16 18:05:42 +0000135#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
136#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
137#define CFG_BASE_BAUD 691200
138#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
stroese13fdf8a2003-09-12 08:55:18 +0000139
140/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000141#define CFG_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000142 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
143 57600, 115200, 230400, 460800, 921600 }
144
145#define CFG_LOAD_ADDR 0x100000 /* default load address */
146#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
147
wdenkc837dcb2004-01-20 23:12:12 +0000148#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese13fdf8a2003-09-12 08:55:18 +0000149
150#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
151
wdenkc837dcb2004-01-20 23:12:12 +0000152#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000153
wdenkc837dcb2004-01-20 23:12:12 +0000154#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000155
156/*-----------------------------------------------------------------------
157 * NAND-FLASH stuff
158 *-----------------------------------------------------------------------
159 */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200160#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
161#define NAND_MAX_CHIPS 1
162#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
163#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100164
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200165#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
166#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
167#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
168#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroese13fdf8a2003-09-12 08:55:18 +0000169
Matthias Fuchsc750d2e2007-09-12 12:36:53 +0200170#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
171#define CFG_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000172
stroese13fdf8a2003-09-12 08:55:18 +0000173/*-----------------------------------------------------------------------
174 * PCI stuff
175 *-----------------------------------------------------------------------
176 */
stroesea20b27a2004-12-16 18:05:42 +0000177#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
178#define PCI_HOST_FORCE 1 /* configure as pci host */
179#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000180
stroesea20b27a2004-12-16 18:05:42 +0000181#define CONFIG_PCI /* include pci support */
182#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
183#define CONFIG_PCI_PNP /* do pci plug-and-play */
184 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000185
stroesea20b27a2004-12-16 18:05:42 +0000186#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000187
stroesea20b27a2004-12-16 18:05:42 +0000188#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
189
190#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
191#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
192#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
193#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
194#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
195#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
196#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
197#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
198#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000199
200/*-----------------------------------------------------------------------
201 * IDE/ATA stuff
202 *-----------------------------------------------------------------------
203 */
wdenkc837dcb2004-01-20 23:12:12 +0000204#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
205#undef CONFIG_IDE_LED /* no led for ide supported */
stroese13fdf8a2003-09-12 08:55:18 +0000206#define CONFIG_IDE_RESET 1 /* reset for ide supported */
207
wdenkc837dcb2004-01-20 23:12:12 +0000208#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
209#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
stroese13fdf8a2003-09-12 08:55:18 +0000210
wdenkc837dcb2004-01-20 23:12:12 +0000211#define CFG_ATA_BASE_ADDR 0xF0100000
212#define CFG_ATA_IDE0_OFFSET 0x0000
213#define CFG_ATA_IDE1_OFFSET 0x0010
stroese13fdf8a2003-09-12 08:55:18 +0000214
215#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
wdenkc837dcb2004-01-20 23:12:12 +0000216#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
stroese13fdf8a2003-09-12 08:55:18 +0000217#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
218
219/*
220 * For booting Linux, the board info and command line data
221 * have to be in the first 8 MB of memory, since this is
222 * the maximum mapped by the Linux kernel during initialization.
223 */
224#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
225/*-----------------------------------------------------------------------
226 * FLASH organization
227 */
228#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
229
230#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
231#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
232
233#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
234#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
235
wdenkc837dcb2004-01-20 23:12:12 +0000236#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
237#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
238#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000239/*
240 * The following defines are added for buggy IOP480 byte interface.
241 * All other boards should use the standard values (CPCI405 etc.)
242 */
wdenkc837dcb2004-01-20 23:12:12 +0000243#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
244#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
245#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000246
wdenkc837dcb2004-01-20 23:12:12 +0000247#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese13fdf8a2003-09-12 08:55:18 +0000248
stroese13fdf8a2003-09-12 08:55:18 +0000249/*-----------------------------------------------------------------------
250 * Start addresses for the final memory configuration
251 * (Set up by the startup code)
252 * Please note that CFG_SDRAM_BASE _must_ start at 0
253 */
254#define CFG_SDRAM_BASE 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000255#define CFG_FLASH_BASE 0xFFF80000
stroese13fdf8a2003-09-12 08:55:18 +0000256#define CFG_MONITOR_BASE TEXT_BASE
stroesea20b27a2004-12-16 18:05:42 +0000257#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
258#define CFG_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
stroese13fdf8a2003-09-12 08:55:18 +0000259
260#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
261# define CFG_RAMBOOT 1
262#else
263# undef CFG_RAMBOOT
264#endif
265
266/*-----------------------------------------------------------------------
267 * Environment Variable setup
268 */
wdenkc837dcb2004-01-20 23:12:12 +0000269#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
270#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
271#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroese13fdf8a2003-09-12 08:55:18 +0000272 /* total size of a CAT24WC16 is 2048 bytes */
273
274#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
wdenkc837dcb2004-01-20 23:12:12 +0000275#define CFG_NVRAM_SIZE 242 /* NVRAM size */
stroese13fdf8a2003-09-12 08:55:18 +0000276
277/*-----------------------------------------------------------------------
278 * I2C EEPROM (CAT24WC16) for environment
279 */
280#define CONFIG_HARD_I2C /* I2c with hardware support */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100281#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
stroese13fdf8a2003-09-12 08:55:18 +0000282#define CFG_I2C_SLAVE 0x7F
283
284#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100285#define CFG_EEPROM_WREN 1
286
stroese13fdf8a2003-09-12 08:55:18 +0000287/* CAT24WC32/64... */
wdenkc837dcb2004-01-20 23:12:12 +0000288#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
289/* mask of address bits that overflow into the "EEPROM chip address" */
stroese13fdf8a2003-09-12 08:55:18 +0000290#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
291#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
292 /* 32 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000293 /* last 5 bits of the address */
stroese13fdf8a2003-09-12 08:55:18 +0000294#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
295#define CFG_EEPROM_PAGE_WRITE_ENABLE
296
297/*-----------------------------------------------------------------------
stroese13fdf8a2003-09-12 08:55:18 +0000298 * External Bus Controller (EBC) Setup
299 */
300
wdenkc837dcb2004-01-20 23:12:12 +0000301#define CAN_BA 0xF0000000 /* CAN Base Address */
302#define DUART0_BA 0xF0000400 /* DUART Base Address */
303#define DUART1_BA 0xF0000408 /* DUART Base Address */
304#define RTC_BA 0xF0000500 /* RTC Base Address */
305#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
306#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000307
wdenkc837dcb2004-01-20 23:12:12 +0000308/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
309#define CFG_EBC_PB0AP 0x92015480
310/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
311#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000312
wdenkc837dcb2004-01-20 23:12:12 +0000313/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
314#define CFG_EBC_PB1AP 0x92015480
315#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000316
wdenkc837dcb2004-01-20 23:12:12 +0000317/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
318#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
319#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000320
wdenkc837dcb2004-01-20 23:12:12 +0000321/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
322#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
323#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000324
wdenkc837dcb2004-01-20 23:12:12 +0000325/* Memory Bank 4 (Epson VGA) initialization */
326#define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
327#define CFG_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000328
329/*-----------------------------------------------------------------------
stroesea20b27a2004-12-16 18:05:42 +0000330 * LCD Setup
331 */
332
333#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
334#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
335#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
336#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
337
Stefan Roesec29ab9d2005-10-08 10:19:07 +0200338#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
stroesea20b27a2004-12-16 18:05:42 +0000339
340/*-----------------------------------------------------------------------
stroese13fdf8a2003-09-12 08:55:18 +0000341 * FPGA stuff
342 */
343
wdenkc837dcb2004-01-20 23:12:12 +0000344#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000345
346/* FPGA internal regs */
wdenkc837dcb2004-01-20 23:12:12 +0000347#define CFG_FPGA_CTRL 0x000
stroese13fdf8a2003-09-12 08:55:18 +0000348
349/* FPGA Control Reg */
wdenkc837dcb2004-01-20 23:12:12 +0000350#define CFG_FPGA_CTRL_CF_RESET 0x0001
351#define CFG_FPGA_CTRL_WDI 0x0002
stroese13fdf8a2003-09-12 08:55:18 +0000352#define CFG_FPGA_CTRL_PS2_RESET 0x0020
353
wdenkc837dcb2004-01-20 23:12:12 +0000354#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
355#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroese13fdf8a2003-09-12 08:55:18 +0000356
357/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000358#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
359#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
360#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
361#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
362#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000363
364/*-----------------------------------------------------------------------
365 * Definitions for initial stack pointer and data area (in data cache)
366 */
367/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
wdenkc837dcb2004-01-20 23:12:12 +0000368#define CFG_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000369
370/* On Chip Memory location */
371#define CFG_OCM_DATA_ADDR 0xF8000000
372#define CFG_OCM_DATA_SIZE 0x1000
373#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
374#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
375
376#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
377#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000378#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000379
380/*-----------------------------------------------------------------------
381 * Definitions for GPIO setup (PPC405EP specific)
382 *
wdenkc837dcb2004-01-20 23:12:12 +0000383 * GPIO0[0] - External Bus Controller BLAST output
384 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000385 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
386 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
387 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
388 * GPIO0[24-27] - UART0 control signal inputs/outputs
389 * GPIO0[28-29] - UART1 data signal input/output
stroesea20b27a2004-12-16 18:05:42 +0000390 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000391 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100392#define CFG_GPIO0_OSRH 0x00000550
wdenkc837dcb2004-01-20 23:12:12 +0000393#define CFG_GPIO0_OSRL 0x00000110
394#define CFG_GPIO0_ISR1H 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000395#define CFG_GPIO0_ISR1L 0x15555440
wdenkc837dcb2004-01-20 23:12:12 +0000396#define CFG_GPIO0_TSRH 0x00000000
397#define CFG_GPIO0_TSRL 0x00000000
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100398#define CFG_GPIO0_TCR 0x777E0017
stroese13fdf8a2003-09-12 08:55:18 +0000399
wdenkc837dcb2004-01-20 23:12:12 +0000400#define CFG_DUART_RST (0x80000000 >> 14)
stroesea20b27a2004-12-16 18:05:42 +0000401#define CFG_LCD_ENDIAN (0x80000000 >> 7)
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100402#define CFG_IIC_ON (0x80000000 >> 8)
stroesea20b27a2004-12-16 18:05:42 +0000403#define CFG_LCD0_RST (0x80000000 >> 30)
404#define CFG_LCD1_RST (0x80000000 >> 31)
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100405#define CFG_EEPROM_WP (0x80000000 >> 0)
stroese13fdf8a2003-09-12 08:55:18 +0000406
407/*
408 * Internal Definitions
409 *
410 * Boot Flags
411 */
412#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
413#define BOOTFLAG_WARM 0x02 /* Software reboot */
414
415/*
416 * Default speed selection (cpu_plb_opb_ebc) in mhz.
417 * This value will be set if iic boot eprom is disabled.
418 */
419#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000420#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
421#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000422#endif
423#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000424#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
425#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000426#endif
427#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000428#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
429#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000430#endif
431
432#endif /* __CONFIG_H */