blob: c312b7781dd7ba73196c2e6c309453f74aeb6547 [file] [log] [blame]
wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
6 *
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
9 *
wdenk04a85b32004-04-15 18:22:41 +000010 * (C) Copyright 2003-2004 Arabella Software Ltd.
wdenkcceb8712003-06-23 18:12:28 +000011 * Yuli Barcohen <yuli@arabellasw.com>
wdenk2535d602003-07-17 23:16:40 +000012 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
wdenkef5a9672003-12-07 00:46:27 +000013 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
wdenk04a85b32004-04-15 18:22:41 +000014 * Ported to MPC8272ADS board.
wdenkcceb8712003-06-23 18:12:28 +000015 *
Wolfgang Denk716c1dc2005-09-25 18:49:35 +020016 * Copyright (c) 2005 MontaVista Software, Inc.
Wolfgang Denk1972dc02005-09-25 16:27:55 +020017 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI bridge on MPC8272ADS
19 *
Scott Woodc73ed272009-04-02 18:20:43 -050020 * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
21 *
wdenke2211742002-11-02 23:30:20 +000022 * See file CREDITS for list of people who contributed to this
23 * project.
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License as
27 * published by the Free Software Foundation; either version 2 of
28 * the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 * MA 02111-1307 USA
39 */
40
wdenke2211742002-11-02 23:30:20 +000041#ifndef __CONFIG_H
42#define __CONFIG_H
43
44/*
45 * High Level Configuration Options
46 * (easy to change)
47 */
48
wdenk04a85b32004-04-15 18:22:41 +000049#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
wdenke2211742002-11-02 23:30:20 +000050
Wolfgang Denk2ae18242010-10-06 09:05:45 +020051#ifndef CONFIG_SYS_TEXT_BASE
52#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
53#endif
54
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050055#define CONFIG_CPM2 1 /* Has a CPM2 */
56
wdenk901787d2005-04-03 23:22:21 +000057/*
58 * Figure out if we are booting low via flash HRCW or high via the BCSR.
59 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +020060#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061# define CONFIG_SYS_LOWBOOT 1
wdenk901787d2005-04-03 23:22:21 +000062#endif
63
wdenk2535d602003-07-17 23:16:40 +000064/* ADS flavours */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
66#define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
67#define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
68#define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
wdenk2535d602003-07-17 23:16:40 +000069
70#ifndef CONFIG_ADSTYPE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
wdenk2535d602003-07-17 23:16:40 +000072#endif /* CONFIG_ADSTYPE */
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
wdenk04a85b32004-04-15 18:22:41 +000075#define CONFIG_MPC8272 1
Scott Wood8701ece2009-04-03 15:26:45 -050076#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
77/*
78 * Actually MPC8275, but the code is littered with ifdefs that
79 * apply to both, or which use this ifdef to assume board-specific
80 * details. :-(
81 */
82#define CONFIG_MPC8272 1
wdenk04a85b32004-04-15 18:22:41 +000083#else
84#define CONFIG_MPC8260 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
wdenk04a85b32004-04-15 18:22:41 +000086
wdenkc837dcb2004-01-20 23:12:12 +000087#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050088#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenke2211742002-11-02 23:30:20 +000089
90/* allow serial and ethaddr to be overwritten */
91#define CONFIG_ENV_OVERWRITE
92
93/*
94 * select serial console configuration
95 *
96 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
97 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
98 * for SCC).
99 *
100 * if CONFIG_CONS_NONE is defined, then the serial console routines must
101 * defined elsewhere (for example, on the cogent platform, there are serial
102 * ports on the motherboard which are used for the serial console - see
103 * cogent/cma101/serial.[ch]).
104 */
105#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
106#define CONFIG_CONS_ON_SCC /* define if console on SCC */
107#undef CONFIG_CONS_NONE /* define if console on something else */
108#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
109
110/*
111 * select ethernet configuration
112 *
113 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
114 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
115 * for FCC)
116 *
117 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500118 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +0000119 */
120#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
121#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
122#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk48b42612003-06-19 23:01:32 +0000123
124#ifdef CONFIG_ETHER_ON_FCC
125
126#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
wdenke2211742002-11-02 23:30:20 +0000127
wdenk04a85b32004-04-15 18:22:41 +0000128#if CONFIG_ETHER_INDEX == 1
129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130# define CONFIG_SYS_PHY_ADDR 0
Mike Frysingerd4590da2011-10-17 05:38:58 +0000131# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
132# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
wdenk04a85b32004-04-15 18:22:41 +0000133
134#elif CONFIG_ETHER_INDEX == 2
135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
137# define CONFIG_SYS_PHY_ADDR 3
Mike Frysingerd4590da2011-10-17 05:38:58 +0000138# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
wdenk04a85b32004-04-15 18:22:41 +0000139#else /* RxCLK is CLK13, TxCLK is CLK14 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140# define CONFIG_SYS_PHY_ADDR 0
Mike Frysingerd4590da2011-10-17 05:38:58 +0000141# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
wdenk04a85b32004-04-15 18:22:41 +0000143
Mike Frysingerd4590da2011-10-17 05:38:58 +0000144# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
wdenke2211742002-11-02 23:30:20 +0000145
146#endif /* CONFIG_ETHER_INDEX */
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
149#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
wdenk04a85b32004-04-15 18:22:41 +0000150
wdenk48b42612003-06-19 23:01:32 +0000151#define CONFIG_MII /* MII PHY management */
152#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
153/*
154 * GPIO pins used for bit-banged MII communications
155 */
156#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200157#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
158 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
159#define MDC_DECLARE MDIO_DECLARE
wdenk48b42612003-06-19 23:01:32 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
162#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
163#define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
wdenk04a85b32004-04-15 18:22:41 +0000164#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
166#define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
167#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
wdenk48b42612003-06-19 23:01:32 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
170#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
171#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
wdenk04a85b32004-04-15 18:22:41 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
174 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
wdenk04a85b32004-04-15 18:22:41 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
177 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
wdenk48b42612003-06-19 23:01:32 +0000178
179#define MIIDELAY udelay(1)
180
181#endif /* CONFIG_ETHER_ON_FCC */
182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
wdenk04a85b32004-04-15 18:22:41 +0000184#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
wdenk2535d602003-07-17 23:16:40 +0000185#else
wdenke2211742002-11-02 23:30:20 +0000186#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
188#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenke2211742002-11-02 23:30:20 +0000189
wdenkdb2f721f2003-03-06 00:58:30 +0000190#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200191#define CONFIG_SPD_ADDR 0x50
wdenkdb2f721f2003-03-06 00:58:30 +0000192#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
wdenke2211742002-11-02 23:30:20 +0000194
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200195/*PCI*/
Scott Wood8701ece2009-04-03 15:26:45 -0500196#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200197#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000198#define CONFIG_PCI_INDIRECT_BRIDGE
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200199#define CONFIG_PCI_PNP
200#define CONFIG_PCI_BOOTDELAY 0
201#define CONFIG_PCI_SCAN_SHOW
202#endif
203
wdenkdb2f721f2003-03-06 00:58:30 +0000204#ifndef CONFIG_SDRAM_PBI
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200205#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
wdenkdb2f721f2003-03-06 00:58:30 +0000206#endif
207
208#ifndef CONFIG_8260_CLKIN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
wdenk2535d602003-07-17 23:16:40 +0000210#define CONFIG_8260_CLKIN 100000000 /* in Hz */
211#else
wdenkef5a9672003-12-07 00:46:27 +0000212#define CONFIG_8260_CLKIN 66000000 /* in Hz */
wdenkdb2f721f2003-03-06 00:58:30 +0000213#endif
wdenk2535d602003-07-17 23:16:40 +0000214#endif
215
wdenke1599e82004-10-10 23:27:33 +0000216#define CONFIG_BAUDRATE 115200
wdenke2211742002-11-02 23:30:20 +0000217
Matvejchikov Ilya0e6989b2008-07-06 13:57:00 +0400218#define CONFIG_OF_LIBFDT 1
219#define CONFIG_OF_BOARD_SETUP 1
220#if defined(CONFIG_OF_LIBFDT)
Matvejchikov Ilya0e6989b2008-07-06 13:57:00 +0400221#define OF_TBCLK (bd->bi_busfreq / 4)
222#endif
223
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500224/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500225 * BOOTP options
226 */
227#define CONFIG_BOOTP_BOOTFILESIZE
228#define CONFIG_BOOTP_BOOTPATH
229#define CONFIG_BOOTP_GATEWAY
230#define CONFIG_BOOTP_HOSTNAME
231
232
233/*
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500234 * Command line configuration.
235 */
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200236#include <config_cmd_default.h>
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500237
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200238#define CONFIG_CMD_ASKENV
239#define CONFIG_CMD_CACHE
240#define CONFIG_CMD_CDP
241#define CONFIG_CMD_DHCP
242#define CONFIG_CMD_DIAG
243#define CONFIG_CMD_I2C
244#define CONFIG_CMD_IMMAP
245#define CONFIG_CMD_IRQ
246#define CONFIG_CMD_JFFS2
247#define CONFIG_CMD_MII
248#define CONFIG_CMD_PCI
249#define CONFIG_CMD_PING
250#define CONFIG_CMD_PORTIO
251#define CONFIG_CMD_REGINFO
252#define CONFIG_CMD_SAVES
253#define CONFIG_CMD_SDRAM
254
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500255#undef CONFIG_CMD_XIMG
wdenk2535d602003-07-17 23:16:40 +0000256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500258 #undef CONFIG_CMD_SDRAM
259 #undef CONFIG_CMD_I2C
260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500262 #undef CONFIG_CMD_SDRAM
263 #undef CONFIG_CMD_I2C
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500264
wdenk2535d602003-07-17 23:16:40 +0000265#else
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500266 #undef CONFIG_CMD_PCI
267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
wdenke2211742002-11-02 23:30:20 +0000269
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500270
wdenk04a85b32004-04-15 18:22:41 +0000271#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
272#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
273#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
wdenke2211742002-11-02 23:30:20 +0000274
Jon Loeliger8353e132007-07-08 14:14:17 -0500275#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000276#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
277#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
278#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
279#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
280#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
281#endif
282
wdenkef5a9672003-12-07 00:46:27 +0000283#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200284#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
wdenke2211742002-11-02 23:30:20 +0000285
286/*
287 * Miscellaneous configurable options
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_LONGHELP /* undef to save memory */
291#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger8353e132007-07-08 14:14:17 -0500292#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000294#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000296#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
298#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
299#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
302#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenke2211742002-11-02 23:30:20 +0000309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_FLASH_BASE 0xff800000
311#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
312#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
313#define CONFIG_SYS_FLASH_SIZE 8
314#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
315#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
316#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
317#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
318#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
wdenk8564acf2003-07-14 22:13:32 +0000319
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200320/*
321 * JFFS2 partitions
322 *
323 * Note: fake mtd_id used, no linux mtd map file
324 */
325#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
326#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
wdenke2211742002-11-02 23:30:20 +0000328
329/* this is stuff came out of the Motorola docs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#ifndef CONFIG_SYS_LOWBOOT
331#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
wdenk901787d2005-04-03 23:22:21 +0000332#endif
wdenke2211742002-11-02 23:30:20 +0000333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_IMMR 0xF0000000
335#define CONFIG_SYS_BCSR 0xF4500000
Scott Wood8701ece2009-04-03 15:26:45 -0500336#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_PCI_INT 0xF8200000
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200338#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_SDRAM_BASE 0x00000000
340#define CONFIG_SYS_LSDRAM_BASE 0xFD000000
wdenke2211742002-11-02 23:30:20 +0000341
342#define RS232EN_1 0x02000002
343#define RS232EN_2 0x01000001
wdenk2535d602003-07-17 23:16:40 +0000344#define FETHIEN1 0x08000008
345#define FETH1_RST 0x04000004
wdenk04a85b32004-04-15 18:22:41 +0000346#define FETHIEN2 0x10000000
wdenk2535d602003-07-17 23:16:40 +0000347#define FETH2_RST 0x08000000
wdenk326428c2003-08-31 18:37:54 +0000348#define BCSR_PCI_MODE 0x01000000
wdenke2211742002-11-02 23:30:20 +0000349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200351#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200352#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#ifdef CONFIG_SYS_LOWBOOT
wdenk901787d2005-04-03 23:22:21 +0000356/* PQ2FADS flash HRCW = 0x0EB4B645 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
wdenk901787d2005-04-03 23:22:21 +0000358 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
359 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
360 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
361 )
362#else
363/* PQ2FADS BCSR HRCW = 0x0CB23645 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
wdenke2211742002-11-02 23:30:20 +0000365 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
366 ( HRCW_BMS | HRCW_APPC10 ) |\
367 ( HRCW_MODCK_H0101 ) \
368 )
wdenk901787d2005-04-03 23:22:21 +0000369#endif
wdenke2211742002-11-02 23:30:20 +0000370/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_HRCW_SLAVE1 0
372#define CONFIG_SYS_HRCW_SLAVE2 0
373#define CONFIG_SYS_HRCW_SLAVE3 0
374#define CONFIG_SYS_HRCW_SLAVE4 0
375#define CONFIG_SYS_HRCW_SLAVE5 0
376#define CONFIG_SYS_HRCW_SLAVE6 0
377#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000378
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200379#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Peter Tyserd98b0522010-10-14 23:33:24 -0500380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
382# define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000383#endif
384
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
386#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000387
wdenkef5a9672003-12-07 00:46:27 +0000388#ifdef CONFIG_BZIP2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
wdenkef5a9672003-12-07 00:46:27 +0000390#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
wdenkef5a9672003-12-07 00:46:27 +0000392#endif /* CONFIG_BZIP2 */
393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200395# define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200396# define CONFIG_ENV_SECT_SIZE 0x40000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
wdenke2211742002-11-02 23:30:20 +0000398#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200399# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200401# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#endif /* CONFIG_SYS_RAMBOOT */
wdenke2211742002-11-02 23:30:20 +0000403
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500405#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000407#endif
408
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_HID0_INIT 0
410#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
wdenke2211742002-11-02 23:30:20 +0000411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000413
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_SYPCR 0xFFFFFFC3
415#define CONFIG_SYS_BCR 0x100C0000
416#define CONFIG_SYS_SIUMCR 0x0A200000
417#define CONFIG_SYS_SCCR SCCR_DFBRG01
418#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
419#define CONFIG_SYS_OR0_PRELIM 0xFF800876
420#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
421#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
wdenke2211742002-11-02 23:30:20 +0000422
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200423/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
424
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
426#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
427#define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
Scott Wood8701ece2009-04-03 15:26:45 -0500428#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
429#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
430#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200431#endif
432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_RMR RMR_CSRE
434#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
435#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
436#define CONFIG_SYS_RCCR 0
wdenk2535d602003-07-17 23:16:40 +0000437
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
439#undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
440#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
wdenk326428c2003-08-31 18:37:54 +0000441
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
443#define CONFIG_SYS_OR2 0xFE002EC0
444#define CONFIG_SYS_PSDMR 0x824B36A3
445#define CONFIG_SYS_PSRT 0x13
446#define CONFIG_SYS_LSDMR 0x828737A3
447#define CONFIG_SYS_LSRT 0x13
448#define CONFIG_SYS_MPTPR 0x2800
449#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
450#define CONFIG_SYS_OR2 0xFC002CC0
451#define CONFIG_SYS_PSDMR 0x834E24A3
452#define CONFIG_SYS_PSRT 0x13
453#define CONFIG_SYS_MPTPR 0x2800
wdenk2535d602003-07-17 23:16:40 +0000454#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_OR2 0xFF000CA0
456#define CONFIG_SYS_PSDMR 0x016EB452
457#define CONFIG_SYS_PSRT 0x21
458#define CONFIG_SYS_LSDMR 0x0086A522
459#define CONFIG_SYS_LSRT 0x21
460#define CONFIG_SYS_MPTPR 0x1900
461#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
wdenke2211742002-11-02 23:30:20 +0000462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_RESET_ADDRESS 0x04400000
wdenke2211742002-11-02 23:30:20 +0000464
Scott Wood8701ece2009-04-03 15:26:45 -0500465#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200466
467/* PCI Memory map (if different from default map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
469#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
470#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200471 PICMR_PREFETCH_EN)
472
473/*
474 * These are the windows that allow the CPU to access PCI address space.
475 * All three PCI master windows, which allow the CPU to access PCI
476 * prefetch, non prefetch, and IO space (see below), must all fit within
477 * these windows.
478 */
479
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200480/*
481 * Master window that allows the CPU to access PCI Memory (prefetch).
482 * This window will be setup with the second set of Outbound ATU registers
483 * in the bridge.
484 */
485
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
487#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
488#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
489#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
490#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200491
492/*
493 * Master window that allows the CPU to access PCI Memory (non-prefetch).
494 * This window will be setup with the second set of Outbound ATU registers
495 * in the bridge.
496 */
497
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
499#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
500#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
501#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
502#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200503
504/*
505 * Master window that allows the CPU to access PCI IO space.
506 * This window will be setup with the first set of Outbound ATU registers
507 * in the bridge.
508 */
509
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
511#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
512#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
513#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
514#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200515
516
517/* PCIBR0 - for PCI IO*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
519#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200520/* PCIBR1 - prefetch and non-prefetch regions joined together */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
522#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200523
524#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
525
Scott Wood42f9ebf2009-04-03 15:24:40 -0500526#define CONFIG_HAS_ETH0
527
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200529#define CONFIG_HAS_ETH1
Wolfgang Denkc2d0ab42005-09-26 00:53:02 +0200530#endif
531
Scott Woodc73ed272009-04-02 18:20:43 -0500532#define CONFIG_NETDEV eth0
533#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
534
Scott Woodc73ed272009-04-02 18:20:43 -0500535#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200536 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
Scott Woodc73ed272009-04-02 18:20:43 -0500537 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200538 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
539 " +$filesize; " \
540 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
541 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
542 " $filesize; " \
543 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
544 " +$filesize; " \
545 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
546 " $filesize\0" \
Scott Woodc73ed272009-04-02 18:20:43 -0500547 "fdtaddr=400000\0" \
548 "console=ttyCPM0\0" \
549 "setbootargs=setenv bootargs " \
550 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
551 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
552 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
553 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
554
555#define CONFIG_NFSBOOTCOMMAND \
556 "setenv rootdev /dev/nfs;" \
557 "run setipargs;" \
558 "tftp $loadaddr $bootfile;" \
559 "tftp $fdtaddr $fdtfile;" \
560 "bootm $loadaddr - $fdtaddr"
561
562#define CONFIG_RAMBOOTCOMMAND \
563 "setenv rootdev /dev/ram;" \
564 "run setbootargs;" \
565 "tftp $ramdiskaddr $ramdiskfile;" \
566 "tftp $loadaddr $bootfile;" \
567 "tftp $fdtaddr $fdtfile;" \
568 "bootm $loadaddr $ramdiskaddr $fdtaddr"
569
wdenke2211742002-11-02 23:30:20 +0000570#endif /* __CONFIG_H */