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wdenkdb2f721f2003-03-06 00:58:30 +00001/*
2 * (C) Copyright 2001
3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
6 *
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
wdenk7a8e9bed2003-05-31 18:35:21 +000030 * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
31 */
32
33/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020034 !! !!
wdenk7a8e9bed2003-05-31 18:35:21 +000035 !! This configuration requires JP3 to be in position 1-2 to work !!
Wolfgang Denk14d0a022010-10-07 21:51:12 +020036 !! To make it work for the default, the CONFIG_SYS_TEXT_BASE define in !!
wdenk7a8e9bed2003-05-31 18:35:21 +000037 !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
38 !! 0xfff00000 !!
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020040 !! !!
wdenk8bde7f72003-06-27 21:31:46 +000041 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
wdenkdb2f721f2003-03-06 00:58:30 +000042 */
43
44#ifndef __CONFIG_H
45#define __CONFIG_H
46
47/*
48 * High Level Configuration Options
49 * (easy to change)
50 */
51
wdenkc837dcb2004-01-20 23:12:12 +000052#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
53#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050054#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkdb2f721f2003-03-06 00:58:30 +000055
Wolfgang Denk2ae18242010-10-06 09:05:45 +020056#define CONFIG_SYS_TEXT_BASE 0xfe000000
57
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050059#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenkdb2f721f2003-03-06 00:58:30 +000060
61/* allow serial and ethaddr to be overwritten */
62#define CONFIG_ENV_OVERWRITE
63
64/*
65 * select serial console configuration
66 *
67 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
68 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
69 * for SCC).
70 *
71 * if CONFIG_CONS_NONE is defined, then the serial console routines must
72 * defined elsewhere (for example, on the cogent platform, there are serial
73 * ports on the motherboard which are used for the serial console - see
74 * cogent/cma101/serial.[ch]).
75 */
76#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
77#define CONFIG_CONS_ON_SCC /* define if console on SCC */
78#undef CONFIG_CONS_NONE /* define if console on something else */
79#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
80
81/*
82 * select ethernet configuration
83 *
84 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
85 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
86 * for FCC)
87 *
88 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050089 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkdb2f721f2003-03-06 00:58:30 +000090 */
91#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
92#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
93#undef CONFIG_ETHER_NONE /* define if ether on something else */
94#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk5d232d02003-05-22 22:52:13 +000095#define CONFIG_MII /* MII PHY management */
96#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
97/*
98 * Port pins used for bit-banged MII communictions (if applicable).
99 */
100#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200101#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
102 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
103#define MDC_DECLARE MDIO_DECLARE
104
wdenk5d232d02003-05-22 22:52:13 +0000105#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
106#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
107#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
108
109#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
110 else iop->pdat &= ~0x00400000
111
112#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
113 else iop->pdat &= ~0x00200000
114
115#define MIIDELAY udelay(1)
wdenkdb2f721f2003-03-06 00:58:30 +0000116
117#if (CONFIG_ETHER_INDEX == 2)
118
119/*
120 * - Rx-CLK is CLK13
121 * - Tx-CLK is CLK14
122 * - Select bus for bd/buffers (see 28-13)
123 * - Half duplex
124 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000125# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
126# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127# define CONFIG_SYS_CPMFCR_RAMTYPE 0
128# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkdb2f721f2003-03-06 00:58:30 +0000129
130#endif /* CONFIG_ETHER_INDEX */
131
132/* other options */
133#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
135#define CONFIG_SYS_I2C_SLAVE 0x7F
136#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenkdb2f721f2003-03-06 00:58:30 +0000137
wdenk5d232d02003-05-22 22:52:13 +0000138/* PCI */
139#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000140#define CONFIG_PCI_INDIRECT_BRIDGE
wdenk5d232d02003-05-22 22:52:13 +0000141#define CONFIG_PCI_PNP
142#define CONFIG_PCI_BOOTDELAY 0
143#undef CONFIG_PCI_SCAN_SHOW
144
wdenkdb2f721f2003-03-06 00:58:30 +0000145/*-----------------------------------------------------------------------
146 * Definitions for Serial Presence Detect EEPROM address
147 * (to get SDRAM settings)
148 */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200149#define SPD_EEPROM_ADDRESS 0x50
wdenkdb2f721f2003-03-06 00:58:30 +0000150
wdenk5d232d02003-05-22 22:52:13 +0000151#define CONFIG_8260_CLKIN 66000000 /* in Hz */
wdenkdb2f721f2003-03-06 00:58:30 +0000152#define CONFIG_BAUDRATE 115200
153
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500154/*
155 * Command line configuration.
156 */
Rune Torgersen298cd4c2007-10-17 11:56:31 -0500157#include <config_cmd_default.h>
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500158
Rune Torgersen298cd4c2007-10-17 11:56:31 -0500159/* Commands we want, that are not part of default set */
160#define CONFIG_CMD_ASKENV /* ask for env variable */
161#define CONFIG_CMD_CACHE /* icache, dcache */
162#define CONFIG_CMD_DHCP /* DHCP Support */
163#define CONFIG_CMD_DIAG /* Diagnostics */
164#define CONFIG_CMD_IMMAP /* IMMR dump support */
165#define CONFIG_CMD_IRQ /* irqinfo */
166#define CONFIG_CMD_MII /* MII support */
167#define CONFIG_CMD_PCI /* pciinfo */
168#define CONFIG_CMD_PING /* ping support */
169#define CONFIG_CMD_PORTIO /* Port I/O */
170#define CONFIG_CMD_REGINFO /* Register dump */
171#define CONFIG_CMD_SAVES /* save S record dump */
172#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
173
174/* Commands from default set we don't need */
175#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
176#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
wdenkdb2f721f2003-03-06 00:58:30 +0000177
wdenk5d232d02003-05-22 22:52:13 +0000178/* Define a command string that is automatically executed when no character
179 * is read on the console interface withing "Boot Delay" after reset.
180 */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200181#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
182#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenk5d232d02003-05-22 22:52:13 +0000183
wdenk42dfe7a2004-03-14 22:25:36 +0000184#ifdef CONFIG_BOOT_ROOT_INITRD
wdenk5d232d02003-05-22 22:52:13 +0000185#define CONFIG_BOOTCOMMAND \
186 "version;" \
187 "echo;" \
188 "bootp;" \
189 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100190 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk5d232d02003-05-22 22:52:13 +0000191 "bootm"
192#endif /* CONFIG_BOOT_ROOT_INITRD */
193
wdenk42dfe7a2004-03-14 22:25:36 +0000194#ifdef CONFIG_BOOT_ROOT_NFS
wdenk5d232d02003-05-22 22:52:13 +0000195#define CONFIG_BOOTCOMMAND \
196 "version;" \
197 "echo;" \
198 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100199 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
200 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk5d232d02003-05-22 22:52:13 +0000201 "bootm"
202#endif /* CONFIG_BOOT_ROOT_NFS */
203
Jon Loeliger7be044e2007-07-09 21:24:19 -0500204/*
205 * BOOTP options
wdenk5d232d02003-05-22 22:52:13 +0000206 */
Jon Loeliger7be044e2007-07-09 21:24:19 -0500207#define CONFIG_BOOTP_SUBNETMASK
208#define CONFIG_BOOTP_GATEWAY
209#define CONFIG_BOOTP_HOSTNAME
210#define CONFIG_BOOTP_BOOTPATH
211#define CONFIG_BOOTP_BOOTFILESIZE
212#define CONFIG_BOOTP_DNS
wdenk5d232d02003-05-22 22:52:13 +0000213
wdenkdb2f721f2003-03-06 00:58:30 +0000214#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkdb2f721f2003-03-06 00:58:30 +0000215
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500216#if defined(CONFIG_CMD_KGDB)
wdenkdb2f721f2003-03-06 00:58:30 +0000217#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
218#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
219#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
220#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
221#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
222#endif
223
224#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
225
226/*
227 * Miscellaneous configurable options
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_LONGHELP /* undef to save memory */
230#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500231#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000233#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000235#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
237#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
238#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
241#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenkdb2f721f2003-03-06 00:58:30 +0000242
wdenk5d232d02003-05-22 22:52:13 +0000243#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
wdenkdb2f721f2003-03-06 00:58:30 +0000244 /* for versions < 2.4.5-pre5 */
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkdb2f721f2003-03-06 00:58:30 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkdb2f721f2003-03-06 00:58:30 +0000249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkdb2f721f2003-03-06 00:58:30 +0000251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_FLASH_BASE 0xFE000000
wdenk5d232d02003-05-22 22:52:13 +0000253#define FLASH_BASE 0xFE000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
255#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
256#define CONFIG_SYS_FLASH_SIZE 8
257#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
258#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
wdenkdb2f721f2003-03-06 00:58:30 +0000259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#undef CONFIG_SYS_FLASH_CHECKSUM
wdenkdb2f721f2003-03-06 00:58:30 +0000261
262/* this is stuff came out of the Motorola docs */
263/* Only change this if you also change the Hardware configuration Word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
wdenkdb2f721f2003-03-06 00:58:30 +0000265
wdenkdb2f721f2003-03-06 00:58:30 +0000266/* Set IMMR to 0xF0000000 or above to boot Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_IMMR 0xF0000000
268#define CONFIG_SYS_BCSR 0xF8000000
269#define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */
wdenkdb2f721f2003-03-06 00:58:30 +0000270
271/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
272 */
273/*#define CONFIG_VERY_BIG_RAM 1*/
274
275/* What should be the base address of SDRAM DIMM and how big is
276 * it (in Mbytes)? This will normally auto-configure via the SPD.
277*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_SDRAM_BASE 0x00000000
279#define CONFIG_SYS_SDRAM_SIZE 16
wdenkdb2f721f2003-03-06 00:58:30 +0000280
281#define SDRAM_SPD_ADDR 0x50
282
wdenkdb2f721f2003-03-06 00:58:30 +0000283/*-----------------------------------------------------------------------
284 * BR2,BR3 - Base Register
285 * Ref: Section 10.3.1 on page 10-14
286 * OR2,OR3 - Option Register
287 * Ref: Section 10.3.2 on page 10-16
288 *-----------------------------------------------------------------------
289 */
290
291/* Bank 2,3 - SDRAM DIMM
292 */
293
294/* The BR2 is configured as follows:
295 *
296 * - Base address of 0x00000000
297 * - 64 bit port size (60x bus only)
298 * - Data errors checking is disabled
299 * - Read and write access
300 * - SDRAM 60x bus
301 * - Access are handled by the memory controller according to MSEL
302 * - Not used for atomic operations
303 * - No data pipelining is done
304 * - Valid
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000307 BRx_PS_64 |\
308 BRx_MS_SDRAM_P |\
309 BRx_V)
310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000312 BRx_PS_64 |\
313 BRx_MS_SDRAM_P |\
314 BRx_V)
315
316/* With a 64 MB DIMM, the OR2 is configured as follows:
317 *
318 * - 64 MB
319 * - 4 internal banks per device
320 * - Row start address bit is A8 with PSDMR[PBI] = 0
321 * - 12 row address lines
322 * - Back-to-back page mode
323 * - Internal bank interleaving within save device enabled
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#if (CONFIG_SYS_SDRAM_SIZE == 64)
326#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000327 ORxS_BPD_4 |\
328 ORxS_ROWST_PBI0_A8 |\
329 ORxS_NUMR_12)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#elif (CONFIG_SYS_SDRAM_SIZE == 16)
331#define CONFIG_SYS_OR2_PRELIM (0xFF000C80)
wdenkdb2f721f2003-03-06 00:58:30 +0000332#else
333#error "INVALID SDRAM CONFIGURATION"
334#endif
335
336/*-----------------------------------------------------------------------
337 * PSDMR - 60x Bus SDRAM Mode Register
338 * Ref: Section 10.3.3 on page 10-21
339 *-----------------------------------------------------------------------
340 */
341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#if (CONFIG_SYS_SDRAM_SIZE == 64)
wdenkdb2f721f2003-03-06 00:58:30 +0000343/* With a 64 MB DIMM, the PSDMR is configured as follows:
344 *
345 * - Bank Based Interleaving,
346 * - Refresh Enable,
347 * - Address Multiplexing where A5 is output on A14 pin
348 * (A6 on A15, and so on),
349 * - use address pins A14-A16 as bank select,
350 * - A9 is output on SDA10 during an ACTIVATE command,
351 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
352 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
353 * is 3 clocks,
354 * - earliest timing for READ/WRITE command after ACTIVATE command is
355 * 2 clocks,
356 * - earliest timing for PRECHARGE after last data was read is 1 clock,
357 * - earliest timing for PRECHARGE after last data was written is 1 clock,
358 * - CAS Latency is 2.
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenkdb2f721f2003-03-06 00:58:30 +0000361 PSDMR_SDAM_A14_IS_A5 |\
362 PSDMR_BSMA_A14_A16 |\
363 PSDMR_SDA10_PBI0_A9 |\
364 PSDMR_RFRC_7_CLK |\
365 PSDMR_PRETOACT_3W |\
366 PSDMR_ACTTORW_2W |\
367 PSDMR_LDOTOPRE_1C |\
368 PSDMR_WRC_1C |\
369 PSDMR_CL_2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#elif (CONFIG_SYS_SDRAM_SIZE == 16)
wdenkdb2f721f2003-03-06 00:58:30 +0000371/* With a 16 MB DIMM, the PSDMR is configured as follows:
372 *
373 * configuration parameters found in Motorola documentation
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_PSDMR (0x016EB452)
wdenkdb2f721f2003-03-06 00:58:30 +0000376#else
377#error "INVALID SDRAM CONFIGURATION"
378#endif
379
wdenkdb2f721f2003-03-06 00:58:30 +0000380#define RS232EN_1 0x02000002
381#define RS232EN_2 0x01000001
382#define FETHIEN 0x08000008
383#define FETH_RST 0x04000004
384
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200386#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200387#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkdb2f721f2003-03-06 00:58:30 +0000389
wdenk7a8e9bed2003-05-31 18:35:21 +0000390/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
wdenk5d232d02003-05-22 22:52:13 +0000391/* 0x0EB2B645 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
wdenk5d232d02003-05-22 22:52:13 +0000393 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\
394 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
395 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
wdenkdb2f721f2003-03-06 00:58:30 +0000396 )
wdenk5d232d02003-05-22 22:52:13 +0000397
wdenk7a8e9bed2003-05-31 18:35:21 +0000398/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
wdenkdb2f721f2003-03-06 00:58:30 +0000400
wdenk8bde7f72003-06-27 21:31:46 +0000401/* This value should actually be situated in the first 256 bytes of the FLASH
wdenkdb2f721f2003-03-06 00:58:30 +0000402 which on the standard MPC8266ADS board is at address 0xFF800000
403 The linker script places it at 0xFFF00000 instead.
404
wdenk8bde7f72003-06-27 21:31:46 +0000405 It still works, however, as long as the ADS board jumper JP3 is set to
406 position 2-3 so the board is using the BCSR as Hardware Configuration Word
wdenkdb2f721f2003-03-06 00:58:30 +0000407
wdenk8bde7f72003-06-27 21:31:46 +0000408 If you want to use the one defined here instead, ust copy the first 256 bytes from
409 0xfff00000 to 0xff800000 (for 8MB flash)
wdenkdb2f721f2003-03-06 00:58:30 +0000410
411 - Rune
412
wdenk7a8e9bed2003-05-31 18:35:21 +0000413*/
wdenkdb2f721f2003-03-06 00:58:30 +0000414
415/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_HRCW_SLAVE1 0
417#define CONFIG_SYS_HRCW_SLAVE2 0
418#define CONFIG_SYS_HRCW_SLAVE3 0
419#define CONFIG_SYS_HRCW_SLAVE4 0
420#define CONFIG_SYS_HRCW_SLAVE5 0
421#define CONFIG_SYS_HRCW_SLAVE6 0
422#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkdb2f721f2003-03-06 00:58:30 +0000423
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200424#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Peter Tyserd98b0522010-10-14 23:33:24 -0500425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
427# define CONFIG_SYS_RAMBOOT
wdenkdb2f721f2003-03-06 00:58:30 +0000428#endif
429
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
431#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
432#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdb2f721f2003-03-06 00:58:30 +0000433
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200435# define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200437# define CONFIG_ENV_SECT_SIZE 0x40000
wdenkdb2f721f2003-03-06 00:58:30 +0000438#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200439# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200441# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#endif /* CONFIG_SYS_RAMBOOT */
wdenkdb2f721f2003-03-06 00:58:30 +0000443
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500445#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkdb2f721f2003-03-06 00:58:30 +0000447#endif
448
wdenk7a8e9bed2003-05-31 18:35:21 +0000449/*-----------------------------------------------------------------------
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200450 * HIDx - Hardware Implementation-dependent Registers 2-11
wdenk7a8e9bed2003-05-31 18:35:21 +0000451 *-----------------------------------------------------------------------
452 * HID0 also contains cache control - initially enable both caches and
453 * invalidate contents, then the final state leaves only the instruction
454 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
455 * but Soft reset does not.
456 *
457 * HID1 has only read-only information - nothing to set.
458 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459/*#define CONFIG_SYS_HID0_INIT 0 */
460#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenk7a8e9bed2003-05-31 18:35:21 +0000461 HID0_DCE |\
462 HID0_ICFI |\
463 HID0_DCI |\
464 HID0_IFEM |\
465 HID0_ABE)
466
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
wdenkdb2f721f2003-03-06 00:58:30 +0000468
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_HID2 0
wdenkdb2f721f2003-03-06 00:58:30 +0000470
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_SYPCR 0xFFFFFFC3
472#define CONFIG_SYS_BCR 0x004C0000
473#define CONFIG_SYS_SIUMCR 0x4E64C000
474#define CONFIG_SYS_SCCR 0x00000000
wdenkdb2f721f2003-03-06 00:58:30 +0000475
wdenk5d232d02003-05-22 22:52:13 +0000476/* local bus memory map
477 *
478 * 0x00000000-0x03FFFFFF 64MB SDRAM
479 * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
480 * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
481 * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200482 * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
wdenk5d232d02003-05-22 22:52:13 +0000483 * 0xF8000000-0xF8007FFF 32KB BCSR
484 * 0xF8100000-0xF8107FFF 32KB ATM UNI
485 * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
486 * 0xF8300000-0xF8307FFF 32KB EEPROM
487 * 0xFE000000-0xFFFFFFFF 32MB flash
488 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */
490#define CONFIG_SYS_OR0_PRELIM 0xFE000836
491#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */
492#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
493#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */
494#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846
495#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
496#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36
497#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
498#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
wdenk5d232d02003-05-22 22:52:13 +0000499
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_RMR 0x0001
501#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
502#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
503#define CONFIG_SYS_RCCR 0
504#define CONFIG_SYS_MPTPR 0x00001900
505#define CONFIG_SYS_PSRT 0x00000021
wdenkdb2f721f2003-03-06 00:58:30 +0000506
wdenk65bd0e22003-09-18 10:45:21 +0000507/* This address must not exist */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00
wdenkdb2f721f2003-03-06 00:58:30 +0000509
wdenk5d232d02003-05-22 22:52:13 +0000510/* PCI Memory map (if different from default map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
512#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
513#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
wdenk8bde7f72003-06-27 21:31:46 +0000514 PICMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000515
wdenk8bde7f72003-06-27 21:31:46 +0000516/*
wdenk5d232d02003-05-22 22:52:13 +0000517 * These are the windows that allow the CPU to access PCI address space.
wdenk8bde7f72003-06-27 21:31:46 +0000518 * All three PCI master windows, which allow the CPU to access PCI
519 * prefetch, non prefetch, and IO space (see below), must all fit within
wdenk5d232d02003-05-22 22:52:13 +0000520 * these windows.
521 */
522
523/* PCIBR0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */
525#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000526/* PCIBR1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
528#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000529
wdenk8bde7f72003-06-27 21:31:46 +0000530/*
wdenk5d232d02003-05-22 22:52:13 +0000531 * Master window that allows the CPU to access PCI Memory (prefetch).
532 * This window will be setup with the first set of Outbound ATU registers
533 * in the bridge.
534 */
535
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
537#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
538#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
539#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
540#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000541
wdenk8bde7f72003-06-27 21:31:46 +0000542/*
wdenk5d232d02003-05-22 22:52:13 +0000543 * Master window that allows the CPU to access PCI Memory (non-prefetch).
544 * This window will be setup with the second set of Outbound ATU registers
545 * in the bridge.
546 */
547
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
549#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
550#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
551#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
552#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
wdenk5d232d02003-05-22 22:52:13 +0000553
wdenk8bde7f72003-06-27 21:31:46 +0000554/*
wdenk5d232d02003-05-22 22:52:13 +0000555 * Master window that allows the CPU to access PCI IO space.
556 * This window will be setup with the third set of Outbound ATU registers
557 * in the bridge.
558 */
559
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
561#define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
562#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
563#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
564#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
wdenk5d232d02003-05-22 22:52:13 +0000565
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200566/*
567 * JFFS2 partitions
568 *
569 */
570/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100571#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200572#define CONFIG_JFFS2_DEV "nor0"
573#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
574#define CONFIG_JFFS2_PART_OFFSET 0x00000000
575
576/* mtdparts command line support */
577/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100578#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200579#define MTDIDS_DEFAULT ""
580#define MTDPARTS_DEFAULT ""
581*/
wdenk5d232d02003-05-22 22:52:13 +0000582
wdenkdb2f721f2003-03-06 00:58:30 +0000583#endif /* __CONFIG_H */