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Heiko Schocherf5e0d032006-06-19 11:02:41 +02001/*
2 * ppmc7xx.h
3 * ---------
Wolfgang Denkb87dfd22006-07-19 13:50:38 +02004 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +02005 * Wind River PPMC 7xx/74xx board configuration file.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +02006 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +02007 * By Richard Danter (richard.danter@windriver.com)
8 * Copyright (C) 2005 Wind River Systems
9 */
10
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_PPMC7XX
16
17
18/*===================================================================
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020019 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020020 * User configurable settings - Modify to your preference
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020021 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020022 *===================================================================
23 */
24
25/*
26 * Debug
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020027 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020028 * DEBUG - Define this is you want extra debug info
29 * GTREGREAD - Required to build with debug
30 * do_bdinfo - Required to build with debug
Heiko Schocherf5e0d032006-06-19 11:02:41 +020031 */
32
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020033#ifdef DEBUG
34#define GTREGREAD(x) 0xFFFFFFFF
Heiko Schocherf5e0d032006-06-19 11:02:41 +020035#define do_bdinfo(a,b,c,d)
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020036#endif
Heiko Schocherf5e0d032006-06-19 11:02:41 +020037
38/*
39 * CPU type
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020040 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020041 * CONFIG_7xx - We have a 750 or 755 CPU
42 * CONFIG_74xx - We have a 7400 CPU
43 * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
44 * CONFIG_BUS_CLK - System bus clock in Hz
Heiko Schocherf5e0d032006-06-19 11:02:41 +020045 */
46
47#define CONFIG_7xx
48#undef CONFIG_74xx
49#undef CONFIG_ALTIVEC
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020050#define CONFIG_BUS_CLK 66000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +020051
Wolfgang Denk2ae18242010-10-06 09:05:45 +020052#define CONFIG_SYS_TEXT_BASE 0xFFF00000
Heiko Schocherf5e0d032006-06-19 11:02:41 +020053
Marek Vasut0aa27652011-10-21 14:17:33 +000054#ifndef __ASSEMBLY__
55#include <galileo/core.h>
56#endif
57
Heiko Schocherf5e0d032006-06-19 11:02:41 +020058/*
59 * Monitor configuration
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020060 *
Jon Loeliger26a34562007-07-04 22:33:17 -050061 * List of command sets to include in shell
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020062 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020063 * The following command sets have been tested and known to work:
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020064 *
Jon Loeliger26a34562007-07-04 22:33:17 -050065 * CMD_CACHE - Cache control commands
66 * CMD_MEMORY - Memory display, change and test commands
67 * CMD_FLASH - Erase and program flash
68 * CMD_ENV - Environment commands
69 * CMD_RUN - Run commands stored in env vars
70 * CMD_ELF - Load ELF files
71 * CMD_NET - Networking/file download commands
72 * CMD_PIN - ICMP Echo Request command
73 * CMD_PCI - PCI Bus scanning command
Heiko Schocherf5e0d032006-06-19 11:02:41 +020074 */
75
Jon Loeliger26a34562007-07-04 22:33:17 -050076/*
Jon Loeliger079a1362007-07-10 10:12:10 -050077 * BOOTP options
78 */
79#define CONFIG_BOOTP_BOOTFILESIZE
80#define CONFIG_BOOTP_BOOTPATH
81#define CONFIG_BOOTP_GATEWAY
82#define CONFIG_BOOTP_HOSTNAME
83
84
85/*
Jon Loeliger26a34562007-07-04 22:33:17 -050086 * Command line configuration.
87 */
88#include <config_cmd_default.h>
89
90#define CONFIG_CMD_FLASH
Mike Frysingerbdab39d2009-01-28 19:08:14 -050091#define CONFIG_CMD_SAVEENV
Jon Loeliger26a34562007-07-04 22:33:17 -050092#define CONFIG_CMD_RUN
93#define CONFIG_CMD_ELF
94#define CONFIG_CMD_NET
95#define CONFIG_CMD_PING
96#define CONFIG_CMD_PCI
97
98#undef CONFIG_CMD_KGDB
Heiko Schocherf5e0d032006-06-19 11:02:41 +020099
100
101/*
102 * Serial configuration
103 *
104 * CONFIG_CONS_INDEX - Serial console port number (COM1)
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200105 * CONFIG_BAUDRATE - Serial speed
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200106 */
107
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200108#define CONFIG_CONS_INDEX 1
109#define CONFIG_BAUDRATE 9600
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200110
111
112/*
113 * PCI config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200114 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200115 * CONFIG_PCI - Enable PCI bus
116 * CONFIG_PCI_PNP - Enable Plug & Play support
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200117 * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
118 */
119
120#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000121#define CONFIG_PCI_INDIRECT_BRIDGE
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200122#define CONFIG_PCI_PNP
123#undef CONFIG_PCI_SCAN_SHOW
124
125
126/*
127 * Network config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200128 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200129 * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
130 * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200131 */
132
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200133#define CONFIG_EEPRO100
134#define CONFIG_EEPRO100_SROM_WRITE
135
136
137/*
138 * Enable extra init functions
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200139 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200140 * CONFIG_MISC_INIT_F - Call pre-relocation init functions
141 * CONFIG_MISC_INIT_R - Call post relocation init functions
142 */
143
144#undef CONFIG_MISC_INIT_F
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200145#define CONFIG_MISC_INIT_R
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200146
147
148/*
149 * Boot config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200150 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200151 * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200152 * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200153 */
154
155#define CONFIG_BOOTCOMMAND \
156 "bootp;" \
157 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
158 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
159 "bootm"
160#define CONFIG_BOOTDELAY 5
161
162
163/*===================================================================
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200164 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200165 * Board configuration settings - You should not need to modify these
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200166 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200167 *===================================================================
168 */
169
170
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200171/*
172 * Memory map
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200173 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200174 * This board runs in a standard CHRP (Map-B) configuration.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200175 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200176 * Type Start End Size Width Chip Sel
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200177 * ----------- ----------- ----------- ------- ------- --------
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200178 * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
179 * User LED's 0x78000000 RCS3
180 * UART 0x7C000000 RCS2
181 * Mailbox 0xFF000000 RCS1
182 * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200183 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200184 * Flash sectors are laid out as follows.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200185 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200186 * Sector Start End Size Comments
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200187 * ------- ----------- ----------- ------- -----------
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200188 * 0 0xFFC00000 0xFFC3FFFF 256KB
189 * 1 0xFFC40000 0xFFC7FFFF 256KB
190 * 2 0xFFC80000 0xFFCBFFFF 256KB
191 * 3 0xFFCC0000 0xFFCFFFFF 256KB
192 * 4 0xFFD00000 0xFFD3FFFF 256KB
193 * 5 0xFFD40000 0xFFD7FFFF 256KB
194 * 6 0xFFD80000 0xFFDBFFFF 256KB
195 * 7 0xFFDC0000 0xFFDFFFFF 256KB
196 * 8 0xFFE00000 0xFFE3FFFF 256KB
197 * 9 0xFFE40000 0xFFE7FFFF 256KB
198 * 10 0xFFE80000 0xFFEBFFFF 256KB
199 * 11 0xFFEC0000 0xFFEFFFFF 256KB
200 * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
201 * 13 0xFFF40000 0xFFF7FFFF 256KB
202 * 14 0xFFF80000 0xFFFBFFFF 256KB
203 * 15 0xFFFC0000 0xFFFDFFFF 128KB
204 * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
205 * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
206 * 18 0xFFFF0000 0xFFFFFFFF 64KB
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200207 */
208
209
210/*
211 * SDRAM config - see memory map details above.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200212 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 * CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
214 * CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200215 */
216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_SDRAM_BASE 0x00000000
218#define CONFIG_SYS_SDRAM_SIZE 0x04000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200219
220
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200221/*
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200222 * Flash config - see memory map details above.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200223 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 * CONFIG_SYS_FLASH_BASE - Start address of flash memory
225 * CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem
226 * CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms
227 * CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms
228 * CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board
229 * CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200230 */
231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_FLASH_BASE 0xFFC00000
233#define CONFIG_SYS_FLASH_SIZE 0x00400000
234#define CONFIG_SYS_FLASH_ERASE_TOUT 250000
235#define CONFIG_SYS_FLASH_WRITE_TOUT 5000
236#define CONFIG_SYS_MAX_FLASH_BANKS 1
237#define CONFIG_SYS_MAX_FLASH_SECT 19
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200238
239
240/*
241 * Monitor config - see memory map details above
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200242 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243 * CONFIG_SYS_MONITOR_BASE - Base address of monitor code
244 * CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200245 */
246
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200247#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_MALLOC_LEN 0x20000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200249
250
251/*
252 * Command shell settings
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200253 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254 * CONFIG_SYS_BARGSIZE - Boot Argument buffer size
255 * CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
256 * CONFIG_SYS_CBSIZE - Console Buffer (input) size
257 * CONFIG_SYS_LOAD_ADDR - Default load address
258 * CONFIG_SYS_LONGHELP - Provide more detailed help
259 * CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands
260 * CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM
261 * CONFIG_SYS_MEMTEST_END - End address of RAM test
262 * CONFIG_SYS_PBSIZE - Print Buffer (output) size
263 * CONFIG_SYS_PROMPT - Prompt string
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200264 */
265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_BARGSIZE 1024
267#define CONFIG_SYS_BOOTMAPSZ 0x800000
268#define CONFIG_SYS_CBSIZE 1024
269#define CONFIG_SYS_LOAD_ADDR 0x100000
270#define CONFIG_SYS_LONGHELP
271#define CONFIG_SYS_MAXARGS 16
272#define CONFIG_SYS_MEMTEST_START 0x00040000
273#define CONFIG_SYS_MEMTEST_END 0x00040100
274#define CONFIG_SYS_PBSIZE 1024
275#define CONFIG_SYS_PROMPT "=> "
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200276
277
278/*
279 * Environment config - see memory map details above
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200280 *
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200281 * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200282 * CONFIG_ENV_ADDR - Address of the sector containing env vars
283 * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
284 * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200285 */
286
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200287#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200288#define CONFIG_ENV_ADDR 0xFFFE0000
289#define CONFIG_ENV_SIZE 0x1000
290#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000
291#define CONFIG_ENV_SIZE_REDUND 0x1000
292#define CONFIG_ENV_SECT_SIZE 0x8000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200293
294
295/*
296 * Initial RAM config
297 *
298 * Since the main system RAM is initialised very early, we place the INIT_RAM
299 * in the main system RAM just above the exception vectors. The contents are
300 * copied to top of RAM by the init code.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200301 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302 * CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect
Wolfgang Denk553f0982010-10-26 13:32:32 +0200303 * CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200304 * GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305 * CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200306 */
307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200309#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200310#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200311
312
313/*
314 * Initial BAT config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200315 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200316 * BAT0 - System SDRAM
317 * BAT1 - LED's and Serial Port
318 * BAT2 - PCI Memory
319 * BAT3 - PCI I/O including Flash Memory
320 */
321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
323#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
324#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
325#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
328#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
329#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
330#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
333#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
334#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
335#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
338#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
339#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
340#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200341
342
343/*
344 * Cache config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200345 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346 * CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific)
347 * CONFIG_SYS_L2 - L2 cache enabled if defined
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200348 * L2_INIT - L2 cache init flags
349 * L2_ENABLE - L2 cache enable flags
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200350 */
351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_CACHELINE_SIZE 32
353#undef CONFIG_SYS_L2
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200354#define L2_INIT 0
355#define L2_ENABLE 0
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200356
357
358/*
359 * Clocks config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200360 *
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200361 * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362 * CONFIG_SYS_HZ - Decrementer freq in Hz
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200363 */
364
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK
366#define CONFIG_SYS_HZ 1000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200367
368
369/*
370 * Serial port config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200371 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372 * CONFIG_SYS_NS16550 - Include the NS16550 driver
373 * CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver
374 * CONFIG_SYS_NS16550_CLK - Frequency of reference clock
375 * CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
376 * CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200377 */
378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_NS16550
380#define CONFIG_SYS_NS16550_SERIAL
381#define CONFIG_SYS_NS16550_CLK 3686400
382#define CONFIG_SYS_NS16550_REG_SIZE -8
383#define CONFIG_SYS_NS16550_COM1 0x7C000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200384
385
386/*
387 * PCI Config - Address Map B (CHRP)
388 */
389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
391#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
392#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
393#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
394#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
395#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000
396#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
397#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000
398#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
399#define CONFIG_SYS_PCI_IO_BUS 0x00800000
400#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000
401#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
402#define CONFIG_SYS_ISA_IO_BUS 0x00000000
403#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000
404#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
405#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
406#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
407#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200408
409
410/*
411 * Extra init functions
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200412 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413 * CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200414 */
415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_BOARD_ASM_INIT
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200417
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200418#endif /* __CONFIG_H */