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maxims@google.com14e4b142017-01-18 13:44:56 -08001/*
2 * (C) Copyright 2016 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <asm/io.h>
11#include <asm/arch/scu_ast2500.h>
12#include <dm/lists.h>
13#include <dt-bindings/clock/ast2500-scu.h>
14
maxims@google.com3b959022017-04-17 12:00:32 -070015/*
16 * MAC Clock Delay settings, taken from Aspeed SDK
17 */
18#define RGMII_TXCLK_ODLY 8
19#define RMII_RXCLK_IDLY 2
20
21/*
22 * TGMII Clock Duty constants, taken from Aspeed SDK
23 */
24#define RGMII2_TXCK_DUTY 0x66
25#define RGMII1_TXCK_DUTY 0x64
26
27#define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
28
maxims@google.com14e4b142017-01-18 13:44:56 -080029DECLARE_GLOBAL_DATA_PTR;
30
31/*
maxims@google.com3b959022017-04-17 12:00:32 -070032 * Clock divider/multiplier configuration struct.
maxims@google.com14e4b142017-01-18 13:44:56 -080033 * For H-PLL and M-PLL the formula is
34 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
35 * M - Numerator
36 * N - Denumerator
37 * P - Post Divider
38 * They have the same layout in their control register.
maxims@google.com3b959022017-04-17 12:00:32 -070039 *
40 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
41 * yet needed and ignored by clock configurations.
maxims@google.com14e4b142017-01-18 13:44:56 -080042 */
maxims@google.com3b959022017-04-17 12:00:32 -070043struct ast2500_div_config {
44 unsigned int num;
45 unsigned int denum;
46 unsigned int post_div;
47};
maxims@google.com14e4b142017-01-18 13:44:56 -080048
49/*
50 * Get the rate of the M-PLL clock from input clock frequency and
51 * the value of the M-PLL Parameter Register.
52 */
53static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
54{
maxims@google.comdefb1842017-04-17 12:00:33 -070055 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
56 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
57 >> SCU_MPLL_DENUM_SHIFT;
58 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
59 >> SCU_MPLL_POST_SHIFT;
maxims@google.com14e4b142017-01-18 13:44:56 -080060
maxims@google.comd5ce3572017-01-30 11:35:04 -080061 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
maxims@google.com14e4b142017-01-18 13:44:56 -080062}
63
64/*
65 * Get the rate of the H-PLL clock from input clock frequency and
66 * the value of the H-PLL Parameter Register.
67 */
68static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
69{
maxims@google.comdefb1842017-04-17 12:00:33 -070070 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
71 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
72 >> SCU_HPLL_DENUM_SHIFT;
73 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
74 >> SCU_HPLL_POST_SHIFT;
maxims@google.com14e4b142017-01-18 13:44:56 -080075
maxims@google.comd5ce3572017-01-30 11:35:04 -080076 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
maxims@google.com14e4b142017-01-18 13:44:56 -080077}
78
79static ulong ast2500_get_clkin(struct ast2500_scu *scu)
80{
81 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
82 ? 25 * 1000 * 1000 : 24 * 1000 * 1000;
83}
84
85/**
86 * Get current rate or uart clock
87 *
88 * @scu SCU registers
89 * @uart_index UART index, 1-5
90 *
91 * @return current setting for uart clock rate
92 */
93static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
94{
95 /*
96 * ast2500 datasheet is very confusing when it comes to UART clocks,
97 * especially when CLKIN = 25 MHz. The settings are in
98 * different registers and it is unclear how they interact.
99 *
100 * This has only been tested with default settings and CLKIN = 24 MHz.
101 */
102 ulong uart_clkin;
103
104 if (readl(&scu->misc_ctrl2) &
105 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
106 uart_clkin = 192 * 1000 * 1000;
107 else
108 uart_clkin = 24 * 1000 * 1000;
109
110 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
111 uart_clkin /= 13;
112
113 return uart_clkin;
114}
115
116static ulong ast2500_clk_get_rate(struct clk *clk)
117{
118 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
119 ulong clkin = ast2500_get_clkin(priv->scu);
120 ulong rate;
121
122 switch (clk->id) {
123 case PLL_HPLL:
124 case ARMCLK:
125 /*
126 * This ignores dynamic/static slowdown of ARMCLK and may
127 * be inaccurate.
128 */
129 rate = ast2500_get_hpll_rate(clkin,
130 readl(&priv->scu->h_pll_param));
131 break;
132 case MCLK_DDR:
133 rate = ast2500_get_mpll_rate(clkin,
134 readl(&priv->scu->m_pll_param));
135 break;
maxims@google.com4999bb02017-04-17 12:00:29 -0700136 case BCLK_PCLK:
137 {
138 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
maxims@google.comdefb1842017-04-17 12:00:33 -0700139 & SCU_PCLK_DIV_MASK)
140 >> SCU_PCLK_DIV_SHIFT);
maxims@google.com4999bb02017-04-17 12:00:29 -0700141 rate = ast2500_get_hpll_rate(clkin,
maxims@google.comdefb1842017-04-17 12:00:33 -0700142 readl(&priv->
143 scu->h_pll_param));
maxims@google.com4999bb02017-04-17 12:00:29 -0700144 rate = rate / apb_div;
145 }
146 break;
maxims@google.com14e4b142017-01-18 13:44:56 -0800147 case PCLK_UART1:
148 rate = ast2500_get_uart_clk_rate(priv->scu, 1);
149 break;
150 case PCLK_UART2:
151 rate = ast2500_get_uart_clk_rate(priv->scu, 2);
152 break;
153 case PCLK_UART3:
154 rate = ast2500_get_uart_clk_rate(priv->scu, 3);
155 break;
156 case PCLK_UART4:
157 rate = ast2500_get_uart_clk_rate(priv->scu, 4);
158 break;
159 case PCLK_UART5:
160 rate = ast2500_get_uart_clk_rate(priv->scu, 5);
161 break;
162 default:
163 return -ENOENT;
164 }
165
166 return rate;
167}
168
maxims@google.com3b959022017-04-17 12:00:32 -0700169/*
170 * @input_rate - the rate of input clock in Hz
171 * @requested_rate - desired output rate in Hz
172 * @div - this is an IN/OUT parameter, at input all fields of the config
173 * need to be set to their maximum allowed values.
174 * The result (the best config we could find), would also be returned
175 * in this structure.
176 *
177 * @return The clock rate, when the resulting div_config is used.
178 */
179static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
180 struct ast2500_div_config *cfg)
maxims@google.com14e4b142017-01-18 13:44:56 -0800181{
maxims@google.com14e4b142017-01-18 13:44:56 -0800182 /*
maxims@google.com3b959022017-04-17 12:00:32 -0700183 * The assumption is that kHz precision is good enough and
184 * also enough to avoid overflow when multiplying.
maxims@google.com14e4b142017-01-18 13:44:56 -0800185 */
maxims@google.com3b959022017-04-17 12:00:32 -0700186 const ulong input_rate_khz = input_rate / 1000;
187 const ulong rate_khz = requested_rate / 1000;
188 const struct ast2500_div_config max_vals = *cfg;
189 struct ast2500_div_config it = { 0, 0, 0 };
190 ulong delta = rate_khz;
191 ulong new_rate_khz = 0;
maxims@google.com14e4b142017-01-18 13:44:56 -0800192
maxims@google.com3b959022017-04-17 12:00:32 -0700193 for (; it.denum <= max_vals.denum; ++it.denum) {
194 for (it.post_div = 0; it.post_div <= max_vals.post_div;
195 ++it.post_div) {
196 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz)
197 * (it.denum + 1);
198 if (it.num > max_vals.num)
199 continue;
200
201 new_rate_khz = (input_rate_khz
202 * ((it.num + 1) / (it.denum + 1)))
203 / (it.post_div + 1);
maxims@google.com14e4b142017-01-18 13:44:56 -0800204
205 /* Keep the rate below requested one. */
206 if (new_rate_khz > rate_khz)
207 continue;
208
209 if (new_rate_khz - rate_khz < delta) {
210 delta = new_rate_khz - rate_khz;
maxims@google.com3b959022017-04-17 12:00:32 -0700211 *cfg = it;
maxims@google.com14e4b142017-01-18 13:44:56 -0800212 if (delta == 0)
maxims@google.com3b959022017-04-17 12:00:32 -0700213 return new_rate_khz * 1000;
maxims@google.com14e4b142017-01-18 13:44:56 -0800214 }
215 }
216 }
217
maxims@google.com3b959022017-04-17 12:00:32 -0700218 return new_rate_khz * 1000;
219}
220
221static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
222{
223 ulong clkin = ast2500_get_clkin(scu);
224 u32 mpll_reg;
225 struct ast2500_div_config div_cfg = {
maxims@google.comdefb1842017-04-17 12:00:33 -0700226 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
227 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
228 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
maxims@google.com3b959022017-04-17 12:00:32 -0700229 };
230
231 ast2500_calc_clock_config(clkin, rate, &div_cfg);
232
maxims@google.com14e4b142017-01-18 13:44:56 -0800233 mpll_reg = readl(&scu->m_pll_param);
maxims@google.comdefb1842017-04-17 12:00:33 -0700234 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
235 | SCU_MPLL_DENUM_MASK);
maxims@google.com3b959022017-04-17 12:00:32 -0700236 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
237 | (div_cfg.num << SCU_MPLL_NUM_SHIFT)
238 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);
maxims@google.com14e4b142017-01-18 13:44:56 -0800239
maxims@google.com413353b2017-04-17 12:00:23 -0700240 ast_scu_unlock(scu);
maxims@google.com14e4b142017-01-18 13:44:56 -0800241 writel(mpll_reg, &scu->m_pll_param);
maxims@google.com413353b2017-04-17 12:00:23 -0700242 ast_scu_lock(scu);
maxims@google.com14e4b142017-01-18 13:44:56 -0800243
244 return ast2500_get_mpll_rate(clkin, mpll_reg);
245}
246
maxims@google.com3b959022017-04-17 12:00:32 -0700247static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index)
248{
249 ulong clkin = ast2500_get_clkin(scu);
250 ulong hpll_rate = ast2500_get_hpll_rate(clkin,
251 readl(&scu->h_pll_param));
252 ulong required_rate;
253 u32 hwstrap;
254 u32 divisor;
255 u32 reset_bit;
256 u32 clkstop_bit;
257
258 /*
259 * According to data sheet, for 10/100 mode the MAC clock frequency
260 * should be at least 25MHz and for 1000 mode at least 100MHz
261 */
262 hwstrap = readl(&scu->hwstrap);
263 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII))
264 required_rate = 100 * 1000 * 1000;
265 else
266 required_rate = 25 * 1000 * 1000;
267
268 divisor = hpll_rate / required_rate;
269
270 if (divisor < 4) {
271 /* Clock can't run fast enough, but let's try anyway */
272 debug("MAC clock too slow\n");
273 divisor = 4;
274 } else if (divisor > 16) {
275 /* Can't slow down the clock enough, but let's try anyway */
276 debug("MAC clock too fast\n");
277 divisor = 16;
278 }
279
280 switch (index) {
281 case 1:
282 reset_bit = SCU_SYSRESET_MAC1;
283 clkstop_bit = SCU_CLKSTOP_MAC1;
284 break;
285 case 2:
286 reset_bit = SCU_SYSRESET_MAC2;
287 clkstop_bit = SCU_CLKSTOP_MAC2;
288 break;
289 default:
290 return -EINVAL;
291 }
292
293 ast_scu_unlock(scu);
294 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,
295 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT);
296
297 /*
298 * Disable MAC, start its clock and re-enable it.
299 * The procedure and the delays (100us & 10ms) are
300 * specified in the datasheet.
301 */
302 setbits_le32(&scu->sysreset_ctrl1, reset_bit);
303 udelay(100);
304 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
305 mdelay(10);
306 clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
307
308 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
309 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT),
310 &scu->clk_duty_sel);
311
312 ast_scu_lock(scu);
313
314 return required_rate;
315}
316
317static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
318{
319 /*
320 * The values and the meaning of the next three
321 * parameters are undocumented. Taken from Aspeed SDK.
322 */
323 const u32 d2_pll_ext_param = 0x2c;
324 const u32 d2_pll_sip = 0x11;
325 const u32 d2_pll_sic = 0x18;
326 u32 clk_delay_settings =
327 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
328 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
329 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
330 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT);
331 struct ast2500_div_config div_cfg = {
332 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT,
333 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT,
334 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT,
335 };
336 ulong clkin = ast2500_get_clkin(scu);
337 ulong new_rate;
338
339 ast_scu_unlock(scu);
340 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT)
341 | SCU_D2PLL_EXT1_OFF
342 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);
343
344 /*
345 * Select USB2.0 port1 PHY clock as a clock source for GCRT.
346 * This would disconnect it from D2-PLL.
347 */
348 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,
349 SCU_MISC_GCRT_USB20CLK);
350
351 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);
352 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT)
353 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT)
354 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT)
355 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT)
356 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT),
357 &scu->d2_pll_param);
358
359 clrbits_le32(&scu->d2_pll_ext_param[0],
360 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET);
361
362 clrsetbits_le32(&scu->misc_ctrl2,
363 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL
364 | SCU_MISC2_RGMII_CLKDIV_MASK |
365 SCU_MISC2_RMII_CLKDIV_MASK,
366 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT));
367
368 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);
369 writel(clk_delay_settings, &scu->mac_clk_delay_100M);
370 writel(clk_delay_settings, &scu->mac_clk_delay_10M);
371
372 ast_scu_lock(scu);
373
374 return new_rate;
375}
376
maxims@google.com14e4b142017-01-18 13:44:56 -0800377static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
378{
379 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
380
381 ulong new_rate;
382 switch (clk->id) {
383 case PLL_MPLL:
384 case MCLK_DDR:
385 new_rate = ast2500_configure_ddr(priv->scu, rate);
386 break;
maxims@google.com3b959022017-04-17 12:00:32 -0700387 case PLL_D2PLL:
388 new_rate = ast2500_configure_d2pll(priv->scu, rate);
389 break;
maxims@google.com14e4b142017-01-18 13:44:56 -0800390 default:
391 return -ENOENT;
392 }
393
394 return new_rate;
395}
396
maxims@google.com3b959022017-04-17 12:00:32 -0700397static int ast2500_clk_enable(struct clk *clk)
398{
399 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
400
401 switch (clk->id) {
402 /*
403 * For MAC clocks the clock rate is
404 * configured based on whether RGMII or RMII mode has been selected
405 * through hardware strapping.
406 */
407 case PCLK_MAC1:
408 ast2500_configure_mac(priv->scu, 1);
409 break;
410 case PCLK_MAC2:
411 ast2500_configure_mac(priv->scu, 2);
412 break;
413 case PLL_D2PLL:
414 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
415 default:
416 return -ENOENT;
417 }
418
419 return 0;
420}
421
maxims@google.com14e4b142017-01-18 13:44:56 -0800422struct clk_ops ast2500_clk_ops = {
423 .get_rate = ast2500_clk_get_rate,
424 .set_rate = ast2500_clk_set_rate,
maxims@google.com3b959022017-04-17 12:00:32 -0700425 .enable = ast2500_clk_enable,
maxims@google.com14e4b142017-01-18 13:44:56 -0800426};
427
428static int ast2500_clk_probe(struct udevice *dev)
429{
430 struct ast2500_clk_priv *priv = dev_get_priv(dev);
431
Simon Glassa821c4a2017-05-17 17:18:05 -0600432 priv->scu = devfdt_get_addr_ptr(dev);
maxims@google.com14e4b142017-01-18 13:44:56 -0800433 if (IS_ERR(priv->scu))
434 return PTR_ERR(priv->scu);
435
436 return 0;
437}
438
439static int ast2500_clk_bind(struct udevice *dev)
440{
441 int ret;
442
443 /* The reset driver does not have a device node, so bind it here */
444 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
445 if (ret)
446 debug("Warning: No reset driver: ret=%d\n", ret);
447
448 return 0;
449}
450
451static const struct udevice_id ast2500_clk_ids[] = {
452 { .compatible = "aspeed,ast2500-scu" },
453 { }
454};
455
456U_BOOT_DRIVER(aspeed_ast2500_scu) = {
457 .name = "aspeed_ast2500_scu",
458 .id = UCLASS_CLK,
459 .of_match = ast2500_clk_ids,
460 .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
461 .ops = &ast2500_clk_ops,
462 .bind = ast2500_clk_bind,
463 .probe = ast2500_clk_probe,
464};