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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk5d3207d2002-08-21 22:08:56 +00002/*
Michal Simekd5dae852013-04-22 15:43:02 +02003 * (C) Copyright 2012-2013, Xilinx, Michal Simek
4 *
wdenk5d3207d2002-08-21 22:08:56 +00005 * (C) Copyright 2002
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7 * Keith Outwater, keith_outwater@mvis.com
wdenk5d3207d2002-08-21 22:08:56 +00008 */
9
10/*
11 * Xilinx FPGA support
12 */
13
14#include <common.h>
Michal Simek6631db42013-04-26 15:04:48 +020015#include <fpga.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060016#include <log.h>
wdenk5d3207d2002-08-21 22:08:56 +000017#include <virtex2.h>
18#include <spartan2.h>
Wolfgang Denk875c7892005-09-25 16:44:21 +020019#include <spartan3.h>
Michal Simekd5dae852013-04-22 15:43:02 +020020#include <zynqpl.h>
wdenk5d3207d2002-08-21 22:08:56 +000021
wdenk5d3207d2002-08-21 22:08:56 +000022/* Local Static Functions */
Michal Simekf8c1be92014-03-13 12:49:21 +010023static int xilinx_validate(xilinx_desc *desc, char *fn);
wdenk5d3207d2002-08-21 22:08:56 +000024
25/* ------------------------------------------------------------------------- */
26
Goldschmidt Simon8b93a922017-11-10 14:17:41 +000027int fpga_is_partial_data(int devnum, size_t img_len)
28{
29 const fpga_desc * const desc = fpga_get_desc(devnum);
30 xilinx_desc *desc_xilinx = desc->devdesc;
31
32 /* Check datasize against FPGA size */
33 if (img_len >= desc_xilinx->size)
34 return 0;
35
36 /* datasize is smaller, must be partial data */
37 return 1;
38}
39
Michal Simek7a78bd22014-05-02 14:09:30 +020040int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
41 bitstream_type bstype)
Michal Simek52c20642013-04-26 13:12:07 +020042{
43 unsigned int length;
44 unsigned int swapsize;
Michal Simek52c20642013-04-26 13:12:07 +020045 unsigned char *dataptr;
46 unsigned int i;
Michal Simek6631db42013-04-26 15:04:48 +020047 const fpga_desc *desc;
Michal Simekf8c1be92014-03-13 12:49:21 +010048 xilinx_desc *xdesc;
Michal Simek52c20642013-04-26 13:12:07 +020049
50 dataptr = (unsigned char *)fpgadata;
Michal Simek6631db42013-04-26 15:04:48 +020051 /* Find out fpga_description */
52 desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
53 /* Assign xilinx device description */
54 xdesc = desc->devdesc;
Michal Simek52c20642013-04-26 13:12:07 +020055
56 /* skip the first bytes of the bitsteam, their meaning is unknown */
57 length = (*dataptr << 8) + *(dataptr + 1);
58 dataptr += 2;
59 dataptr += length;
60
61 /* get design name (identifier, length, string) */
62 length = (*dataptr << 8) + *(dataptr + 1);
63 dataptr += 2;
64 if (*dataptr++ != 0x61) {
65 debug("%s: Design name id not recognized in bitstream\n",
66 __func__);
67 return FPGA_FAIL;
68 }
69
70 length = (*dataptr << 8) + *(dataptr + 1);
71 dataptr += 2;
Siva Durga Prasad Paladugud8639092017-03-02 18:50:11 +053072 printf(" design filename = \"%s\"\n", dataptr);
73 dataptr += length;
Michal Simek52c20642013-04-26 13:12:07 +020074
75 /* get part number (identifier, length, string) */
76 if (*dataptr++ != 0x62) {
77 printf("%s: Part number id not recognized in bitstream\n",
78 __func__);
79 return FPGA_FAIL;
80 }
81
82 length = (*dataptr << 8) + *(dataptr + 1);
83 dataptr += 2;
Michal Simek6631db42013-04-26 15:04:48 +020084
85 if (xdesc->name) {
Siva Durga Prasad Paladugud8639092017-03-02 18:50:11 +053086 i = (ulong)strstr((char *)dataptr, xdesc->name);
Siva Durga Prasad Paladuguf7213262016-01-11 12:30:41 +053087 if (!i) {
Michal Simek6631db42013-04-26 15:04:48 +020088 printf("%s: Wrong bitstream ID for this device\n",
89 __func__);
90 printf("%s: Bitstream ID %s, current device ID %d/%s\n",
Siva Durga Prasad Paladugud8639092017-03-02 18:50:11 +053091 __func__, dataptr, devnum, xdesc->name);
Michal Simek6631db42013-04-26 15:04:48 +020092 return FPGA_FAIL;
93 }
94 } else {
Michal Simekf8c1be92014-03-13 12:49:21 +010095 printf("%s: Please fill correct device ID to xilinx_desc\n",
Michal Simek6631db42013-04-26 15:04:48 +020096 __func__);
97 }
Siva Durga Prasad Paladugud8639092017-03-02 18:50:11 +053098 printf(" part number = \"%s\"\n", dataptr);
99 dataptr += length;
Michal Simek52c20642013-04-26 13:12:07 +0200100
101 /* get date (identifier, length, string) */
102 if (*dataptr++ != 0x63) {
103 printf("%s: Date identifier not recognized in bitstream\n",
104 __func__);
105 return FPGA_FAIL;
106 }
107
108 length = (*dataptr << 8) + *(dataptr+1);
109 dataptr += 2;
Siva Durga Prasad Paladugud8639092017-03-02 18:50:11 +0530110 printf(" date = \"%s\"\n", dataptr);
111 dataptr += length;
Michal Simek52c20642013-04-26 13:12:07 +0200112
113 /* get time (identifier, length, string) */
114 if (*dataptr++ != 0x64) {
115 printf("%s: Time identifier not recognized in bitstream\n",
116 __func__);
117 return FPGA_FAIL;
118 }
119
120 length = (*dataptr << 8) + *(dataptr+1);
121 dataptr += 2;
Siva Durga Prasad Paladugud8639092017-03-02 18:50:11 +0530122 printf(" time = \"%s\"\n", dataptr);
123 dataptr += length;
Michal Simek52c20642013-04-26 13:12:07 +0200124
125 /* get fpga data length (identifier, length) */
126 if (*dataptr++ != 0x65) {
127 printf("%s: Data length id not recognized in bitstream\n",
128 __func__);
129 return FPGA_FAIL;
130 }
131 swapsize = ((unsigned int) *dataptr << 24) +
132 ((unsigned int) *(dataptr + 1) << 16) +
133 ((unsigned int) *(dataptr + 2) << 8) +
134 ((unsigned int) *(dataptr + 3));
135 dataptr += 4;
136 printf(" bytes in bitstream = %d\n", swapsize);
137
Oleksandr Suvorov282eed52022-07-22 17:16:07 +0300138 return fpga_load(devnum, dataptr, swapsize, bstype, 0);
Michal Simek52c20642013-04-26 13:12:07 +0200139}
140
Michal Simek7a78bd22014-05-02 14:09:30 +0200141int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
Oleksandr Suvorov7a9a0df2022-07-22 17:16:06 +0300142 bitstream_type bstype, int flags)
wdenk5d3207d2002-08-21 22:08:56 +0000143{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200144 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000145 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
Michal Simek14cfc4f2014-03-13 13:07:57 +0100146 return FPGA_FAIL;
147 }
wdenk5d3207d2002-08-21 22:08:56 +0000148
Michal Simek6cd68c82014-07-16 10:31:21 +0200149 if (!desc->operations || !desc->operations->load) {
150 printf("%s: Missing load operation\n", __func__);
151 return FPGA_FAIL;
152 }
153
Oleksandr Suvorov3e784812022-07-22 17:16:10 +0300154 return desc->operations->load(desc, buf, bsize, bstype, flags);
wdenk5d3207d2002-08-21 22:08:56 +0000155}
156
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530157#if defined(CONFIG_CMD_FPGA_LOADFS)
158int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
159 fpga_fs_info *fpga_fsinfo)
160{
161 if (!xilinx_validate(desc, (char *)__func__)) {
162 printf("%s: Invalid device descriptor\n", __func__);
163 return FPGA_FAIL;
164 }
165
Michal Simek6cd68c82014-07-16 10:31:21 +0200166 if (!desc->operations || !desc->operations->loadfs) {
167 printf("%s: Missing loadfs operation\n", __func__);
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530168 return FPGA_FAIL;
Michal Simek6cd68c82014-07-16 10:31:21 +0200169 }
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530170
171 return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
172}
173#endif
174
Oleksandr Suvorovfb2b8852022-07-22 17:16:02 +0300175#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
Siva Durga Prasad Paladugua18d09e2018-05-31 15:10:23 +0530176int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
177 struct fpga_secure_info *fpga_sec_info)
178{
179 if (!xilinx_validate(desc, (char *)__func__)) {
180 printf("%s: Invalid device descriptor\n", __func__);
181 return FPGA_FAIL;
182 }
183
184 if (!desc->operations || !desc->operations->loads) {
185 printf("%s: Missing loads operation\n", __func__);
186 return FPGA_FAIL;
187 }
188
189 return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
190}
191#endif
192
Michal Simekf8c1be92014-03-13 12:49:21 +0100193int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
wdenk5d3207d2002-08-21 22:08:56 +0000194{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200195 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000196 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
Michal Simek14cfc4f2014-03-13 13:07:57 +0100197 return FPGA_FAIL;
198 }
wdenk5d3207d2002-08-21 22:08:56 +0000199
Michal Simek6cd68c82014-07-16 10:31:21 +0200200 if (!desc->operations || !desc->operations->dump) {
201 printf("%s: Missing dump operation\n", __func__);
202 return FPGA_FAIL;
203 }
204
Michal Simek14cfc4f2014-03-13 13:07:57 +0100205 return desc->operations->dump(desc, buf, bsize);
wdenk5d3207d2002-08-21 22:08:56 +0000206}
207
Michal Simekf8c1be92014-03-13 12:49:21 +0100208int xilinx_info(xilinx_desc *desc)
wdenk5d3207d2002-08-21 22:08:56 +0000209{
210 int ret_val = FPGA_FAIL;
211
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200212 if (xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000213 printf ("Family: \t");
214 switch (desc->family) {
Michal Simekb625b9a2014-03-13 11:23:43 +0100215 case xilinx_spartan2:
wdenk5d3207d2002-08-21 22:08:56 +0000216 printf ("Spartan-II\n");
217 break;
Michal Simek2a6e3862014-03-13 11:28:42 +0100218 case xilinx_spartan3:
Wolfgang Denk875c7892005-09-25 16:44:21 +0200219 printf ("Spartan-III\n");
220 break;
Michal Simekd9071ce2014-03-13 11:33:36 +0100221 case xilinx_virtex2:
wdenk5d3207d2002-08-21 22:08:56 +0000222 printf ("Virtex-II\n");
223 break;
Michal Simekd5dae852013-04-22 15:43:02 +0200224 case xilinx_zynq:
225 printf("Zynq PL\n");
226 break;
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530227 case xilinx_zynqmp:
228 printf("ZynqMP PL\n");
229 break;
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +0530230 case xilinx_versal:
231 printf("Versal PL\n");
232 break;
233 /* Add new family types here */
wdenk5d3207d2002-08-21 22:08:56 +0000234 default:
235 printf ("Unknown family type, %d\n", desc->family);
236 }
237
238 printf ("Interface type:\t");
239 switch (desc->iface) {
240 case slave_serial:
241 printf ("Slave Serial\n");
242 break;
243 case master_serial: /* Not used */
244 printf ("Master Serial\n");
245 break;
246 case slave_parallel:
247 printf ("Slave Parallel\n");
248 break;
249 case jtag_mode: /* Not used */
250 printf ("JTAG Mode\n");
251 break;
252 case slave_selectmap:
253 printf ("Slave SelectMap Mode\n");
254 break;
255 case master_selectmap:
256 printf ("Master SelectMap Mode\n");
257 break;
Michal Simekd5dae852013-04-22 15:43:02 +0200258 case devcfg:
259 printf("Device configuration interface (Zynq)\n");
260 break;
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530261 case csu_dma:
262 printf("csu_dma configuration interface (ZynqMP)\n");
263 break;
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +0530264 case cfi:
265 printf("CFI configuration interface (Versal)\n");
266 break;
wdenk5d3207d2002-08-21 22:08:56 +0000267 /* Add new interface types here */
268 default:
269 printf ("Unsupported interface type, %d\n", desc->iface);
270 }
271
Simon Glassddc94372014-06-07 22:07:58 -0600272 printf("Device Size: \t%zd bytes\n"
273 "Cookie: \t0x%x (%d)\n",
274 desc->size, desc->cookie, desc->cookie);
Michal Simek6631db42013-04-26 15:04:48 +0200275 if (desc->name)
276 printf("Device name: \t%s\n", desc->name);
wdenk5d3207d2002-08-21 22:08:56 +0000277
Michal Simeke136eae2014-07-16 10:36:42 +0200278 if (desc->iface_fns)
wdenk5d3207d2002-08-21 22:08:56 +0000279 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
Michal Simeke136eae2014-07-16 10:36:42 +0200280 else
wdenk5d3207d2002-08-21 22:08:56 +0000281 printf ("No Device Function Table.\n");
282
Michal Simeke136eae2014-07-16 10:36:42 +0200283 if (desc->operations && desc->operations->info)
284 desc->operations->info(desc);
285
wdenk5d3207d2002-08-21 22:08:56 +0000286 ret_val = FPGA_SUCCESS;
287 } else {
288 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
289 }
290
291 return ret_val;
292}
293
wdenk5d3207d2002-08-21 22:08:56 +0000294/* ------------------------------------------------------------------------- */
295
Michal Simekf8c1be92014-03-13 12:49:21 +0100296static int xilinx_validate(xilinx_desc *desc, char *fn)
wdenk5d3207d2002-08-21 22:08:56 +0000297{
York Sun472d5462013-04-01 11:29:11 -0700298 int ret_val = false;
wdenk5d3207d2002-08-21 22:08:56 +0000299
300 if (desc) {
301 if ((desc->family > min_xilinx_type) &&
302 (desc->family < max_xilinx_type)) {
303 if ((desc->iface > min_xilinx_iface_type) &&
304 (desc->iface < max_xilinx_iface_type)) {
305 if (desc->size) {
York Sun472d5462013-04-01 11:29:11 -0700306 ret_val = true;
wdenk5d3207d2002-08-21 22:08:56 +0000307 } else
308 printf ("%s: NULL part size\n", fn);
309 } else
310 printf ("%s: Invalid Interface type, %d\n",
311 fn, desc->iface);
312 } else
313 printf ("%s: Invalid family type, %d\n", fn, desc->family);
314 } else
315 printf ("%s: NULL descriptor!\n", fn);
316
317 return ret_val;
318}