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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 85ffbbd51914925a542d8528be7f072e5ab02157 / . / cpu / mcf52x2 / start.S
blob: ba6b8843e42e37bb8b810e6a4ad0bc6d0201cbee [file] [log] [blame]
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]25#include <timestamp.h>
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]26#include "version.h"
27
28#ifndef CONFIG_IDENT_STRING
29#define CONFIG_IDENT_STRING ""
30#endif
31
32
33#define _START _start
34#define _FAULT _fault
35
36
37#define SAVE_ALL \
38 move.w #0x2700,%sr; /* disable intrs */ \
39 subl #60,%sp; /* space for 15 regs */ \
40 moveml %d0-%d7/%a0-%a6,%sp@; \
41
42#define RESTORE_ALL \
43 moveml %sp@,%d0-%d7/%a0-%a6; \
44 addl #60,%sp; /* space for 15 regs */ \
45 rte
46
47/* If we come from a pre-loader we don't need an initial exception
48 * table.
49 */
50#if !defined(CONFIG_MONITOR_IS_IN_RAM)
51
52.text
53/*
54 * Vector table. This is used for initial platform startup.
55 * These vectors are to catch any un-intended traps.
56 */
57_vectors:
58
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]59.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]60#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]61.long _start - TEXT_BASE
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]62#else
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]63.long _START
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]64#endif
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]65
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101
102#endif
103
104 .text
105
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]107#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]108 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]109 #if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]110 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
111 .long 0xFFFFFFFF /* all sectors protected */
112 .long 0x00000000 /* supervisor/User restriction */
113 .long 0x00000000 /* programm/data space restriction */
114 .long 0x00000000 /* Flash security */
115 #endif
116#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]117 .globl _start
118_start:
119 nop
120 nop
121 move.w #0x2700,%sr
122
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]123#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]124 move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]125 move.c %d0, %MBAR
126
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]127 /*** The 5249 has MBAR2 as well ***/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]128#ifdef CONFIG_SYS_MBAR2
129 move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]130 movec %d0, #0xc0e /* Set MBAR2 */
131#endif
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]133 move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]134 movec %d0, %RAMBAR0
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]135#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]136
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]137#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]138 /* Initialize IPSBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]139 move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]140 move.l %d0, 0x40000000
141
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]142 /* Initialize RAMBAR1: locate SRAM and validate it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]143 move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]144 movec %d0, %RAMBAR1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]145
Bartlomiej Siekadaa6e412006-12-20 00:27:32 +0100[diff] [blame]146#if defined(CONFIG_M5282)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]147#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]148 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]150 move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
151 move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
152 move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]153_copy_flash:
154 move.l (%a0)+, (%a2)+
155 cmp.l %a0, %a1
156 bgt.s _copy_flash
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]157 jmp CONFIG_SYS_INIT_RAM_ADDR
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]158
159_flashbar_setup:
160 /* Initialize FLASHBAR: locate internal Flash and validate it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]161 move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
TsiChung Liew43d60642008-03-13 14:26:32 -0500[diff] [blame]162 movec %d0, %FLASHBAR
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]163 jmp _after_flashbar_copy.L /* Force jump to absolute address */
164_flashbar_setup_end:
165 nop
166_after_flashbar_copy:
167#else
168 /* Setup code to initialize FLASHBAR, if start from external Memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]169 move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
TsiChung Liew4cb4e652008-08-11 15:54:25 +0000[diff] [blame]170 movec %d0, %FLASHBAR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]171#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]172
173#endif
Wolfgang Denk6741ae92006-09-04 01:03:57 +0200[diff] [blame]174#endif
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]175 /* if we come from a pre-loader we have no exception table and
176 * therefore no VBR to set
177 */
178#if !defined(CONFIG_MONITOR_IS_IN_RAM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]179#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
180 move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]181#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]182 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]183#endif
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]184 movec %d0, %VBR
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]185#endif
186
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]187#ifdef CONFIG_M5275
188 /* Initialize IPSBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]189 move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]190 move.l %d0, 0x40000000
191/* movec %d0, %MBAR */
192
193 /* Initialize RAMBAR: locate SRAM and validate it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]194 move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]195 movec %d0, %RAMBAR1
196#endif
197
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]198#if 0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]199 /* invalidate and disable cache */
200 move.l #0x01000000, %d0 /* Invalidate cache cmd */
201 movec %d0, %CACR /* Invalidate cache */
202 move.l #0, %d0
203 movec %d0, %ACR0
204 movec %d0, %ACR1
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]205#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]206
207 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]208 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]209 clr.l %sp@-
210
211 move.l #__got_start, %a5 /* put relocation table address to a5 */
212
213 bsr cpu_init_f /* run low-level CPU init code (from flash) */
214 bsr board_init_f /* run low-level board init code (from flash) */
215
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]216 /* board_init_f() does not return */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]217
218/*------------------------------------------------------------------------------*/
219
220/*
221 * void relocate_code (addr_sp, gd, addr_moni)
222 *
223 * This "function" does not return, instead it continues in RAM
224 * after relocating the monitor code.
225 *
226 * r3 = dest
227 * r4 = src
228 * r5 = length in bytes
229 * r6 = cachelinesize
230 */
231 .globl relocate_code
232relocate_code:
233 link.w %a6,#0
234 move.l 8(%a6), %sp /* set new stack pointer */
235
236 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
237 move.l 16(%a6), %a0 /* Save copy of Destination Address */
238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]239 move.l #CONFIG_SYS_MONITOR_BASE, %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]240 move.l #__init_end, %a2
241 move.l %a0, %a3
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]242 /* copy the code to RAM */
2431:
244 move.l (%a1)+, (%a3)+
245 cmp.l %a1,%a2
246 bgt.s 1b
247
248/*
249 * We are done. Do not return, instead branch to second part of board
250 * initialization, now running from RAM.
251 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]252 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]253 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]254 jmp (%a1)
255
256in_ram:
257
258clear_bss:
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]259 /*
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]260 * Now clear BSS segment
261 */
262 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]263 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]264 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]265 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]2666:
267 clr.l (%a1)+
268 cmp.l %a1,%d1
269 bgt.s 6b
270
271 /*
272 * fix got table in RAM
273 */
274 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]275 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]276 move.l %a1,%a5 /* * fix got pointer register a5 */
277
278 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]279 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]280
2817:
282 move.l (%a1),%d1
283 sub.l #_start,%d1
284 add.l %a0,%d1
285 move.l %d1,(%a1)+
286 cmp.l %a2, %a1
287 bne 7b
288
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]289#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
290 /* patch the 3 accesspoints to 3 ichache_state */
291 /* quick and dirty */
292
293 move.l %a0,%d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]294 add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]295 move.l %a0,%a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]296 add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]297 move.l %d1,(%a1)
298 move.l %a0,%a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]299 add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]300 move.l %d1,(%a1)
301 move.l %a0,%a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]302 add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]303 move.l %d1,(%a1)
304#endif
305
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]306 /* calculate relative jump to board_init_r in ram */
307 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]308 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]309
310 /* set parameters for board_init_r */
311 move.l %a0,-(%sp) /* dest_addr */
312 move.l %d0,-(%sp) /* gd */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]313#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
314 defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]315 halt
316#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]317 jsr (%a1)
318
319/*------------------------------------------------------------------------------*/
320/* exception code */
321 .globl _fault
322_fault:
323 jmp _fault
324
325 .globl _exc_handler
326_exc_handler:
327 SAVE_ALL
328 movel %sp,%sp@-
329 bsr exc_handler
330 addql #4,%sp
331 RESTORE_ALL
332
333 .globl _int_handler
334_int_handler:
335 SAVE_ALL
336 movel %sp,%sp@-
337 bsr int_handler
338 addql #4,%sp
339 RESTORE_ALL
340
341/*------------------------------------------------------------------------------*/
342/* cache functions */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]343#ifdef CONFIG_M5271
344 .globl icache_enable
345icache_enable:
346 move.l #0x01000000, %d0 /* Invalidate cache cmd */
347 movec %d0, %CACR /* Invalidate cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]348 move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]349 movec %d0, %ACR0 /* Enable cache */
350
351 move.l #0x80000200, %d0 /* Setup cache mask */
352 movec %d0, %CACR /* Enable cache */
353 nop
354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]355 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]356 moveq #1, %d0
357 move.l %d0, (%a1)
358 rts
359#endif
360
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]361#ifdef CONFIG_M5272
362 .globl icache_enable
363icache_enable:
364 move.l #0x01000000, %d0 /* Invalidate cache cmd */
365 movec %d0, %CACR /* Invalidate cache */
366 move.l #0x0000c000, %d0 /* Setup cache mask */
367 movec %d0, %ACR0 /* Enable cache */
368 move.l #0xff00c000, %d0 /* Setup cache mask */
369 movec %d0, %ACR1 /* Enable cache */
370 move.l #0x80000100, %d0 /* Setup cache mask */
371 movec %d0, %CACR /* Enable cache */
372 moveq #1, %d0
373 move.l %d0, icache_state
374 rts
375#endif
376
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]377#if defined(CONFIG_M5275)
378/*
379 * Instruction cache only
380 */
381 .globl icache_enable
382icache_enable:
383 move.l #0x01400000, %d0 /* Invalidate cache cmd */
384 movec %d0, %CACR /* Invalidate cache */
385 move.l #0x0000c000, %d0 /* Setup SDRAM caching */
386 movec %d0, %ACR0 /* Enable cache */
387 move.l #0x00000000, %d0 /* No other caching */
388 movec %d0, %ACR1 /* Enable cache */
389 move.l #0x80400100, %d0 /* Setup cache mask */
390 movec %d0, %CACR /* Enable cache */
391 moveq #1, %d0
392 move.l %d0, icache_state
393 rts
394#endif
395
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]396#ifdef CONFIG_M5282
397 .globl icache_enable
398icache_enable:
399 move.l #0x01000000, %d0 /* Invalidate cache cmd */
400 movec %d0, %CACR /* Invalidate cache */
401 move.l #0x0000c000, %d0 /* Setup cache mask */
402 movec %d0, %ACR0 /* Enable cache */
403 move.l #0xff00c000, %d0 /* Setup cache mask */
404 movec %d0, %ACR1 /* Enable cache */
405 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
406 movec %d0, %CACR /* Enable cache */
407 moveq #1, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]408icache_state_access_1:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]409 move.l %d0, icache_state
410 rts
411#endif
412
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]413#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]414 .globl icache_enable
415icache_enable:
416 /*
417 * Note: The 5249 Documentation doesn't give a bit position for CINV!
418 * From the 5272 and the 5307 documentation, I have deduced that it is
419 * probably CACR[24]. Should someone say something to Motorola?
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]420 * ~Jeremy
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]421 */
422 move.l #0x01000000, %d0 /* Invalidate whole cache */
423 move.c %d0,%CACR
424 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
425 move.c %d0, %ACR0
426 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
427 move.c %d0, %ACR1
428 move.l #0x90000200, %d0 /* Set cache enable cmd */
429 move.c %d0,%CACR
430 moveq #1, %d0
431 move.l %d0, icache_state
432 rts
433#endif
434
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]435 .globl icache_disable
436icache_disable:
437 move.l #0x00000100, %d0 /* Setup cache mask */
438 movec %d0, %CACR /* Enable cache */
439 clr.l %d0 /* Setup cache mask */
440 movec %d0, %ACR0 /* Enable cache */
441 movec %d0, %ACR1 /* Enable cache */
442 moveq #0, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]443icache_state_access_2:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]444 move.l %d0, icache_state
445 rts
446
447 .globl icache_status
448icache_status:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]449icache_state_access_3:
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]450 move.l #(icache_state), %a0
451 move.l (%a0), %d0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]452 rts
453
454 .data
455icache_state:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]456 .long 0 /* cache is diabled on inirialization */
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]457
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]458 .globl dcache_enable
459dcache_enable:
460 /* dummy function */
461 rts
462
463 .globl dcache_disable
464dcache_disable:
465 /* dummy function */
466 rts
467
468 .globl dcache_status
469dcache_status:
470 /* dummy function */
471 rts
472
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]473/*------------------------------------------------------------------------------*/
474
475 .globl version_string
476version_string:
477 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]478 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]479 .ascii CONFIG_IDENT_STRING, "\0"
TsiChung Liew9b464322008-03-28 08:47:45 -0500[diff] [blame]480 .align 4