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wdenkc00b5f82002-11-03 11:12:02 +00001/*----------------------------------------------------------------------------+
Josh Boyer31773492009-08-07 13:53:20 -04002| This source code is dual-licensed. You may use it under the terms of the
3| GNU General Public License version 2, or under the license below.
wdenkc00b5f82002-11-03 11:12:02 +00004|
wdenkba56f622004-02-06 23:19:44 +00005| This source code has been made available to you by IBM on an AS-IS
6| basis. Anyone receiving this source is licensed under IBM
7| copyrights to use it in any way he or she deems fit, including
8| copying it, modifying it, compiling it, and redistributing it either
9| with or without modifications. No license under IBM patents or
10| patent applications is to be implied by the copyright license.
wdenkc00b5f82002-11-03 11:12:02 +000011|
wdenkba56f622004-02-06 23:19:44 +000012| Any user of this software should understand that IBM cannot provide
13| technical support for this software and will not be responsible for
14| any consequences resulting from the use of this software.
wdenkc00b5f82002-11-03 11:12:02 +000015|
wdenkba56f622004-02-06 23:19:44 +000016| Any person who transfers this source code or any derivative work
17| must include the IBM copyright notice, this paragraph, and the
18| preceding two paragraphs in the transferred software.
wdenkc00b5f82002-11-03 11:12:02 +000019|
wdenkba56f622004-02-06 23:19:44 +000020| COPYRIGHT I B M CORPORATION 1999
21| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkc00b5f82002-11-03 11:12:02 +000022+----------------------------------------------------------------------------*/
23
Larry Johnsonc46f5332007-12-22 15:15:13 -050024/*
25 * (C) Copyright 2006
26 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
27 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
28 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
29 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
30 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
31 *
32 * This program is free software; you can redistribute it and/or
33 * modify it under the terms of the GNU General Public License as
34 * published by the Free Software Foundation; either version 2 of
35 * the License, or (at your option) any later version.
36 *
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
41 *
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
45 * MA 02111-1307 USA
46 */
47
wdenkba56f622004-02-06 23:19:44 +000048#ifndef __PPC440_H__
wdenkc00b5f82002-11-03 11:12:02 +000049#define __PPC440_H__
50
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
Stefan Roese9b94ac62007-10-31 17:55:58 +010052
wdenkc00b5f82002-11-03 11:12:02 +000053/******************************************************************************
54 * DCRs & Related
55 ******************************************************************************/
56
57/*-----------------------------------------------------------------------------
wdenkba56f622004-02-06 23:19:44 +000058 | Clocking Controller
59 +----------------------------------------------------------------------------*/
wdenkba56f622004-02-06 23:19:44 +000060/* values for clkcfga register - indirect addressing of these regs */
61#define clk_clkukpd 0x0020
62#define clk_pllc 0x0040
63#define clk_plld 0x0060
64#define clk_primad 0x0080
65#define clk_primbd 0x00a0
66#define clk_opbd 0x00c0
67#define clk_perd 0x00e0
68#define clk_mald 0x0100
Wolfgang Denk1636d1c2007-06-22 23:59:00 +020069#define clk_spcid 0x0120
wdenkba56f622004-02-06 23:19:44 +000070#define clk_icfg 0x0140
71
72/* 440gx sdr register definations */
wdenkba56f622004-02-06 23:19:44 +000073#define sdr_sdstp0 0x0020 /* */
74#define sdr_sdstp1 0x0021 /* */
Stefan Roese90e6f412007-04-18 12:05:59 +020075#define SDR_PINSTP 0x0040
wdenkba56f622004-02-06 23:19:44 +000076#define sdr_sdcs 0x0060
77#define sdr_ecid0 0x0080
78#define sdr_ecid1 0x0081
79#define sdr_ecid2 0x0082
80#define sdr_jtag 0x00c0
Steven A. Falco711e2b22008-11-20 14:37:57 -050081#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
82#define SDR0_DDRCFG 0x00e0
83#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
wdenkba56f622004-02-06 23:19:44 +000084#define sdr_ebc 0x0100
85#define sdr_uart0 0x0120 /* UART0 Config */
86#define sdr_uart1 0x0121 /* UART1 Config */
Stefan Roesec157d8e2005-08-01 16:41:48 +020087#define sdr_uart2 0x0122 /* UART2 Config */
88#define sdr_uart3 0x0123 /* UART3 Config */
wdenkba56f622004-02-06 23:19:44 +000089#define sdr_cp440 0x0180
90#define sdr_xcr 0x01c0
91#define sdr_xpllc 0x01c1
92#define sdr_xplld 0x01c2
93#define sdr_srst 0x0200
94#define sdr_slpipe 0x0220
Stefan Roesec157d8e2005-08-01 16:41:48 +020095#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
96#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
wdenkba56f622004-02-06 23:19:44 +000097#define sdr_mirq0 0x0260
98#define sdr_mirq1 0x0261
99#define sdr_maltbl 0x0280
100#define sdr_malrbl 0x02a0
101#define sdr_maltbs 0x02c0
102#define sdr_malrbs 0x02e0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200103#define sdr_pci0 0x0300
104#define sdr_usb0 0x0320
wdenkba56f622004-02-06 23:19:44 +0000105#define sdr_cust0 0x4000
wdenkba56f622004-02-06 23:19:44 +0000106#define sdr_cust1 0x4002
wdenkba56f622004-02-06 23:19:44 +0000107#define sdr_pfc0 0x4100 /* Pin Function 0 */
108#define sdr_pfc1 0x4101 /* Pin Function 1 */
109#define sdr_plbtr 0x4200
110#define sdr_mfr 0x4300 /* SDR0_MFR reg */
111
Marian Balakowiczbba68372006-06-30 18:35:04 +0200112#ifdef CONFIG_440GX
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200113#define sdr_amp 0x0240
114#define sdr_xpllc 0x01c1
115#define sdr_xplld 0x01c2
116#define sdr_xcr 0x01c0
117#define sdr_sdstp2 0x4001
118#define sdr_sdstp3 0x4003
Marian Balakowiczbba68372006-06-30 18:35:04 +0200119#endif /* CONFIG_440GX */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200120
Igor Lisitsina11e0692007-03-28 19:06:19 +0400121/*----------------------------------------------------------------------------+
122| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
123+----------------------------------------------------------------------------*/
124#define CCR0_PRE 0x40000000
125#define CCR0_CRPE 0x08000000
126#define CCR0_DSTG 0x00200000
127#define CCR0_DAPUIB 0x00100000
128#define CCR0_DTB 0x00008000
129#define CCR0_GICBT 0x00004000
130#define CCR0_GDCBT 0x00002000
131#define CCR0_FLSTA 0x00000100
132#define CCR0_ICSLC_MASK 0x0000000C
133#define CCR0_ICSLT_MASK 0x00000003
134#define CCR1_TCS_MASK 0x00000080
135#define CCR1_TCS_INTCLK 0x00000000
136#define CCR1_TCS_EXTCLK 0x00000080
137#define MMUCR_SWOA 0x01000000
138#define MMUCR_U1TE 0x00400000
139#define MMUCR_U2SWOAE 0x00200000
140#define MMUCR_DULXE 0x00800000
141#define MMUCR_IULXE 0x00400000
142#define MMUCR_STS 0x00100000
143#define MMUCR_STID_MASK 0x000000FF
Igor Lisitsina11e0692007-03-28 19:06:19 +0400144
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200145#ifdef CONFIG_440SPE
146#undef sdr_sdstp2
147#define sdr_sdstp2 0x0022
148#undef sdr_sdstp3
149#define sdr_sdstp3 0x0023
150#define sdr_ddr0 0x00E1
151#define sdr_uart2 0x0122
152#define sdr_xcr0 0x01c0
153/* #define sdr_xcr1 0x01c3 only one PCIX - SG */
154/* #define sdr_xcr2 0x01c6 only one PCIX - SG */
155#define sdr_xpllc0 0x01c1
156#define sdr_xplld0 0x01c2
157#define sdr_xpllc1 0x01c4 /*notRCW - SG */
158#define sdr_xplld1 0x01c5 /*notRCW - SG */
159#define sdr_xpllc2 0x01c7 /*notRCW - SG */
160#define sdr_xplld2 0x01c8 /*notRCW - SG */
161#define sdr_amp0 0x0240
162#define sdr_amp1 0x0241
163#define sdr_cust2 0x4004
164#define sdr_cust3 0x4006
165#define sdr_sdstp4 0x4001
166#define sdr_sdstp5 0x4003
167#define sdr_sdstp6 0x4005
168#define sdr_sdstp7 0x4007
169
Stefan Roesedf294492007-03-08 10:06:09 +0100170#endif /* CONFIG_440SPE */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200171
wdenkc00b5f82002-11-03 11:12:02 +0000172/*-----------------------------------------------------------------------------
Wolfgang Denk6ed6ce62005-09-25 16:01:42 +0200173 | External Bus Controller
wdenkc00b5f82002-11-03 11:12:02 +0000174 +----------------------------------------------------------------------------*/
wdenkba56f622004-02-06 23:19:44 +0000175/* values for ebccfga register - indirect addressing of these regs */
176#define pb0cr 0x00 /* periph bank 0 config reg */
177#define pb1cr 0x01 /* periph bank 1 config reg */
178#define pb2cr 0x02 /* periph bank 2 config reg */
179#define pb3cr 0x03 /* periph bank 3 config reg */
180#define pb4cr 0x04 /* periph bank 4 config reg */
181#define pb5cr 0x05 /* periph bank 5 config reg */
182#define pb6cr 0x06 /* periph bank 6 config reg */
183#define pb7cr 0x07 /* periph bank 7 config reg */
184#define pb0ap 0x10 /* periph bank 0 access parameters */
185#define pb1ap 0x11 /* periph bank 1 access parameters */
186#define pb2ap 0x12 /* periph bank 2 access parameters */
187#define pb3ap 0x13 /* periph bank 3 access parameters */
188#define pb4ap 0x14 /* periph bank 4 access parameters */
189#define pb5ap 0x15 /* periph bank 5 access parameters */
190#define pb6ap 0x16 /* periph bank 6 access parameters */
191#define pb7ap 0x17 /* periph bank 7 access parameters */
192#define pbear 0x20 /* periph bus error addr reg */
193#define pbesr 0x21 /* periph bus error status reg */
194#define xbcfg 0x23 /* external bus configuration reg */
Stefan Roese4745aca2007-02-20 10:57:08 +0100195#define EBC0_CFG 0x23 /* external bus configuration reg */
Wolfgang Denk6ed6ce62005-09-25 16:01:42 +0200196#define xbcid 0x24 /* external bus core id reg */
wdenkc00b5f82002-11-03 11:12:02 +0000197
Stefan Roese887e2ec2006-09-07 11:51:23 +0200198#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
199 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200200
201/* PLB4 to PLB3 Bridge OUT */
202#define P4P3_DCR_BASE 0x020
203#define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
204#define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
205#define p4p3_eadr (P4P3_DCR_BASE+0x2)
206#define p4p3_euadr (P4P3_DCR_BASE+0x3)
207#define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
208#define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
209#define p4p3_confg (P4P3_DCR_BASE+0x6)
210#define p4p3_pic (P4P3_DCR_BASE+0x7)
211#define p4p3_peir (P4P3_DCR_BASE+0x8)
212#define p4p3_rev (P4P3_DCR_BASE+0xA)
213
214/* PLB3 to PLB4 Bridge IN */
215#define P3P4_DCR_BASE 0x030
216#define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
217#define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
218#define p3p4_eadr (P3P4_DCR_BASE+0x2)
219#define p3p4_euadr (P3P4_DCR_BASE+0x3)
220#define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
221#define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
222#define p3p4_confg (P3P4_DCR_BASE+0x6)
223#define p3p4_pic (P3P4_DCR_BASE+0x7)
224#define p3p4_peir (P3P4_DCR_BASE+0x8)
225#define p3p4_rev (P3P4_DCR_BASE+0xA)
226
227/* PLB3 Arbiter */
228#define PLB3_DCR_BASE 0x070
229#define plb3_revid (PLB3_DCR_BASE+0x2)
230#define plb3_besr (PLB3_DCR_BASE+0x3)
231#define plb3_bear (PLB3_DCR_BASE+0x6)
232#define plb3_acr (PLB3_DCR_BASE+0x7)
233
234/* PLB4 Arbiter - PowerPC440EP Pass1 */
235#define PLB4_DCR_BASE 0x080
Stefan Roesea78bc442007-01-05 10:40:36 +0100236#define plb4_acr (PLB4_DCR_BASE+0x1)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200237#define plb4_revid (PLB4_DCR_BASE+0x2)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200238#define plb4_besr (PLB4_DCR_BASE+0x4)
239#define plb4_bearl (PLB4_DCR_BASE+0x6)
240#define plb4_bearh (PLB4_DCR_BASE+0x7)
241
Stefan Roesea78bc442007-01-05 10:40:36 +0100242#define PLB4_ACR_WRP (0x80000000 >> 7)
243
Stefan Roese17f50f222005-08-04 17:09:16 +0200244/* Pin Function Control Register 1 */
245#define SDR0_PFC1 0x4101
246#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
247#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
248#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
249#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
250#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
251#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
252#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
253#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
254#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
255#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
256#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
257#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
258#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
259#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
260#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
261#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
262#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
263#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
264#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
265#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
266#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
267#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
268#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
269#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
270
271#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
272#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
273#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
274#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
275
276/* USB Control Register */
277#define SDR0_USB0 0x0320
278#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
279#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
280#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
281#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
282#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
283#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
284
Stefan Roese887e2ec2006-09-07 11:51:23 +0200285/* Miscealleneaous Function Reg. */
286#define SDR0_MFR 0x4300
287#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
288#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
289#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
290#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
291#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
292#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
293#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
294#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
295#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
296#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
297#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
298#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
299#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
300
301#define SDR0_MFR_ERRATA3_EN0 0x00800000
302#define SDR0_MFR_ERRATA3_EN1 0x00400000
303#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
304#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
305#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
306#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
307#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
308
Stefan Roese8f24e062008-01-09 10:28:20 +0100309#define GPT0_COMP6 0x00000098
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100310#define GPT0_COMP5 0x00000094
311#define GPT0_COMP4 0x00000090
312#define GPT0_COMP3 0x0000008C
Yuri Tikhonov3d610182008-02-06 18:48:36 +0100313#define GPT0_COMP2 0x00000088
314#define GPT0_COMP1 0x00000084
Stefan Roese887e2ec2006-09-07 11:51:23 +0200315
Yuri Tikhonoveb0615b2008-04-24 10:30:53 +0200316#define GPT0_MASK6 0x000000D8
317#define GPT0_MASK5 0x000000D4
318#define GPT0_MASK4 0x000000D0
319#define GPT0_MASK3 0x000000CC
320#define GPT0_MASK2 0x000000C8
321#define GPT0_MASK1 0x000000C4
322
Stefan Roese887e2ec2006-09-07 11:51:23 +0200323#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Niklaus Gigerf780b832007-06-27 18:11:38 +0200324#define SDR0_USB2D0CR 0x0320
Stefan Roese887e2ec2006-09-07 11:51:23 +0200325#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
326#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
327#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
328
329#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
330#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
331#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
332
333#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
334#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
335#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
336
337/* USB2 Host Control Register */
338#define SDR0_USB2H0CR 0x0340
339#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
340#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
341#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
342#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
343
344/* Pin Function Control Register 1 */
345#define SDR0_PFC1 0x4101
346#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
347#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
348#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
349
350#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
351#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
352#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
353#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
354#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
355#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
356#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
357#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
358
359#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
360#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
361#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
362#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
363#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
364#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
365#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
366#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
367#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
368#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
369#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
370#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
371#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
372#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
373#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
374#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
375#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
376#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
377#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
378#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
379#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
380
381#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
382#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
383#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
384#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
385
386/* Ethernet PLL Configuration Register */
387#define SDR0_PFC2 0x4102
388#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
389#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
390#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
391#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
392
393#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
394#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
395#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
396#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
397#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
398#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
399#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
400#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
401
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200402#define SDR0_PFC4 0x4104
403
Stefan Roese887e2ec2006-09-07 11:51:23 +0200404/* USB2PHY0 Control Register */
405#define SDR0_USB2PHY0CR 0x4103
406#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
407#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
408#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
409
410#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
411#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
412#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
413
414#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
415#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
416#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
417
418#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
419#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
420#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
421
422#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
423#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
424#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
425
426#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
427#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
428#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
429
430#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
431#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
432#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
433
434#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
435#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
436#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
437
438#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
439#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
440#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
441
442#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
443#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
444#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
445#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
446
447/* Miscealleneaous Function Reg. */
448#define SDR0_MFR 0x4300
449#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
450#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
451#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
452#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
453#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
454#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
455#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
456#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
457#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
458#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
459#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
460
461#define SDR0_MFR_ERRATA3_EN0 0x00800000
462#define SDR0_MFR_ERRATA3_EN1 0x00400000
463#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
464#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
465#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
466#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
467#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
468
469#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
470
Stefan Roese17f50f222005-08-04 17:09:16 +0200471/* CUST1 Customer Configuration Register1 */
472#define SDR0_CUST1 0x4002
473#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
474#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
475#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
476
477/* Pin Function Control Register 0 */
478#define SDR0_PFC0 0x4100
479#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
480#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
481#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
482#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
483#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
484
485/* Pin Function Control Register 1 */
486#define SDR0_PFC1 0x4101
487#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
488#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
489#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
490#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
491#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
492#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
493#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
494#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
495#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
496#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
497#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
498#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
499#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
500#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
501#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
502#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
503#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
504#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
505#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
506#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
507#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
508#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
509#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
510#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
511
512#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
513#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
514#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
515#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
516
Stefan Roese43c60992008-03-11 15:11:43 +0100517#endif /* 440EP || 440GR || 440EPX || 440GRX */
518
Stefan Roese43c60992008-03-11 15:11:43 +0100519#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
520 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
521 defined(CONFIG_460EX) || defined(CONFIG_460GT)
522/* CUST0 Customer Configuration Register0 */
523#define SDR0_CUST0 0x4000
524#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
525#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
526#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
527#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
wdenkba56f622004-02-06 23:19:44 +0000528
Stefan Roese43c60992008-03-11 15:11:43 +0100529#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
530#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
531#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
532
533#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
534#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
535#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
536
537#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
538#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
539#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
540
541#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
542#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
543#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
544
545#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
546#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
547#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
548
549#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
550#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
551#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
552
553#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
554#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
555#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
556
557#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
558#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
559#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
560#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
561#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
562#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
563#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
564#endif
wdenkc00b5f82002-11-03 11:12:02 +0000565
566/*-----------------------------------------------------------------------------
567 | On-Chip Buses
568 +----------------------------------------------------------------------------*/
569/* TODO: as needed */
570
571/*-----------------------------------------------------------------------------
572 | Clocking, Power Management and Chip Control
573 +----------------------------------------------------------------------------*/
Feng Kan96e5fc02008-07-08 22:48:07 -0700574#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
575 defined(CONFIG_460SX)
Stefan Roese43c60992008-03-11 15:11:43 +0100576#define CNTRL_DCR_BASE 0x160
577#else
wdenkc00b5f82002-11-03 11:12:02 +0000578#define CNTRL_DCR_BASE 0x0b0
Stefan Roese43c60992008-03-11 15:11:43 +0100579#endif
Eugene O'Brien5b2052e2008-04-11 10:00:35 -0400580
wdenk63153492005-04-03 20:55:38 +0000581#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
582#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
583#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
wdenkc00b5f82002-11-03 11:12:02 +0000584
wdenk63153492005-04-03 20:55:38 +0000585#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
586#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
587#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
588#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000589
590#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
591#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
592#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
593#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
594
Stefan Roese5568e612005-11-22 13:20:42 +0100595#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
596
wdenk63153492005-04-03 20:55:38 +0000597#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
598#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
wdenkc00b5f82002-11-03 11:12:02 +0000599
wdenkc00b5f82002-11-03 11:12:02 +0000600/*-----------------------------------------------------------------------------
601 | DMA
602 +----------------------------------------------------------------------------*/
Stefan Roese43c60992008-03-11 15:11:43 +0100603#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
604#define DMA_DCR_BASE 0x200
605#else
wdenkc00b5f82002-11-03 11:12:02 +0000606#define DMA_DCR_BASE 0x100
Stefan Roese43c60992008-03-11 15:11:43 +0100607#endif
wdenkba56f622004-02-06 23:19:44 +0000608#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
609#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
610#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
611#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
612#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
613#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
wdenkc00b5f82002-11-03 11:12:02 +0000614#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
615#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
wdenkba56f622004-02-06 23:19:44 +0000616#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
617#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
618#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
619#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
620#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
621#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000622#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
623#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
wdenkba56f622004-02-06 23:19:44 +0000624#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
625#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
626#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
627#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
628#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
629#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +0000630#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
631#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
wdenkba56f622004-02-06 23:19:44 +0000632#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
633#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
634#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
635#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
636#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
637#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +0000638#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
639#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
wdenkba56f622004-02-06 23:19:44 +0000640#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
641#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
642#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
643#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
wdenkc00b5f82002-11-03 11:12:02 +0000644
645/*-----------------------------------------------------------------------------
646 | Memory Access Layer
647 +----------------------------------------------------------------------------*/
648#define MAL_DCR_BASE 0x180
wdenkba56f622004-02-06 23:19:44 +0000649#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
650#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
651#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
652#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
653#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +0000654#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
655#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
wdenkba56f622004-02-06 23:19:44 +0000656#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
657#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
658#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
659#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +0000660#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
661#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
wdenkba56f622004-02-06 23:19:44 +0000662#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
663#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
664#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
wdenkc00b5f82002-11-03 11:12:02 +0000665#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
666#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000667#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
668#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
wdenkc00b5f82002-11-03 11:12:02 +0000669#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
670#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000671#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
672#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
Stefan Roese43c60992008-03-11 15:11:43 +0100673#if defined(CONFIG_440GX) || \
674 defined(CONFIG_460EX) || defined(CONFIG_460GT)
675#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
676#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
677#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100678#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
679#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000680#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
681#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
Stefan Roese43c60992008-03-11 15:11:43 +0100682#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100683#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
684#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200685#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +0000686
wdenkc00b5f82002-11-03 11:12:02 +0000687/*-----------------------------------------------------------------------------+
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100688| SDR0 Bit Settings
wdenk0e6d7982004-03-14 00:07:33 +0000689+-----------------------------------------------------------------------------*/
Stefan Roesedf294492007-03-08 10:06:09 +0100690#if defined(CONFIG_440SP)
691#define SDR0_SRST 0x0200
692
693#define SDR0_DDR0 0x00E1
694#define SDR0_DDR0_DPLLRST 0x80000000
695#define SDR0_DDR0_DDRM_MASK 0x60000000
696#define SDR0_DDR0_DDRM_DDR1 0x20000000
697#define SDR0_DDR0_DDRM_DDR2 0x40000000
698#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
699#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
700#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
701#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
702#endif
703
Feng Kan96e5fc02008-07-08 22:48:07 -0700704#if defined(CONFIG_440SPE) || defined(CONFIG_460SX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200705#define SDR0_CP440 0x0180
706#define SDR0_CP440_ERPN_MASK 0x30000000
707#define SDR0_CP440_ERPN_MASK_HI 0x3000
708#define SDR0_CP440_ERPN_MASK_LO 0x0000
709#define SDR0_CP440_ERPN_EBC 0x10000000
710#define SDR0_CP440_ERPN_EBC_HI 0x1000
711#define SDR0_CP440_ERPN_EBC_LO 0x0000
712#define SDR0_CP440_ERPN_PCI 0x20000000
713#define SDR0_CP440_ERPN_PCI_HI 0x2000
714#define SDR0_CP440_ERPN_PCI_LO 0x0000
715#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
716#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
717#define SDR0_CP440_NTO1_MASK 0x00000002
718#define SDR0_CP440_NTO1_NTOP 0x00000000
719#define SDR0_CP440_NTO1_NTO1 0x00000002
720#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
721#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200722
723#define SDR0_SDSTP0 0x0020
724#define SDR0_SDSTP0_ENG_MASK 0x80000000
725#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
726#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
727#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
728#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
729#define SDR0_SDSTP0_SRC_MASK 0x40000000
730#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
731#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
732#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
733#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
734#define SDR0_SDSTP0_SEL_MASK 0x38000000
735#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
736#define SDR0_SDSTP0_SEL_CPU 0x08000000
737#define SDR0_SDSTP0_SEL_EBC 0x28000000
738#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
739#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
740#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
741#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
742#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
743#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
744#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
745#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
746#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
747#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
748#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
749#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
750#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
751#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
752#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
753#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
754#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
755#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
756#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
757#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
758
759
760#define SDR0_SDSTP1 0x0021
761#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
762#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
763#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
764#define SDR0_SDSTP1_PERDV0_MASK 0x03000000
765#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
766#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
767#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
768#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
769#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
770#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
771#define SDR0_SDSTP1_DDR1_MODE 0x00100000
772#define SDR0_SDSTP1_DDR2_MODE 0x00200000
773#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
774#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
775#define SDR0_SDSTP1_ERPN_MASK 0x00080000
776#define SDR0_SDSTP1_ERPN_EBC 0x00000000
777#define SDR0_SDSTP1_ERPN_PCI 0x00080000
778#define SDR0_SDSTP1_PAE_MASK 0x00040000
779#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
780#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
781#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
782#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
783#define SDR0_SDSTP1_PHCE_MASK 0x00020000
784#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
785#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
786#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
787#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
788#define SDR0_SDSTP1_PISE_MASK 0x00010000
789#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
790#define SDR0_SDSTP1_PISE_ENABLE 0x00001000
791#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
792#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
793#define SDR0_SDSTP1_PCWE_MASK 0x00008000
794#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
795#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
796#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
797#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
798#define SDR0_SDSTP1_PPIM_MASK 0x00007800
799#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
800#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
801#define SDR0_SDSTP1_PR64E_MASK 0x00000400
802#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
803#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
804#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
805#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
806#define SDR0_SDSTP1_PXFS_MASK 0x00000300
807#define SDR0_SDSTP1_PXFS_100_133 0x00000000
808#define SDR0_SDSTP1_PXFS_66_100 0x00000100
809#define SDR0_SDSTP1_PXFS_50_66 0x00000200
810#define SDR0_SDSTP1_PXFS_0_50 0x00000300
811#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
812#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
813#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
814#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
815#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
816#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
817#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
818#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
819#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
820#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
821#define SDR0_SDSTP1_ETH_MASK 0x00000004
822#define SDR0_SDSTP1_ETH_10_100 0x00000000
823#define SDR0_SDSTP1_ETH_GIGA 0x00000004
824#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
825#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
826#define SDR0_SDSTP1_NTO1_MASK 0x00000001
827#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
828#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
829#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
830#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
831
832#define SDR0_SDSTP2 0x0022
833#define SDR0_SDSTP2_P1AE_MASK 0x80000000
834#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
835#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
836#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
837#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
838#define SDR0_SDSTP2_P1HCE_MASK 0x40000000
839#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
840#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
841#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
842#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
843#define SDR0_SDSTP2_P1ISE_MASK 0x20000000
844#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
845#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
846#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
847#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
848#define SDR0_SDSTP2_P1CWE_MASK 0x10000000
849#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
850#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
851#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
852#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
853#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
854#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
855#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
856#define SDR0_SDSTP2_P1R64E_MASK 0x00800000
857#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
858#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
859#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
860#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
861#define SDR0_SDSTP2_P1XFS_MASK 0x00600000
862#define SDR0_SDSTP2_P1XFS_100_133 0x00000000
863#define SDR0_SDSTP2_P1XFS_66_100 0x00200000
864#define SDR0_SDSTP2_P1XFS_50_66 0x00400000
865#define SDR0_SDSTP2_P1XFS_0_50 0x00600000
866#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
867#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
868#define SDR0_SDSTP2_P2AE_MASK 0x00040000
869#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
870#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
871#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
872#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
873#define SDR0_SDSTP2_P2HCE_MASK 0x00020000
874#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
875#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
876#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
877#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
878#define SDR0_SDSTP2_P2ISE_MASK 0x00010000
879#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
880#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
881#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
882#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
883#define SDR0_SDSTP2_P2CWE_MASK 0x00008000
884#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
885#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
886#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
887#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
888#define SDR0_SDSTP2_P2PIM_MASK 0x00007800
889#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
890#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
891#define SDR0_SDSTP2_P2XFS_MASK 0x00000300
892#define SDR0_SDSTP2_P2XFS_100_133 0x00000000
893#define SDR0_SDSTP2_P2XFS_66_100 0x00000100
894#define SDR0_SDSTP2_P2XFS_50_66 0x00000200
895#define SDR0_SDSTP2_P2XFS_0_50 0x00000100
896#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
897#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
898
899#define SDR0_SDSTP3 0x0023
900
901#define SDR0_PINSTP 0x0040
902#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
903#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
904#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
905#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
906#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
907#define SDR0_SDCS 0x0060
908#define SDR0_ECID0 0x0080
909#define SDR0_ECID1 0x0081
910#define SDR0_ECID2 0x0082
911#define SDR0_JTAG 0x00C0
912
913#define SDR0_DDR0 0x00E1
914#define SDR0_DDR0_DPLLRST 0x80000000
915#define SDR0_DDR0_DDRM_MASK 0x60000000
916#define SDR0_DDR0_DDRM_DDR1 0x20000000
917#define SDR0_DDR0_DDRM_DDR2 0x40000000
918#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
919#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
920#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
921#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
922
923#define SDR0_UART0 0x0120
924#define SDR0_UART1 0x0121
925#define SDR0_UART2 0x0122
926#define SDR0_UARTX_UXICS_MASK 0xF0000000
927#define SDR0_UARTX_UXICS_PLB 0x20000000
928#define SDR0_UARTX_UXEC_MASK 0x00800000
929#define SDR0_UARTX_UXEC_INT 0x00000000
930#define SDR0_UARTX_UXEC_EXT 0x00800000
931#define SDR0_UARTX_UXDIV_MASK 0x000000FF
932#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
933#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
934
935#define SDR0_CP440 0x0180
936#define SDR0_CP440_ERPN_MASK 0x30000000
937#define SDR0_CP440_ERPN_MASK_HI 0x3000
938#define SDR0_CP440_ERPN_MASK_LO 0x0000
939#define SDR0_CP440_ERPN_EBC 0x10000000
940#define SDR0_CP440_ERPN_EBC_HI 0x1000
941#define SDR0_CP440_ERPN_EBC_LO 0x0000
942#define SDR0_CP440_ERPN_PCI 0x20000000
943#define SDR0_CP440_ERPN_PCI_HI 0x2000
944#define SDR0_CP440_ERPN_PCI_LO 0x0000
945#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
946#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
947#define SDR0_CP440_NTO1_MASK 0x00000002
948#define SDR0_CP440_NTO1_NTOP 0x00000000
949#define SDR0_CP440_NTO1_NTO1 0x00000002
950#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
951#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
952
953#define SDR0_XCR0 0x01C0
954#define SDR0_XCR1 0x01C3
955#define SDR0_XCR2 0x01C6
956#define SDR0_XCRn_PAE_MASK 0x80000000
957#define SDR0_XCRn_PAE_DISABLE 0x00000000
958#define SDR0_XCRn_PAE_ENABLE 0x80000000
959#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
960#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
961#define SDR0_XCRn_PHCE_MASK 0x40000000
962#define SDR0_XCRn_PHCE_DISABLE 0x00000000
963#define SDR0_XCRn_PHCE_ENABLE 0x40000000
964#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
965#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
966#define SDR0_XCRn_PISE_MASK 0x20000000
967#define SDR0_XCRn_PISE_DISABLE 0x00000000
968#define SDR0_XCRn_PISE_ENABLE 0x20000000
969#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
970#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
971#define SDR0_XCRn_PCWE_MASK 0x10000000
972#define SDR0_XCRn_PCWE_DISABLE 0x00000000
973#define SDR0_XCRn_PCWE_ENABLE 0x10000000
974#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
975#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
976#define SDR0_XCRn_PPIM_MASK 0x0F000000
977#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
978#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
979#define SDR0_XCRn_PR64E_MASK 0x00800000
980#define SDR0_XCRn_PR64E_DISABLE 0x00000000
981#define SDR0_XCRn_PR64E_ENABLE 0x00800000
982#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
983#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
984#define SDR0_XCRn_PXFS_MASK 0x00600000
985#define SDR0_XCRn_PXFS_100_133 0x00000000
986#define SDR0_XCRn_PXFS_66_100 0x00200000
987#define SDR0_XCRn_PXFS_50_66 0x00400000
988#define SDR0_XCRn_PXFS_0_33 0x00600000
989#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
990#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
991
992#define SDR0_XPLLC0 0x01C1
993#define SDR0_XPLLD0 0x01C2
994#define SDR0_XPLLC1 0x01C4
995#define SDR0_XPLLD1 0x01C5
996#define SDR0_XPLLC2 0x01C7
997#define SDR0_XPLLD2 0x01C8
998#define SDR0_SRST 0x0200
999#define SDR0_SLPIPE 0x0220
1000
1001#define SDR0_AMP0 0x0240
1002#define SDR0_AMP0_PRIORITY 0xFFFF0000
1003#define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
1004#define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
1005
1006#define SDR0_AMP1 0x0241
1007#define SDR0_AMP1_PRIORITY 0xFC000000
1008#define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
1009#define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
1010
1011#define SDR0_MIRQ0 0x0260
1012#define SDR0_MIRQ1 0x0261
1013#define SDR0_MALTBL 0x0280
1014#define SDR0_MALRBL 0x02A0
1015#define SDR0_MALTBS 0x02C0
1016#define SDR0_MALRBS 0x02E0
1017
1018/* Reserved for Customer Use */
1019#define SDR0_CUST0 0x4000
1020#define SDR0_CUST0_AUTONEG_MASK 0x8000000
1021#define SDR0_CUST0_NO_AUTONEG 0x0000000
1022#define SDR0_CUST0_AUTONEG 0x8000000
1023#define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
1024#define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
1025#define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
1026#define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
1027#define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
1028#define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
1029#define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
1030
1031#define SDR0_SDSTP4 0x4001
1032#define SDR0_CUST1 0x4002
1033#define SDR0_SDSTP5 0x4003
1034#define SDR0_CUST2 0x4004
1035#define SDR0_SDSTP6 0x4005
1036#define SDR0_CUST3 0x4006
1037#define SDR0_SDSTP7 0x4007
1038
1039#define SDR0_PFC0 0x4100
1040#define SDR0_PFC0_GPIO_0 0x80000000
1041#define SDR0_PFC0_PCIX0REQ2_N 0x00000000
1042#define SDR0_PFC0_GPIO_1 0x40000000
1043#define SDR0_PFC0_PCIX0REQ3_N 0x00000000
1044#define SDR0_PFC0_GPIO_2 0x20000000
1045#define SDR0_PFC0_PCIX0GNT2_N 0x00000000
1046#define SDR0_PFC0_GPIO_3 0x10000000
1047#define SDR0_PFC0_PCIX0GNT3_N 0x00000000
1048#define SDR0_PFC0_GPIO_4 0x08000000
1049#define SDR0_PFC0_PCIX1REQ2_N 0x00000000
1050#define SDR0_PFC0_GPIO_5 0x04000000
1051#define SDR0_PFC0_PCIX1REQ3_N 0x00000000
1052#define SDR0_PFC0_GPIO_6 0x02000000
1053#define SDR0_PFC0_PCIX1GNT2_N 0x00000000
1054#define SDR0_PFC0_GPIO_7 0x01000000
1055#define SDR0_PFC0_PCIX1GNT3_N 0x00000000
1056#define SDR0_PFC0_GPIO_8 0x00800000
1057#define SDR0_PFC0_PERREADY 0x00000000
1058#define SDR0_PFC0_GPIO_9 0x00400000
1059#define SDR0_PFC0_PERCS1_N 0x00000000
1060#define SDR0_PFC0_GPIO_10 0x00200000
1061#define SDR0_PFC0_PERCS2_N 0x00000000
1062#define SDR0_PFC0_GPIO_11 0x00100000
1063#define SDR0_PFC0_IRQ0 0x00000000
1064#define SDR0_PFC0_GPIO_12 0x00080000
1065#define SDR0_PFC0_IRQ1 0x00000000
1066#define SDR0_PFC0_GPIO_13 0x00040000
1067#define SDR0_PFC0_IRQ2 0x00000000
1068#define SDR0_PFC0_GPIO_14 0x00020000
1069#define SDR0_PFC0_IRQ3 0x00000000
1070#define SDR0_PFC0_GPIO_15 0x00010000
1071#define SDR0_PFC0_IRQ4 0x00000000
1072#define SDR0_PFC0_GPIO_16 0x00008000
1073#define SDR0_PFC0_IRQ5 0x00000000
1074#define SDR0_PFC0_GPIO_17 0x00004000
1075#define SDR0_PFC0_PERBE0_N 0x00000000
1076#define SDR0_PFC0_GPIO_18 0x00002000
1077#define SDR0_PFC0_PCI0GNT0_N 0x00000000
1078#define SDR0_PFC0_GPIO_19 0x00001000
1079#define SDR0_PFC0_PCI0GNT1_N 0x00000000
1080#define SDR0_PFC0_GPIO_20 0x00000800
1081#define SDR0_PFC0_PCI0REQ0_N 0x00000000
1082#define SDR0_PFC0_GPIO_21 0x00000400
1083#define SDR0_PFC0_PCI0REQ1_N 0x00000000
1084#define SDR0_PFC0_GPIO_22 0x00000200
1085#define SDR0_PFC0_PCI1GNT0_N 0x00000000
1086#define SDR0_PFC0_GPIO_23 0x00000100
1087#define SDR0_PFC0_PCI1GNT1_N 0x00000000
1088#define SDR0_PFC0_GPIO_24 0x00000080
1089#define SDR0_PFC0_PCI1REQ0_N 0x00000000
1090#define SDR0_PFC0_GPIO_25 0x00000040
1091#define SDR0_PFC0_PCI1REQ1_N 0x00000000
1092#define SDR0_PFC0_GPIO_26 0x00000020
1093#define SDR0_PFC0_PCI2GNT0_N 0x00000000
1094#define SDR0_PFC0_GPIO_27 0x00000010
1095#define SDR0_PFC0_PCI2GNT1_N 0x00000000
1096#define SDR0_PFC0_GPIO_28 0x00000008
1097#define SDR0_PFC0_PCI2REQ0_N 0x00000000
1098#define SDR0_PFC0_GPIO_29 0x00000004
1099#define SDR0_PFC0_PCI2REQ1_N 0x00000000
1100#define SDR0_PFC0_GPIO_30 0x00000002
1101#define SDR0_PFC0_UART1RX 0x00000000
1102#define SDR0_PFC0_GPIO_31 0x00000001
1103#define SDR0_PFC0_UART1TX 0x00000000
1104
1105#define SDR0_PFC1 0x4101
1106#define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
1107#define SDR0_PFC1_UART1_DSR_DTR 0x00000000
1108#define SDR0_PFC1_UART1_CTS_RTS 0x02000000
1109#define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
1110#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
1111#define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
1112#define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
1113#define SDR0_PFC1_ETH_10_100 0x00000000
1114#define SDR0_PFC1_ETH_GIGA 0x00200000
1115#define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
1116#define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1117#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
1118#define SDR0_PFC1_CPU_NO_TRACE 0x00000000
1119#define SDR0_PFC1_CPU_TRACE 0x00080000
1120#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
1121#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
1122
1123#define SDR0_MFR 0x4300
1124#endif /* CONFIG_440SPE */
1125
Stefan Roese43c60992008-03-11 15:11:43 +01001126#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1127/* Pin Function Control Register 0 (SDR0_PFC0) */
1128#define SDR0_PFC0 0x4100
1129#define SDR0_PFC0_DBG 0x00008000 /* debug enable */
1130#define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */
1131#define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */
1132#define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */
1133#define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */
1134#define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */
1135#define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */
1136#define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */
1137#define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */
1138#define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */
1139#define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */
1140#define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */
1141#define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */
1142#define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */
1143#define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */
1144#define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */
1145
1146/* Pin Function Control Register 1 (SDR0_PFC1) */
1147#define SDR0_PFC1 0x4101
1148#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1149#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1150#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1151#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1152#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1153#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1154#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1155#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/
1156#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/
1157#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1158#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1159#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1160
Stefan Roese89bcc482009-07-29 08:45:27 +02001161#define SDR0_ECID0 0x0080
1162#define SDR0_ECID1 0x0081
1163#define SDR0_ECID2 0x0082
1164#define SDR0_ECID3 0x0083
1165
Stefan Roese43c60992008-03-11 15:11:43 +01001166/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
1167#define SDR0_ETH_PLL 0x4102
1168#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
1169#define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */
1170#define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */
1171#define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */
1172#define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */
1173#define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16)
1174#define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */
1175#define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8)
1176#define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */
1177#define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4)
1178#define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */
1179#define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f)
1180
1181/* Ethernet Configuration Register (SDR0_ETH_CFG) */
1182#define SDR0_ETH_CFG 0x4103
1183#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */
1184#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */
1185#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */
1186#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */
1187#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */
1188#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */
1189#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */
1190#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */
1191#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */
1192#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */
1193#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */
1194#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */
1195#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */
1196#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */
1197#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */
1198#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */
1199#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */
1200#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */
1201#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */
1202#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */
1203#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */
1204#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */
1205#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */
1206#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */
1207#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */
1208#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */
1209#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */
1210#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */
1211
1212#define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4
1213#define SDR0_ETH_CFG_ZMII_MII_MODE 0x00
1214#define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01
1215#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
1216#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
1217
Adam Grahamf09f09d2008-10-08 10:12:53 -07001218/* Ethernet Status Register */
1219#define SDR0_ETH_STS 0x4104
1220
Stefan Roese43c60992008-03-11 15:11:43 +01001221/* Miscealleneaous Function Reg. (SDR0_MFR) */
1222#define SDR0_MFR 0x4300
1223#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
1224#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */
1225#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */
1226#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */
1227#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */
1228#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */
1229#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */
1230#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */
1231#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */
1232#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */
1233#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */
1234#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */
1235#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */
1236#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */
1237#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */
1238#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */
1239#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */
1240#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */
1241#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */
1242#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */
1243
1244/* EMACx TX Status Register (SDR0_EMACxTXST)*/
1245#define SDR0_EMAC0TXST 0x4400
1246#define SDR0_EMAC1TXST 0x4401
1247#define SDR0_EMAC2TXST 0x4402
1248#define SDR0_EMAC3TXST 0x4403
1249
1250#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
1251#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
1252#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
1253#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
1254#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
1255#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */
1256#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
1257#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
1258#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
1259#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
1260#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
1261#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
1262#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
1263#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
1264#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
1265#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
1266#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
1267#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
1268#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
1269#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
1270#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
1271#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
1272#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
1273#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
1274
1275/* EMACx RX Status Register (SDR0_EMACxRXST)*/
1276#define SDR0_EMAC0RXST 0x4404
1277#define SDR0_EMAC1RXST 0x4405
1278#define SDR0_EMAC2RXST 0x4406
1279#define SDR0_EMAC3RXST 0x4407
1280
1281#define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */
1282#define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */
1283#define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */
1284#define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */
1285#define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */
1286#define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23)
1287#define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */
1288#define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */
1289#define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */
1290#define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */
1291#define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/
1292#define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/
1293#define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */
1294#define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */
1295#define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */
1296#define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */
1297#define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */
1298#define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */
1299#define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */
1300#define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */
1301#define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */
1302#define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */
1303#define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */
1304#define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */
1305#define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */
1306#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */
1307#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
1308#define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */
1309
1310/* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
1311#define SDR0_EMAC0REJCNT 0x4408
1312#define SDR0_EMAC1REJCNT 0x4409
1313#define SDR0_EMAC2REJCNT 0x440A
1314#define SDR0_EMAC3REJCNT 0x440B
1315
1316#define SDR0_DDR0 0x00E1
1317#define SDR0_DDR0_DPLLRST 0x80000000
1318#define SDR0_DDR0_DDRM_MASK 0x60000000
1319#define SDR0_DDR0_DDRM_DDR1 0x20000000
1320#define SDR0_DDR0_DDRM_DDR2 0x40000000
1321#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1322#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1323#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1324#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
Stefan Roese41712b42008-03-05 12:31:53 +01001325
1326#define AHB_TOP 0xA4
1327#define AHB_BOT 0xA5
Stefan Roese745d8a02008-06-28 14:56:17 +02001328#define SDR0_AHB_CFG 0x370
1329#define SDR0_USB2HOST_CFG 0x371
Stefan Roese43c60992008-03-11 15:11:43 +01001330#endif /* CONFIG_460EX || CONFIG_460GT */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001331
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001332#define SDR0_SDCS_SDD (0x80000000 >> 31)
wdenk0e6d7982004-03-14 00:07:33 +00001333
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001334#if defined(CONFIG_440GP)
1335#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
1336#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
1337#endif /* defined(CONFIG_440GP) */
1338#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
1339#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
1340#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
1341#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001342#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1343 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001344#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
1345#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
1346#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
wdenk0e6d7982004-03-14 00:07:33 +00001347
wdenk63153492005-04-03 20:55:38 +00001348#define SDR0_UARTX_UXICS_MASK 0xF0000000
1349#define SDR0_UARTX_UXICS_PLB 0x20000000
1350#define SDR0_UARTX_UXEC_MASK 0x00800000
1351#define SDR0_UARTX_UXEC_INT 0x00000000
1352#define SDR0_UARTX_UXEC_EXT 0x00800000
1353#define SDR0_UARTX_UXDTE_MASK 0x00400000
1354#define SDR0_UARTX_UXDTE_DISABLE 0x00000000
1355#define SDR0_UARTX_UXDTE_ENABLE 0x00400000
1356#define SDR0_UARTX_UXDRE_MASK 0x00200000
1357#define SDR0_UARTX_UXDRE_DISABLE 0x00000000
1358#define SDR0_UARTX_UXDRE_ENABLE 0x00200000
1359#define SDR0_UARTX_UXDC_MASK 0x00100000
1360#define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
1361#define SDR0_UARTX_UXDC_CLEARED 0x00100000
1362#define SDR0_UARTX_UXDIV_MASK 0x000000FF
1363#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1364#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
wdenk0e6d7982004-03-14 00:07:33 +00001365
wdenk63153492005-04-03 20:55:38 +00001366#define SDR0_CPU440_EARV_MASK 0x30000000
1367#define SDR0_CPU440_EARV_EBC 0x10000000
1368#define SDR0_CPU440_EARV_PCI 0x20000000
1369#define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1370#define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1371#define SDR0_CPU440_NTO1_MASK 0x00000002
1372#define SDR0_CPU440_NTO1_NTOP 0x00000000
1373#define SDR0_CPU440_NTO1_NTO1 0x00000002
1374#define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1375#define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +00001376
wdenk63153492005-04-03 20:55:38 +00001377#define SDR0_XCR_PAE_MASK 0x80000000
1378#define SDR0_XCR_PAE_DISABLE 0x00000000
1379#define SDR0_XCR_PAE_ENABLE 0x80000000
1380#define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1381#define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1382#define SDR0_XCR_PHCE_MASK 0x40000000
1383#define SDR0_XCR_PHCE_DISABLE 0x00000000
1384#define SDR0_XCR_PHCE_ENABLE 0x40000000
1385#define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1386#define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1387#define SDR0_XCR_PISE_MASK 0x20000000
1388#define SDR0_XCR_PISE_DISABLE 0x00000000
1389#define SDR0_XCR_PISE_ENABLE 0x20000000
1390#define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1391#define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1392#define SDR0_XCR_PCWE_MASK 0x10000000
1393#define SDR0_XCR_PCWE_DISABLE 0x00000000
1394#define SDR0_XCR_PCWE_ENABLE 0x10000000
1395#define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1396#define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1397#define SDR0_XCR_PPIM_MASK 0x0F000000
1398#define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1399#define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1400#define SDR0_XCR_PR64E_MASK 0x00800000
1401#define SDR0_XCR_PR64E_DISABLE 0x00000000
1402#define SDR0_XCR_PR64E_ENABLE 0x00800000
1403#define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1404#define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1405#define SDR0_XCR_PXFS_MASK 0x00600000
1406#define SDR0_XCR_PXFS_HIGH 0x00000000
1407#define SDR0_XCR_PXFS_MED 0x00200000
1408#define SDR0_XCR_PXFS_LOW 0x00400000
1409#define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1410#define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1411#define SDR0_XCR_PDM_MASK 0x00000040
1412#define SDR0_XCR_PDM_MULTIPOINT 0x00000000
1413#define SDR0_XCR_PDM_P2P 0x00000040
1414#define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
1415#define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +00001416
1417#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
wdenk63153492005-04-03 20:55:38 +00001418#define SDR0_PFC0_GEIE_MASK 0x00003E00
1419#define SDR0_PFC0_GEIE_TRE 0x00003E00
1420#define SDR0_PFC0_GEIE_NOTRE 0x00000000
1421#define SDR0_PFC0_TRE_MASK 0x00000100
1422#define SDR0_PFC0_TRE_DISABLE 0x00000000
1423#define SDR0_PFC0_TRE_ENABLE 0x00000100
1424#define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1425#define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +00001426
wdenk63153492005-04-03 20:55:38 +00001427#define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
1428#define SDR0_PFC1_EPS_MASK 0x01C00000
1429#define SDR0_PFC1_EPS_GROUP0 0x00000000
1430#define SDR0_PFC1_EPS_GROUP1 0x00400000
1431#define SDR0_PFC1_EPS_GROUP2 0x00800000
1432#define SDR0_PFC1_EPS_GROUP3 0x00C00000
1433#define SDR0_PFC1_EPS_GROUP4 0x01000000
1434#define SDR0_PFC1_EPS_GROUP5 0x01400000
1435#define SDR0_PFC1_EPS_GROUP6 0x01800000
1436#define SDR0_PFC1_EPS_GROUP7 0x01C00000
1437#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1438#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1439#define SDR0_PFC1_RMII_MASK 0x00200000
1440#define SDR0_PFC1_RMII_100MBIT 0x00000000
1441#define SDR0_PFC1_RMII_10MBIT 0x00200000
1442#define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
1443#define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1444#define SDR0_PFC1_CTEMS_MASK 0x00100000
1445#define SDR0_PFC1_CTEMS_EMS 0x00000000
1446#define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
wdenk0e6d7982004-03-14 00:07:33 +00001447
wdenk63153492005-04-03 20:55:38 +00001448#define SDR0_MFR_TAH0_MASK 0x80000000
1449#define SDR0_MFR_TAH0_ENABLE 0x00000000
1450#define SDR0_MFR_TAH0_DISABLE 0x80000000
1451#define SDR0_MFR_TAH1_MASK 0x40000000
1452#define SDR0_MFR_TAH1_ENABLE 0x00000000
1453#define SDR0_MFR_TAH1_DISABLE 0x40000000
1454#define SDR0_MFR_PCM_MASK 0x20000000
1455#define SDR0_MFR_PCM_PPC440GX 0x00000000
1456#define SDR0_MFR_PCM_PPC440GP 0x20000000
1457#define SDR0_MFR_ECS_MASK 0x10000000
1458#define SDR0_MFR_ECS_INTERNAL 0x10000000
1459
Stefan Roesec157d8e2005-08-01 16:41:48 +02001460#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
1461#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
1462#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1463#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1464#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1465#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1466#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1467#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1468#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1469#define SDR0_MFR_ERRATA3_EN0 0x00800000
1470#define SDR0_MFR_ERRATA3_EN1 0x00400000
Stefan Roese887e2ec2006-09-07 11:51:23 +02001471#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
Stefan Roesec157d8e2005-08-01 16:41:48 +02001472#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
1473#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1474#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
1475#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
1476#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001477#endif
1478
1479#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1480#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1481#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1482#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
1483#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
1484#endif
1485
1486#define SDR0_MFR_ECS_MASK 0x10000000
1487#define SDR0_MFR_ECS_INTERNAL 0x10000000
1488
1489#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1490#define SDR0_SRST0 0x200
1491#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1492#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1493#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1494#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1495#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1496#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1497#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1498#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
1499#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
1500#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1501#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1502#define SDR0_SRST0_PCI 0x00100000 /* PCI */
1503#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
1504#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
1505#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1506#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
1507#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
1508#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
1509#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
1510#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
1511#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
1512#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
1513#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
1514#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1515#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
1516#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1517#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
1518#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
1519#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
1520#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
1521#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
1522
1523#define SDR0_SRST1 0x201
1524#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
1525#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
1526#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
1527#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
1528#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
1529#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
1530#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
1531#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
1532#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
1533#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
1534#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
1535#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
1536#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
1537#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
1538#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
1539#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
1540#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
1541#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
1542#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
1543#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
1544
Stefan Roese43c60992008-03-11 15:11:43 +01001545#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1546
1547#define SDR0_SRST0 0x0200
1548#define SDR0_SRST SDR0_SRST0 /* for compatability reasons */
1549#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1550#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1551#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1552#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1553#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1554#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1555#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1556#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
1557#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
1558#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1559#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1560#define SDR0_SRST0_PCI 0x00100000 /* PCI */
1561#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1562#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */
1563#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/
1564#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/
1565#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/
1566#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
1567#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
1568#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
1569#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */
1570#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1571#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1572#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
1573#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */
1574#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
1575
1576#define SDR0_SRST1 0x201
1577#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */
1578#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */
1579#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
1580#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
1581#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
1582#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */
1583#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */
1584#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */
1585#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */
1586#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
1587#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
1588#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
1589#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
1590#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
1591#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
1592#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */
1593#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
1594#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
1595#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
1596#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */
1597#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */
1598#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */
1599#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */
1600#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */
1601#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */
1602#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
1603#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */
1604#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */
1605#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */
1606#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */
1607#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */
1608#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */
1609
1610#define SDR0_PCI0 0x1c0 /* PCI Configuration Register */
1611
Stefan Roese887e2ec2006-09-07 11:51:23 +02001612#else
Stefan Roesec157d8e2005-08-01 16:41:48 +02001613
wdenk63153492005-04-03 20:55:38 +00001614#define SDR0_SRST_BGO 0x80000000
1615#define SDR0_SRST_PLB 0x40000000
1616#define SDR0_SRST_EBC 0x20000000
1617#define SDR0_SRST_OPB 0x10000000
1618#define SDR0_SRST_UART0 0x08000000
1619#define SDR0_SRST_UART1 0x04000000
1620#define SDR0_SRST_IIC0 0x02000000
1621#define SDR0_SRST_IIC1 0x01000000
1622#define SDR0_SRST_GPIO 0x00800000
1623#define SDR0_SRST_GPT 0x00400000
1624#define SDR0_SRST_DMC 0x00200000
1625#define SDR0_SRST_PCI 0x00100000
1626#define SDR0_SRST_EMAC0 0x00080000
1627#define SDR0_SRST_EMAC1 0x00040000
1628#define SDR0_SRST_CPM 0x00020000
1629#define SDR0_SRST_IMU 0x00010000
1630#define SDR0_SRST_UIC01 0x00008000
1631#define SDR0_SRST_UICB2 0x00004000
1632#define SDR0_SRST_SRAM 0x00002000
1633#define SDR0_SRST_EBM 0x00001000
1634#define SDR0_SRST_BGI 0x00000800
1635#define SDR0_SRST_DMA 0x00000400
1636#define SDR0_SRST_DMAC 0x00000200
1637#define SDR0_SRST_MAL 0x00000100
1638#define SDR0_SRST_ZMII 0x00000080
1639#define SDR0_SRST_GPTR 0x00000040
1640#define SDR0_SRST_PPM 0x00000020
1641#define SDR0_SRST_EMAC2 0x00000010
1642#define SDR0_SRST_EMAC3 0x00000008
1643#define SDR0_SRST_RGMII 0x00000001
wdenk0e6d7982004-03-14 00:07:33 +00001644
Stefan Roese887e2ec2006-09-07 11:51:23 +02001645#endif
1646
wdenk0e6d7982004-03-14 00:07:33 +00001647/*-----------------------------------------------------------------------------+
wdenkc00b5f82002-11-03 11:12:02 +00001648| Clocking
1649+-----------------------------------------------------------------------------*/
Feng Kan96e5fc02008-07-08 22:48:07 -07001650#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1651 defined(CONFIG_460SX)
Stefan Roese43c60992008-03-11 15:11:43 +01001652#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
1653#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
1654#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
1655#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
1656#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
1657#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1658#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
1659#elif !defined (CONFIG_440GX) && \
Stefan Roese887e2ec2006-09-07 11:51:23 +02001660 !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
1661 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1662 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
wdenkba56f622004-02-06 23:19:44 +00001663#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
1664#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
1665#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
1666#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
1667#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
1668#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
1669#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
1670#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
1671#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
1672#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
1673#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
1674#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
wdenkc00b5f82002-11-03 11:12:02 +00001675
wdenkba56f622004-02-06 23:19:44 +00001676#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1677#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1678#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1679#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
Stefan Roese846b0dd2005-08-08 12:42:22 +02001680#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
wdenkba56f622004-02-06 23:19:44 +00001681#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
1682#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
1683#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
1684#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
1685#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
1686#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
1687#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
1688#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
1689#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
1690
Stefan Roesec157d8e2005-08-01 16:41:48 +02001691#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
1692#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
1693#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
1694#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
1695#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
1696#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
1697
1698#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
1699#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
1700#define PRADV_MASK 0x07000000 /* Primary Divisor A */
1701#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
1702#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
1703
wdenkba56f622004-02-06 23:19:44 +00001704#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1705#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1706#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1707#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
1708
1709/* Strap 1 Register */
1710#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
1711#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1712#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
1713#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
1714#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
1715#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
1716#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
1717#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
1718#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
1719#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
1720#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
1721#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
1722#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
1723#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
1724#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
1725#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
1726#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
1727#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
Stefan Roese846b0dd2005-08-08 12:42:22 +02001728#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +00001729
Stefan Roese887e2ec2006-09-07 11:51:23 +02001730#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
Stefan Roese26173fc2008-06-30 14:11:07 +02001731#define CPR0_ICFG_RLI_MASK 0x80000000
1732#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
1733#define CPR0_PERD_PERDV0_MASK 0x07000000
Stefan Roese887e2ec2006-09-07 11:51:23 +02001734#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +02001735
wdenkc00b5f82002-11-03 11:12:02 +00001736/*-----------------------------------------------------------------------------
1737| IIC Register Offsets
1738'----------------------------------------------------------------------------*/
wdenk63153492005-04-03 20:55:38 +00001739#define IICMDBUF 0x00
1740#define IICSDBUF 0x02
1741#define IICLMADR 0x04
1742#define IICHMADR 0x05
1743#define IICCNTL 0x06
1744#define IICMDCNTL 0x07
1745#define IICSTS 0x08
1746#define IICEXTSTS 0x09
1747#define IICLSADR 0x0A
1748#define IICHSADR 0x0B
1749#define IICCLKDIV 0x0C
1750#define IICINTRMSK 0x0D
1751#define IICXFRCNT 0x0E
1752#define IICXTCNTLSS 0x0F
1753#define IICDIRECTCNTL 0x10
wdenkc00b5f82002-11-03 11:12:02 +00001754
1755/*-----------------------------------------------------------------------------
wdenkc00b5f82002-11-03 11:12:02 +00001756| PCI Internal Registers et. al. (accessed via plb)
1757+----------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001758#define PCIX0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
1759#define PCIX0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
1760#define PCIX0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
1761#define PCIX0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
wdenkc00b5f82002-11-03 11:12:02 +00001762
Stefan Roese887e2ec2006-09-07 11:51:23 +02001763#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1764 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roesec157d8e2005-08-01 16:41:48 +02001765
1766/* PCI Local Configuration Registers
1767 --------------------------------- */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001768#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
Stefan Roesec157d8e2005-08-01 16:41:48 +02001769
1770/* PCI Master Local Configuration Registers */
1771#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
1772#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
1773#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
1774#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
1775#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
1776#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
1777#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
1778#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
1779#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
1780#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
1781#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
1782#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
1783
1784/* PCI Target Local Configuration Registers */
1785#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
1786#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
1787#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
1788#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
1789
1790#else
1791
wdenk0e6d7982004-03-14 00:07:33 +00001792#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
1793#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
1794#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
1795#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
1796#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
1797#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
1798#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
1799#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
1800#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
1801#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
1802#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
1803#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
1804#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
1805#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
1806#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
1807#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
1808#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
1809#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
1810#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
1811#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
1812#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
1813#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
1814#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
1815#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
1816#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
1817#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
1818#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
1819#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
wdenkc00b5f82002-11-03 11:12:02 +00001820
wdenk63153492005-04-03 20:55:38 +00001821#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
1822#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
wdenkc00b5f82002-11-03 11:12:02 +00001823
wdenk0e6d7982004-03-14 00:07:33 +00001824#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
1825#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
1826#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
wdenk63153492005-04-03 20:55:38 +00001827#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
1828#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
wdenk0e6d7982004-03-14 00:07:33 +00001829#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
1830#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
1831#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
wdenk63153492005-04-03 20:55:38 +00001832#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
1833#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
wdenk0e6d7982004-03-14 00:07:33 +00001834#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
wdenkc00b5f82002-11-03 11:12:02 +00001835
wdenk0e6d7982004-03-14 00:07:33 +00001836#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
1837#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
1838#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
1839#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
1840#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
1841#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
1842#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
1843#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
1844#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
wdenkc00b5f82002-11-03 11:12:02 +00001845
wdenk0e6d7982004-03-14 00:07:33 +00001846#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
wdenkc00b5f82002-11-03 11:12:02 +00001847
Stefan Roese846b0dd2005-08-08 12:42:22 +02001848#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
Stefan Roesec157d8e2005-08-01 16:41:48 +02001849
Stefan Roese887e2ec2006-09-07 11:51:23 +02001850#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1851
1852/* USB2.0 Device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001853#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE
Stefan Roese887e2ec2006-09-07 11:51:23 +02001854
1855#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
1856
1857#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
1858#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
1859#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
1860#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
1861#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
1862#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
1863#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
1864#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
1865#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
1866#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
1867#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
1868#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
1869#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
1870#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
1871#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
1872#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
1873#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
1874#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
1875#endif
1876
Stefan Roesec157d8e2005-08-01 16:41:48 +02001877/******************************************************************************
1878 * GPIO macro register defines
1879 ******************************************************************************/
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001880#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
Feng Kan96e5fc02008-07-08 22:48:07 -07001881 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1882 defined(CONFIG_460SX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001883#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700)
Stefan Roesea4c8d132006-06-02 16:18:04 +02001884
1885#define GPIO0_OR (GPIO0_BASE+0x0)
1886#define GPIO0_TCR (GPIO0_BASE+0x4)
1887#define GPIO0_ODR (GPIO0_BASE+0x18)
1888#define GPIO0_IR (GPIO0_BASE+0x1C)
Stefan Roese5568e612005-11-22 13:20:42 +01001889#endif /* CONFIG_440GP */
1890
Stefan Roese887e2ec2006-09-07 11:51:23 +02001891#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese43c60992008-03-11 15:11:43 +01001892 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1893 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001894#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
1895#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00)
Stefan Roesec157d8e2005-08-01 16:41:48 +02001896
Stefan Roesea4c8d132006-06-02 16:18:04 +02001897#define GPIO0_OR (GPIO0_BASE+0x0)
1898#define GPIO0_TCR (GPIO0_BASE+0x4)
1899#define GPIO0_OSRL (GPIO0_BASE+0x8)
1900#define GPIO0_OSRH (GPIO0_BASE+0xC)
1901#define GPIO0_TSRL (GPIO0_BASE+0x10)
1902#define GPIO0_TSRH (GPIO0_BASE+0x14)
1903#define GPIO0_ODR (GPIO0_BASE+0x18)
1904#define GPIO0_IR (GPIO0_BASE+0x1C)
1905#define GPIO0_RR1 (GPIO0_BASE+0x20)
1906#define GPIO0_RR2 (GPIO0_BASE+0x24)
1907#define GPIO0_RR3 (GPIO0_BASE+0x28)
1908#define GPIO0_ISR1L (GPIO0_BASE+0x30)
1909#define GPIO0_ISR1H (GPIO0_BASE+0x34)
1910#define GPIO0_ISR2L (GPIO0_BASE+0x38)
1911#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
1912#define GPIO0_ISR3L (GPIO0_BASE+0x40)
1913#define GPIO0_ISR3H (GPIO0_BASE+0x44)
1914
1915#define GPIO1_OR (GPIO1_BASE+0x0)
1916#define GPIO1_TCR (GPIO1_BASE+0x4)
1917#define GPIO1_OSRL (GPIO1_BASE+0x8)
1918#define GPIO1_OSRH (GPIO1_BASE+0xC)
1919#define GPIO1_TSRL (GPIO1_BASE+0x10)
1920#define GPIO1_TSRH (GPIO1_BASE+0x14)
1921#define GPIO1_ODR (GPIO1_BASE+0x18)
1922#define GPIO1_IR (GPIO1_BASE+0x1C)
1923#define GPIO1_RR1 (GPIO1_BASE+0x20)
1924#define GPIO1_RR2 (GPIO1_BASE+0x24)
1925#define GPIO1_RR3 (GPIO1_BASE+0x28)
1926#define GPIO1_ISR1L (GPIO1_BASE+0x30)
1927#define GPIO1_ISR1H (GPIO1_BASE+0x34)
1928#define GPIO1_ISR2L (GPIO1_BASE+0x38)
1929#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
1930#define GPIO1_ISR3L (GPIO1_BASE+0x40)
1931#define GPIO1_ISR3H (GPIO1_BASE+0x44)
Stefan Roesec157d8e2005-08-01 16:41:48 +02001932#endif
1933
wdenkc00b5f82002-11-03 11:12:02 +00001934#ifndef __ASSEMBLY__
1935
wdenkba56f622004-02-06 23:19:44 +00001936#endif /* _ASMLANGUAGE */
wdenkc00b5f82002-11-03 11:12:02 +00001937
wdenkc00b5f82002-11-03 11:12:02 +00001938#endif /* __PPC440_H__ */