wdenk | 507bbe3 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 1 | /* |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 2 | * (C) Copyright 2007 Michal Simek |
wdenk | 507bbe3 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 3 | * (C) Copyright 2004 Atmark Techno, Inc. |
| 4 | * |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 5 | * Michal SIMEK <monstr@monstr.eu> |
wdenk | 507bbe3 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 6 | * Yasushi SHOJI <yashi@atmark-techno.com> |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
wdenk | 507bbe3 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 27 | #include <asm-offsets.h> |
wdenk | 507bbe3 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 28 | #include <config.h> |
| 29 | |
| 30 | .text |
| 31 | .global _start |
| 32 | _start: |
Michal Simek | 86c1b2a | 2011-07-21 10:47:21 +0200 | [diff] [blame^] | 33 | /* |
| 34 | * reserve registers: |
| 35 | * r10: Stores little/big endian offset for vectors |
| 36 | * r2: Stores imm opcode |
| 37 | * r3: Stores brai opcode |
| 38 | */ |
| 39 | |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 40 | mts rmsr, r0 /* disable cache */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 41 | addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET |
Michal Simek | 1798049 | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 42 | addi r1, r1, -4 /* Decrement SP to top of memory */ |
Michal Simek | b98cba0 | 2010-08-12 11:47:11 +0200 | [diff] [blame] | 43 | |
| 44 | /* Find-out if u-boot is running on BIG/LITTLE endian platform |
| 45 | * There are some steps which is necessary to keep in mind: |
| 46 | * 1. Setup offset value to r6 |
| 47 | * 2. Store word offset value to address 0x0 |
| 48 | * 3. Load just byte from address 0x0 |
| 49 | * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest |
| 50 | * value that's why is on address 0x0 |
| 51 | * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3 |
| 52 | */ |
| 53 | addik r6, r0, 0x2 /* BIG/LITTLE endian offset */ |
| 54 | swi r6, r0, 0 |
| 55 | lbui r10, r0, 0 |
Michal Simek | b98cba0 | 2010-08-12 11:47:11 +0200 | [diff] [blame] | 56 | |
Michal Simek | 86c1b2a | 2011-07-21 10:47:21 +0200 | [diff] [blame^] | 57 | /* add opcode instruction for 32bit jump - 2 instruction imm & brai */ |
| 58 | addi r2, r0, 0xb0000000 /* hex b000 opcode imm */ |
| 59 | addi r3, r0, 0xb8080000 /* hew b808 opcode brai */ |
wdenk | 507bbe3 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 60 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | #ifdef CONFIG_SYS_RESET_ADDRESS |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 62 | /* reset address */ |
Michal Simek | 86c1b2a | 2011-07-21 10:47:21 +0200 | [diff] [blame^] | 63 | swi r2, r0, 0x0 /* reset address - imm opcode */ |
| 64 | swi r3, r0, 0x4 /* reset address - brai opcode */ |
| 65 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | addik r6, r0, CONFIG_SYS_RESET_ADDRESS |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 67 | sw r6, r1, r0 |
| 68 | lhu r7, r1, r0 |
| 69 | shi r7, r0, 0x2 |
| 70 | shi r6, r0, 0x6 |
Wolfgang Denk | 31c98a8 | 2007-04-04 02:09:30 +0200 | [diff] [blame] | 71 | /* |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 72 | * Copy U-Boot code to CONFIG_SYS_TEXT_BASE |
Michal Simek | 1798049 | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 73 | * solve problem with sbrk_base |
| 74 | */ |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 75 | #if (CONFIG_SYS_RESET_ADDRESS != CONFIG_SYS_TEXT_BASE) |
Michal Simek | 1798049 | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 76 | addi r4, r0, __end |
| 77 | addi r5, r0, __text_start |
| 78 | rsub r4, r5, r4 /* size = __end - __text_start */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | addi r6, r0, CONFIG_SYS_RESET_ADDRESS /* source address */ |
Michal Simek | 1798049 | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 80 | addi r7, r0, 0 /* counter */ |
| 81 | 4: |
| 82 | lw r8, r6, r7 |
| 83 | sw r8, r5, r7 |
| 84 | addi r7, r7, 0x4 |
| 85 | cmp r8, r4, r7 |
| 86 | blti r8, 4b |
| 87 | #endif |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 88 | #endif |
| 89 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 90 | #ifdef CONFIG_SYS_USR_EXCEP |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 91 | /* user_vector_exception */ |
Michal Simek | 86c1b2a | 2011-07-21 10:47:21 +0200 | [diff] [blame^] | 92 | swi r2, r0, 0x8 /* user vector exception - imm opcode */ |
| 93 | swi r3, r0, 0xC /* user vector exception - brai opcode */ |
| 94 | |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 95 | addik r6, r0, _exception_handler |
| 96 | sw r6, r1, r0 |
Michal Simek | b98cba0 | 2010-08-12 11:47:11 +0200 | [diff] [blame] | 97 | /* |
| 98 | * BIG ENDIAN memory map for user exception |
| 99 | * 0x8: 0xB000XXXX |
| 100 | * 0xC: 0xB808XXXX |
| 101 | * |
| 102 | * then it is necessary to count address for storing the most significant |
Wolfgang Denk | 071bc92 | 2010-10-27 22:48:30 +0200 | [diff] [blame] | 103 | * 16bits from _exception_handler address and copy it to |
Michal Simek | b98cba0 | 2010-08-12 11:47:11 +0200 | [diff] [blame] | 104 | * 0xa address. Big endian use offset in r10=0 that's why is it just |
| 105 | * 0xa address. The same is done for the least significant 16 bits |
| 106 | * for 0xe address. |
| 107 | * |
| 108 | * LITTLE ENDIAN memory map for user exception |
| 109 | * 0x8: 0xXXXX00B0 |
| 110 | * 0xC: 0xXXXX08B8 |
| 111 | * |
| 112 | * Offset is for little endian setup to 0x2. rsubi instruction decrease |
| 113 | * address value to ensure that points to proper place which is |
| 114 | * 0x8 for the most significant 16 bits and |
| 115 | * 0xC for the least significant 16 bits |
| 116 | */ |
| 117 | lhu r7, r1, r10 |
| 118 | rsubi r8, r10, 0xa |
| 119 | sh r7, r0, r8 |
| 120 | rsubi r8, r10, 0xe |
| 121 | sh r6, r0, r8 |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 122 | #endif |
| 123 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #ifdef CONFIG_SYS_INTC_0 |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 125 | /* interrupt_handler */ |
Michal Simek | 86c1b2a | 2011-07-21 10:47:21 +0200 | [diff] [blame^] | 126 | swi r2, r0, 0x10 /* interrupt - imm opcode */ |
| 127 | swi r3, r0, 0x14 /* interrupt - brai opcode */ |
| 128 | |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 129 | addik r6, r0, _interrupt_handler |
| 130 | sw r6, r1, r0 |
Michal Simek | b98cba0 | 2010-08-12 11:47:11 +0200 | [diff] [blame] | 131 | lhu r7, r1, r10 |
| 132 | rsubi r8, r10, 0x12 |
| 133 | sh r7, r0, r8 |
| 134 | rsubi r8, r10, 0x16 |
| 135 | sh r6, r0, r8 |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 136 | #endif |
| 137 | |
| 138 | /* hardware exception */ |
Michal Simek | 86c1b2a | 2011-07-21 10:47:21 +0200 | [diff] [blame^] | 139 | swi r2, r0, 0x20 /* hardware exception - imm opcode */ |
| 140 | swi r3, r0, 0x24 /* hardware exception - brai opcode */ |
| 141 | |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 142 | addik r6, r0, _hw_exception_handler |
| 143 | sw r6, r1, r0 |
Michal Simek | b98cba0 | 2010-08-12 11:47:11 +0200 | [diff] [blame] | 144 | lhu r7, r1, r10 |
| 145 | rsubi r8, r10, 0x22 |
| 146 | sh r7, r0, r8 |
| 147 | rsubi r8, r10, 0x26 |
| 148 | sh r6, r0, r8 |
Michal Simek | cfc6711 | 2007-03-11 13:48:24 +0100 | [diff] [blame] | 149 | |
| 150 | /* enable instruction and data cache */ |
| 151 | mfs r12, rmsr |
| 152 | ori r12, r12, 0xa0 |
| 153 | mts rmsr, r12 |
| 154 | |
Michal Simek | 1798049 | 2007-03-26 01:39:07 +0200 | [diff] [blame] | 155 | clear_bss: |
| 156 | /* clear BSS segments */ |
| 157 | addi r5, r0, __bss_start |
| 158 | addi r4, r0, __bss_end |
| 159 | cmp r6, r5, r4 |
| 160 | beqi r6, 3f |
| 161 | 2: |
| 162 | swi r0, r5, 0 /* write zero to loc */ |
| 163 | addi r5, r5, 4 /* increment to next loc */ |
| 164 | cmp r6, r5, r4 /* check if we have reach the end */ |
| 165 | bnei r6, 2b |
| 166 | 3: /* jumping to board_init */ |
wdenk | 507bbe3 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 167 | brai board_init |
wdenk | 507bbe3 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 168 | 1: bri 1b |
Michal Simek | 0643631 | 2007-04-21 21:02:40 +0200 | [diff] [blame] | 169 | |
| 170 | /* |
| 171 | * Read 16bit little endian |
| 172 | */ |
| 173 | .text |
| 174 | .global in16 |
| 175 | .ent in16 |
| 176 | .align 2 |
| 177 | in16: lhu r3, r0, r5 |
| 178 | bslli r4, r3, 8 |
| 179 | bsrli r3, r3, 8 |
| 180 | andi r4, r4, 0xffff |
| 181 | or r3, r3, r4 |
| 182 | rtsd r15, 8 |
| 183 | sext16 r3, r3 |
| 184 | .end in16 |
| 185 | |
| 186 | /* |
| 187 | * Write 16bit little endian |
| 188 | * first parameter(r5) - address, second(r6) - short value |
| 189 | */ |
| 190 | .text |
| 191 | .global out16 |
| 192 | .ent out16 |
| 193 | .align 2 |
| 194 | out16: bslli r3, r6, 8 |
| 195 | bsrli r6, r6, 8 |
| 196 | andi r3, r3, 0xffff |
| 197 | or r3, r3, r6 |
| 198 | sh r3, r0, r5 |
| 199 | rtsd r15, 8 |
| 200 | or r0, r0, r0 |
| 201 | .end out16 |