wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 1 | /* |
Shinya Kuribayashi | 373b16f | 2008-03-25 21:30:07 +0900 | [diff] [blame] | 2 | * Cache-handling routined for MIPS CPUs |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 9 | #include <asm-offsets.h> |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 10 | #include <config.h> |
Shinya Kuribayashi | 2f5d414 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 11 | #include <asm/asm.h> |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 12 | #include <asm/regdef.h> |
| 13 | #include <asm/mipsregs.h> |
| 14 | #include <asm/addrspace.h> |
| 15 | #include <asm/cacheops.h> |
| 16 | |
Daniel Schwierzeck | 979cfea | 2012-04-02 02:57:55 +0000 | [diff] [blame] | 17 | #ifndef CONFIG_SYS_MIPS_CACHE_MODE |
| 18 | #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT |
| 19 | #endif |
| 20 | |
Shinya Kuribayashi | 7daf2eb | 2008-06-05 22:29:00 +0900 | [diff] [blame] | 21 | #define INDEX_BASE CKSEG0 |
Shinya Kuribayashi | 2e0e527 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 22 | |
Shinya Kuribayashi | 1898840 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 23 | .macro f_fill64 dst, offset, val |
| 24 | LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) |
| 25 | LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) |
| 26 | LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) |
| 27 | LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) |
| 28 | LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) |
| 29 | LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) |
| 30 | LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) |
| 31 | LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) |
| 32 | #if LONGSIZE == 4 |
| 33 | LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) |
| 34 | LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) |
| 35 | LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) |
| 36 | LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) |
| 37 | LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) |
| 38 | LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) |
| 39 | LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) |
| 40 | LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) |
| 41 | #endif |
| 42 | .endm |
| 43 | |
Paul Burton | ac22fec | 2015-01-29 01:28:00 +0000 | [diff] [blame] | 44 | .macro cache_loop curr, end, line_sz, op |
| 45 | 10: cache \op, 0(\curr) |
| 46 | PTR_ADDU \curr, \curr, \line_sz |
| 47 | bne \curr, \end, 10b |
| 48 | .endm |
| 49 | |
Paul Burton | 536cb7c | 2015-01-29 01:27:59 +0000 | [diff] [blame] | 50 | .macro l1_info sz, line_sz, off |
| 51 | .set push |
| 52 | .set noat |
| 53 | |
| 54 | mfc0 $1, CP0_CONFIG, 1 |
| 55 | |
| 56 | /* detect line size */ |
| 57 | srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT |
| 58 | andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT) |
| 59 | move \sz, zero |
| 60 | beqz \line_sz, 10f |
| 61 | li \sz, 2 |
| 62 | sllv \line_sz, \sz, \line_sz |
| 63 | |
| 64 | /* detect associativity */ |
| 65 | srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT |
| 66 | andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT) |
| 67 | addi \sz, \sz, 1 |
| 68 | |
| 69 | /* sz *= line_sz */ |
| 70 | mul \sz, \sz, \line_sz |
| 71 | |
| 72 | /* detect log32(sets) */ |
| 73 | srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT |
| 74 | andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT) |
| 75 | addiu $1, $1, 1 |
| 76 | andi $1, $1, 0x7 |
| 77 | |
| 78 | /* sz <<= log32(sets) */ |
| 79 | sllv \sz, \sz, $1 |
| 80 | |
| 81 | /* sz *= 32 */ |
| 82 | li $1, 32 |
| 83 | mul \sz, \sz, $1 |
| 84 | 10: |
| 85 | .set pop |
| 86 | .endm |
Shinya Kuribayashi | 7aa1f19 | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 87 | /* |
| 88 | * mips_cache_reset - low level initialisation of the primary caches |
| 89 | * |
| 90 | * This routine initialises the primary caches to ensure that they have good |
| 91 | * parity. It must be called by the ROM before any cached locations are used |
| 92 | * to prevent the possibility of data with bad parity being written to memory. |
| 93 | * |
| 94 | * To initialise the instruction cache it is essential that a source of data |
| 95 | * with good parity is available. This routine will initialise an area of |
| 96 | * memory starting at location zero to be used as a source of parity. |
| 97 | * |
| 98 | * RETURNS: N/A |
| 99 | * |
| 100 | */ |
Paul Burton | ca4e833 | 2015-01-29 01:28:01 +0000 | [diff] [blame] | 101 | LEAF(mips_cache_reset) |
Paul Burton | fa476f7 | 2013-11-08 11:18:42 +0000 | [diff] [blame] | 102 | #ifdef CONFIG_SYS_ICACHE_SIZE |
| 103 | li t2, CONFIG_SYS_ICACHE_SIZE |
Paul Burton | 536cb7c | 2015-01-29 01:27:59 +0000 | [diff] [blame] | 104 | li t8, CONFIG_SYS_CACHELINE_SIZE |
Paul Burton | fa476f7 | 2013-11-08 11:18:42 +0000 | [diff] [blame] | 105 | #else |
Paul Burton | 536cb7c | 2015-01-29 01:27:59 +0000 | [diff] [blame] | 106 | l1_info t2, t8, MIPS_CONF1_IA_SHIFT |
Paul Burton | fa476f7 | 2013-11-08 11:18:42 +0000 | [diff] [blame] | 107 | #endif |
| 108 | |
| 109 | #ifdef CONFIG_SYS_DCACHE_SIZE |
| 110 | li t3, CONFIG_SYS_DCACHE_SIZE |
Paul Burton | 536cb7c | 2015-01-29 01:27:59 +0000 | [diff] [blame] | 111 | li t9, CONFIG_SYS_CACHELINE_SIZE |
Paul Burton | fa476f7 | 2013-11-08 11:18:42 +0000 | [diff] [blame] | 112 | #else |
Paul Burton | 536cb7c | 2015-01-29 01:27:59 +0000 | [diff] [blame] | 113 | l1_info t3, t9, MIPS_CONF1_DA_SHIFT |
Paul Burton | fa476f7 | 2013-11-08 11:18:42 +0000 | [diff] [blame] | 114 | #endif |
| 115 | |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 116 | #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 117 | |
Paul Burton | fa476f7 | 2013-11-08 11:18:42 +0000 | [diff] [blame] | 118 | /* Determine the largest L1 cache size */ |
| 119 | #if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE) |
| 120 | #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE |
| 121 | li v0, CONFIG_SYS_ICACHE_SIZE |
| 122 | #else |
| 123 | li v0, CONFIG_SYS_DCACHE_SIZE |
| 124 | #endif |
| 125 | #else |
| 126 | move v0, t2 |
| 127 | sltu t1, t2, t3 |
| 128 | movn v0, t3, t1 |
| 129 | #endif |
Shinya Kuribayashi | 1898840 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 130 | /* |
| 131 | * Now clear that much memory starting from zero. |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 132 | */ |
Shinya Kuribayashi | 7daf2eb | 2008-06-05 22:29:00 +0900 | [diff] [blame] | 133 | PTR_LI a0, CKSEG1 |
Shinya Kuribayashi | 1898840 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 134 | PTR_ADDU a1, a0, v0 |
| 135 | 2: PTR_ADDIU a0, 64 |
| 136 | f_fill64 a0, -64, zero |
| 137 | bne a0, a1, 2b |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 138 | |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 139 | #endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */ |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 140 | |
Shinya Kuribayashi | 2e0e527 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 141 | /* |
Paul Burton | 8755d50 | 2015-01-29 01:28:03 +0000 | [diff] [blame^] | 142 | * The TagLo registers used depend upon the CPU implementation, but the |
| 143 | * architecture requires that it is safe for software to write to both |
| 144 | * TagLo selects 0 & 2 covering supported cases. |
| 145 | */ |
| 146 | mtc0 zero, CP0_TAGLO |
| 147 | mtc0 zero, CP0_TAGLO, 2 |
| 148 | |
| 149 | /* |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 150 | * The caches are probably in an indeterminate state, so we force good |
| 151 | * parity into them by doing an invalidate for each line. If |
| 152 | * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to |
| 153 | * perform a load/fill & a further invalidate for each line, assuming |
| 154 | * that the bottom of RAM (having just been cleared) will generate good |
| 155 | * parity for the cache. |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 156 | */ |
| 157 | |
Shinya Kuribayashi | 2e0e527 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 158 | /* |
| 159 | * Initialize the I-cache first, |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 160 | */ |
Paul Burton | ca4e833 | 2015-01-29 01:28:01 +0000 | [diff] [blame] | 161 | blez t2, 1f |
Paul Burton | ca4e833 | 2015-01-29 01:28:01 +0000 | [diff] [blame] | 162 | PTR_LI t0, INDEX_BASE |
| 163 | PTR_ADDU t1, t0, t2 |
| 164 | /* clear tag to invalidate */ |
| 165 | cache_loop t0, t1, t8, INDEX_STORE_TAG_I |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 166 | #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD |
Paul Burton | ca4e833 | 2015-01-29 01:28:01 +0000 | [diff] [blame] | 167 | /* fill once, so data field parity is correct */ |
| 168 | PTR_LI t0, INDEX_BASE |
| 169 | cache_loop t0, t1, t8, FILL |
| 170 | /* invalidate again - prudent but not strictly neccessary */ |
| 171 | PTR_LI t0, INDEX_BASE |
| 172 | cache_loop t0, t1, t8, INDEX_STORE_TAG_I |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 173 | #endif |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 174 | |
Shinya Kuribayashi | 2e0e527 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 175 | /* |
| 176 | * then initialize D-cache. |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 177 | */ |
Paul Burton | ca4e833 | 2015-01-29 01:28:01 +0000 | [diff] [blame] | 178 | 1: blez t3, 3f |
Paul Burton | ca4e833 | 2015-01-29 01:28:01 +0000 | [diff] [blame] | 179 | PTR_LI t0, INDEX_BASE |
| 180 | PTR_ADDU t1, t0, t3 |
| 181 | /* clear all tags */ |
| 182 | cache_loop t0, t1, t9, INDEX_STORE_TAG_D |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 183 | #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD |
Paul Burton | ca4e833 | 2015-01-29 01:28:01 +0000 | [diff] [blame] | 184 | /* load from each line (in cached space) */ |
| 185 | PTR_LI t0, INDEX_BASE |
| 186 | 2: LONG_L zero, 0(t0) |
| 187 | PTR_ADDU t0, t9 |
| 188 | bne t0, t1, 2b |
| 189 | /* clear all tags */ |
| 190 | PTR_LI t0, INDEX_BASE |
| 191 | cache_loop t0, t1, t9, INDEX_STORE_TAG_D |
Paul Burton | dd7c720 | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 192 | #endif |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 193 | |
Paul Burton | ca4e833 | 2015-01-29 01:28:01 +0000 | [diff] [blame] | 194 | 3: jr ra |
Shinya Kuribayashi | 2f5d414 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 195 | END(mips_cache_reset) |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 196 | |
Shinya Kuribayashi | 7aa1f19 | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 197 | /* |
| 198 | * dcache_status - get cache status |
| 199 | * |
| 200 | * RETURNS: 0 - cache disabled; 1 - cache enabled |
| 201 | * |
| 202 | */ |
Shinya Kuribayashi | 2f5d414 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 203 | LEAF(dcache_status) |
Shinya Kuribayashi | d98e348 | 2008-03-25 21:30:07 +0900 | [diff] [blame] | 204 | mfc0 t0, CP0_CONFIG |
| 205 | li t1, CONF_CM_UNCACHED |
| 206 | andi t0, t0, CONF_CM_CMASK |
| 207 | move v0, zero |
| 208 | beq t0, t1, 2f |
| 209 | li v0, 1 |
| 210 | 2: jr ra |
Shinya Kuribayashi | 2f5d414 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 211 | END(dcache_status) |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 212 | |
Shinya Kuribayashi | 7aa1f19 | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 213 | /* |
| 214 | * dcache_disable - disable cache |
| 215 | * |
| 216 | * RETURNS: N/A |
| 217 | * |
| 218 | */ |
Shinya Kuribayashi | 2f5d414 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 219 | LEAF(dcache_disable) |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 220 | mfc0 t0, CP0_CONFIG |
| 221 | li t1, -8 |
| 222 | and t0, t0, t1 |
| 223 | ori t0, t0, CONF_CM_UNCACHED |
Shinya Kuribayashi | 03c031d | 2007-10-27 15:27:06 +0900 | [diff] [blame] | 224 | mtc0 t0, CP0_CONFIG |
Shinya Kuribayashi | 43c5092 | 2008-04-17 23:35:13 +0900 | [diff] [blame] | 225 | jr ra |
Shinya Kuribayashi | 2f5d414 | 2008-03-25 21:30:06 +0900 | [diff] [blame] | 226 | END(dcache_disable) |
wdenk | c021880 | 2003-03-27 12:09:35 +0000 | [diff] [blame] | 227 | |
Shinya Kuribayashi | 7aa1f19 | 2011-05-07 00:18:13 +0900 | [diff] [blame] | 228 | /* |
| 229 | * dcache_enable - enable cache |
| 230 | * |
| 231 | * RETURNS: N/A |
| 232 | * |
| 233 | */ |
Shinya Kuribayashi | ea63895 | 2008-05-03 13:51:28 +0900 | [diff] [blame] | 234 | LEAF(dcache_enable) |
| 235 | mfc0 t0, CP0_CONFIG |
| 236 | ori t0, CONF_CM_CMASK |
| 237 | xori t0, CONF_CM_CMASK |
Daniel Schwierzeck | 979cfea | 2012-04-02 02:57:55 +0000 | [diff] [blame] | 238 | ori t0, CONFIG_SYS_MIPS_CACHE_MODE |
Shinya Kuribayashi | ea63895 | 2008-05-03 13:51:28 +0900 | [diff] [blame] | 239 | mtc0 t0, CP0_CONFIG |
| 240 | jr ra |
| 241 | END(dcache_enable) |