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Roberto Cerati45a16932013-04-24 10:46:17 +08001/*
2 * Micrel KS8851_MLL 16bit Network driver
3 * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Roberto Cerati45a16932013-04-24 10:46:17 +08006 */
7
8#include <asm/io.h>
9#include <common.h>
10#include <command.h>
11#include <malloc.h>
12#include <net.h>
13#include <miiphy.h>
14
15#include "ks8851_mll.h"
16
17#define DRIVERNAME "ks8851_mll"
18
19#define MAX_RECV_FRAMES 32
20#define MAX_BUF_SIZE 2048
21#define TX_BUF_SIZE 2000
22#define RX_BUF_SIZE 2000
23
24static const struct chip_id chip_ids[] = {
25 {CIDER_ID, "KSZ8851"},
26 {0, NULL},
27};
28
29/*
30 * union ks_tx_hdr - tx header data
31 * @txb: The header as bytes
32 * @txw: The header as 16bit, little-endian words
33 *
34 * A dual representation of the tx header data to allow
35 * access to individual bytes, and to allow 16bit accesses
36 * with 16bit alignment.
37 */
38union ks_tx_hdr {
39 u8 txb[4];
40 __le16 txw[2];
41};
42
43/*
44 * struct ks_net - KS8851 driver private data
45 * @net_device : The network device we're bound to
46 * @txh : temporaly buffer to save status/length.
47 * @frame_head_info : frame header information for multi-pkt rx.
48 * @statelock : Lock on this structure for tx list.
49 * @msg_enable : The message flags controlling driver output (see ethtool).
50 * @frame_cnt : number of frames received.
51 * @bus_width : i/o bus width.
52 * @irq : irq number assigned to this device.
53 * @rc_rxqcr : Cached copy of KS_RXQCR.
54 * @rc_txcr : Cached copy of KS_TXCR.
55 * @rc_ier : Cached copy of KS_IER.
56 * @sharedbus : Multipex(addr and data bus) mode indicator.
57 * @cmd_reg_cache : command register cached.
58 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
59 * @promiscuous : promiscuous mode indicator.
60 * @all_mcast : mutlicast indicator.
61 * @mcast_lst_size : size of multicast list.
62 * @mcast_lst : multicast list.
63 * @mcast_bits : multicast enabed.
64 * @mac_addr : MAC address assigned to this device.
65 * @fid : frame id.
66 * @extra_byte : number of extra byte prepended rx pkt.
67 * @enabled : indicator this device works.
68 */
69
70/* Receive multiplex framer header info */
71struct type_frame_head {
72 u16 sts; /* Frame status */
73 u16 len; /* Byte count */
74} fr_h_i[MAX_RECV_FRAMES];
75
76struct ks_net {
77 struct net_device *netdev;
78 union ks_tx_hdr txh;
79 struct type_frame_head *frame_head_info;
80 u32 msg_enable;
81 u32 frame_cnt;
82 int bus_width;
83 int irq;
84 u16 rc_rxqcr;
85 u16 rc_txcr;
86 u16 rc_ier;
87 u16 sharedbus;
88 u16 cmd_reg_cache;
89 u16 cmd_reg_cache_int;
90 u16 promiscuous;
91 u16 all_mcast;
92 u16 mcast_lst_size;
93 u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
94 u8 mcast_bits[HW_MCAST_SIZE];
95 u8 mac_addr[6];
96 u8 fid;
97 u8 extra_byte;
98 u8 enabled;
99} ks_str, *ks;
100
101#define BE3 0x8000 /* Byte Enable 3 */
102#define BE2 0x4000 /* Byte Enable 2 */
103#define BE1 0x2000 /* Byte Enable 1 */
104#define BE0 0x1000 /* Byte Enable 0 */
105
106static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
107{
108 u8 shift_bit = offset & 0x03;
109 u8 shift_data = (offset & 1) << 3;
110
111 writew(offset | (BE0 << shift_bit), dev->iobase + 2);
112
113 return (u8)(readw(dev->iobase) >> shift_data);
114}
115
116static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
117{
118 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
119
120 return readw(dev->iobase);
121}
122
123static void ks_wrreg8(struct eth_device *dev, u16 offset, u8 val)
124{
125 u8 shift_bit = (offset & 0x03);
126 u16 value_write = (u16)(val << ((offset & 1) << 3));
127
128 writew(offset | (BE0 << shift_bit), dev->iobase + 2);
129 writew(value_write, dev->iobase);
130}
131
132static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
133{
134 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
135 writew(val, dev->iobase);
136}
137
138/*
139 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
140 * enabled.
141 * @ks: The chip state
142 * @wptr: buffer address to save data
143 * @len: length in byte to read
144 */
145static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
146{
147 len >>= 1;
148
149 while (len--)
150 *wptr++ = readw(dev->iobase);
151}
152
153/*
154 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
155 * @ks: The chip information
156 * @wptr: buffer address
157 * @len: length in byte to write
158 */
159static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
160{
161 len >>= 1;
162
163 while (len--)
164 writew(*wptr++, dev->iobase);
165}
166
167static void ks_enable_int(struct eth_device *dev)
168{
169 ks_wrreg16(dev, KS_IER, ks->rc_ier);
170}
171
172static void ks_set_powermode(struct eth_device *dev, unsigned pwrmode)
173{
174 unsigned pmecr;
175
176 ks_rdreg16(dev, KS_GRR);
177 pmecr = ks_rdreg16(dev, KS_PMECR);
178 pmecr &= ~PMECR_PM_MASK;
179 pmecr |= pwrmode;
180
181 ks_wrreg16(dev, KS_PMECR, pmecr);
182}
183
184/*
185 * ks_read_config - read chip configuration of bus width.
186 * @ks: The chip information
187 */
188static void ks_read_config(struct eth_device *dev)
189{
190 u16 reg_data = 0;
191
192 /* Regardless of bus width, 8 bit read should always work. */
193 reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
194 reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
195
196 /* addr/data bus are multiplexed */
197 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
198
199 /*
200 * There are garbage data when reading data from QMU,
201 * depending on bus-width.
202 */
203 if (reg_data & CCR_8BIT) {
204 ks->bus_width = ENUM_BUS_8BIT;
205 ks->extra_byte = 1;
206 } else if (reg_data & CCR_16BIT) {
207 ks->bus_width = ENUM_BUS_16BIT;
208 ks->extra_byte = 2;
209 } else {
210 ks->bus_width = ENUM_BUS_32BIT;
211 ks->extra_byte = 4;
212 }
213}
214
215/*
216 * ks_soft_reset - issue one of the soft reset to the device
217 * @ks: The device state.
218 * @op: The bit(s) to set in the GRR
219 *
220 * Issue the relevant soft-reset command to the device's GRR register
221 * specified by @op.
222 *
223 * Note, the delays are in there as a caution to ensure that the reset
224 * has time to take effect and then complete. Since the datasheet does
225 * not currently specify the exact sequence, we have chosen something
226 * that seems to work with our device.
227 */
228static void ks_soft_reset(struct eth_device *dev, unsigned op)
229{
230 /* Disable interrupt first */
231 ks_wrreg16(dev, KS_IER, 0x0000);
232 ks_wrreg16(dev, KS_GRR, op);
233 mdelay(10); /* wait a short time to effect reset */
234 ks_wrreg16(dev, KS_GRR, 0);
235 mdelay(1); /* wait for condition to clear */
236}
237
238void ks_enable_qmu(struct eth_device *dev)
239{
240 u16 w;
241
242 w = ks_rdreg16(dev, KS_TXCR);
243
244 /* Enables QMU Transmit (TXCR). */
245 ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
246
247 /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
248 w = ks_rdreg16(dev, KS_RXQCR);
249 ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
250
251 /* Enables QMU Receive (RXCR1). */
252 w = ks_rdreg16(dev, KS_RXCR1);
253 ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
254}
255
256static void ks_disable_qmu(struct eth_device *dev)
257{
258 u16 w;
259
260 w = ks_rdreg16(dev, KS_TXCR);
261
262 /* Disables QMU Transmit (TXCR). */
263 w &= ~TXCR_TXE;
264 ks_wrreg16(dev, KS_TXCR, w);
265
266 /* Disables QMU Receive (RXCR1). */
267 w = ks_rdreg16(dev, KS_RXCR1);
268 w &= ~RXCR1_RXE;
269 ks_wrreg16(dev, KS_RXCR1, w);
270}
271
272static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
273{
274 u32 r = ks->extra_byte & 0x1;
275 u32 w = ks->extra_byte - r;
276
277 /* 1. set sudo DMA mode */
278 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
279 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
280
281 /*
282 * 2. read prepend data
283 *
284 * read 4 + extra bytes and discard them.
285 * extra bytes for dummy, 2 for status, 2 for len
286 */
287
288 if (r)
289 ks_rdreg8(dev, 0);
290
291 ks_inblk(dev, buf, w + 2 + 2);
292
293 /* 3. read pkt data */
294 ks_inblk(dev, buf, ALIGN(len, 4));
295
296 /* 4. reset sudo DMA Mode */
297 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
298}
299
300static void ks_rcv(struct eth_device *dev, uchar **pv_data)
301{
302 struct type_frame_head *frame_hdr = ks->frame_head_info;
303 int i;
304
305 ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
306
307 /* read all header information */
308 for (i = 0; i < ks->frame_cnt; i++) {
309 /* Checking Received packet status */
310 frame_hdr->sts = ks_rdreg16(dev, KS_RXFHSR);
311 /* Get packet len from hardware */
312 frame_hdr->len = ks_rdreg16(dev, KS_RXFHBCR);
313 frame_hdr++;
314 }
315
316 frame_hdr = ks->frame_head_info;
317 while (ks->frame_cnt--) {
318 if ((frame_hdr->sts & RXFSHR_RXFV) &&
319 (frame_hdr->len < RX_BUF_SIZE) &&
320 frame_hdr->len) {
321 /* read data block including CRC 4 bytes */
322 ks_read_qmu(dev, (u16 *)(*pv_data), frame_hdr->len);
323
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500324 /* net_rx_packets buffer size is ok (*pv_data) */
325 net_process_received_packet(*pv_data, frame_hdr->len);
Roberto Cerati45a16932013-04-24 10:46:17 +0800326 pv_data++;
327 } else {
328 ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
329 printf(DRIVERNAME ": bad packet\n");
330 }
331 frame_hdr++;
332 }
333}
334
335/*
336 * ks_read_selftest - read the selftest memory info.
337 * @ks: The device state
338 *
339 * Read and check the TX/RX memory selftest information.
340 */
341static int ks_read_selftest(struct eth_device *dev)
342{
343 u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
344 u16 mbir;
345 int ret = 0;
346
347 mbir = ks_rdreg16(dev, KS_MBIR);
348
349 if ((mbir & both_done) != both_done) {
350 printf(DRIVERNAME ": Memory selftest not finished\n");
351 return 0;
352 }
353
354 if (mbir & MBIR_TXMBFA) {
355 printf(DRIVERNAME ": TX memory selftest fails\n");
356 ret |= 1;
357 }
358
359 if (mbir & MBIR_RXMBFA) {
360 printf(DRIVERNAME ": RX memory selftest fails\n");
361 ret |= 2;
362 }
363
364 debug(DRIVERNAME ": the selftest passes\n");
365
366 return ret;
367}
368
369static void ks_setup(struct eth_device *dev)
370{
371 u16 w;
372
373 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
374 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
375
376 /* Setup Receive Frame Data Pointer Auto-Increment */
377 ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
378
379 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
380 ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
381
382 /* Setup RxQ Command Control (RXQCR) */
383 ks->rc_rxqcr = RXQCR_CMD_CNTL;
384 ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr);
385
386 /*
387 * set the force mode to half duplex, default is full duplex
388 * because if the auto-negotiation fails, most switch uses
389 * half-duplex.
390 */
391 w = ks_rdreg16(dev, KS_P1MBCR);
392 w &= ~P1MBCR_FORCE_FDX;
393 ks_wrreg16(dev, KS_P1MBCR, w);
394
395 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
396 ks_wrreg16(dev, KS_TXCR, w);
397
398 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
399
400 /* Normal mode */
401 w |= RXCR1_RXPAFMA;
402
403 ks_wrreg16(dev, KS_RXCR1, w);
404}
405
406static void ks_setup_int(struct eth_device *dev)
407{
408 ks->rc_ier = 0x00;
409
410 /* Clear the interrupts status of the hardware. */
411 ks_wrreg16(dev, KS_ISR, 0xffff);
412
413 /* Enables the interrupts of the hardware. */
414 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
415}
416
417static int ks8851_mll_detect_chip(struct eth_device *dev)
418{
419 unsigned short val, i;
420
421 ks_read_config(dev);
422
423 val = ks_rdreg16(dev, KS_CIDER);
424
425 if (val == 0xffff) {
426 /* Special case -- no chip present */
427 printf(DRIVERNAME ": is chip mounted ?\n");
428 return -1;
429 } else if ((val & 0xfff0) != CIDER_ID) {
430 printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
431 return -1;
432 }
433
434 debug("Read back KS8851 id 0x%x\n", val);
435
436 /* only one entry in the table */
437 val &= 0xfff0;
438 for (i = 0; chip_ids[i].id != 0; i++) {
439 if (chip_ids[i].id == val)
440 break;
441 }
442 if (!chip_ids[i].id) {
443 printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
444 return -1;
445 }
446
447 dev->priv = (void *)&chip_ids[i];
448
449 return 0;
450}
451
452static void ks8851_mll_reset(struct eth_device *dev)
453{
454 /* wake up powermode to normal mode */
455 ks_set_powermode(dev, PMECR_PM_NORMAL);
456 mdelay(1); /* wait for normal mode to take effect */
457
458 /* Disable interrupt and reset */
459 ks_soft_reset(dev, GRR_GSR);
460
461 /* turn off the IRQs and ack any outstanding */
462 ks_wrreg16(dev, KS_IER, 0x0000);
463 ks_wrreg16(dev, KS_ISR, 0xffff);
464
465 /* shutdown RX/TX QMU */
466 ks_disable_qmu(dev);
467}
468
469static void ks8851_mll_phy_configure(struct eth_device *dev)
470{
471 u16 data;
472
473 ks_setup(dev);
474 ks_setup_int(dev);
475
476 /* Probing the phy */
477 data = ks_rdreg16(dev, KS_OBCR);
478 ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
479
480 debug(DRIVERNAME ": phy initialized\n");
481}
482
483static void ks8851_mll_enable(struct eth_device *dev)
484{
485 ks_wrreg16(dev, KS_ISR, 0xffff);
486 ks_enable_int(dev);
487 ks_enable_qmu(dev);
488}
489
490static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
491{
492 struct chip_id *id = dev->priv;
493
494 debug(DRIVERNAME ": detected %s controller\n", id->name);
495
496 if (ks_read_selftest(dev)) {
497 printf(DRIVERNAME ": Selftest failed\n");
498 return -1;
499 }
500
501 ks8851_mll_reset(dev);
502
503 /* Configure the PHY, initialize the link state */
504 ks8851_mll_phy_configure(dev);
505
506 /* static allocation of private informations */
507 ks->frame_head_info = fr_h_i;
508
509 /* Turn on Tx + Rx */
510 ks8851_mll_enable(dev);
511
512 return 0;
513}
514
515static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
516{
517 /* start header at txb[0] to align txw entries */
518 ks->txh.txw[0] = 0;
519 ks->txh.txw[1] = cpu_to_le16(len);
520
521 /* 1. set sudo-DMA mode */
522 ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
523 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
524 /* 2. write status/lenth info */
525 ks_outblk(dev, ks->txh.txw, 4);
526 /* 3. write pkt data */
527 ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
528 /* 4. reset sudo-DMA mode */
529 ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);
530 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
531 ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
532 /* 6. wait until TXQCR_METFE is auto-cleared */
533 do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
534}
535
536static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
537{
538 u8 *data = (u8 *)packet;
539 u16 tmplen = (u16)length;
540 u16 retv;
541
542 /*
543 * Extra space are required:
544 * 4 byte for alignment, 4 for status/length, 4 for CRC
545 */
546 retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
547 if (retv >= tmplen + 12) {
548 ks_write_qmu(dev, data, tmplen);
549 return 0;
550 } else {
551 printf(DRIVERNAME ": failed to send packet: No buffer\n");
552 return -1;
553 }
554}
555
556static void ks8851_mll_halt(struct eth_device *dev)
557{
558 ks8851_mll_reset(dev);
559}
560
561/*
562 * Maximum receive ring size; that is, the number of packets
563 * we can buffer before overflow happens. Basically, this just
564 * needs to be enough to prevent a packet being discarded while
565 * we are processing the previous one.
566 */
567static int ks8851_mll_recv(struct eth_device *dev)
568{
569 u16 status;
570
571 status = ks_rdreg16(dev, KS_ISR);
572
573 ks_wrreg16(dev, KS_ISR, status);
574
575 if ((status & IRQ_RXI))
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500576 ks_rcv(dev, (uchar **)net_rx_packets);
Roberto Cerati45a16932013-04-24 10:46:17 +0800577
578 if ((status & IRQ_LDI)) {
579 u16 pmecr = ks_rdreg16(dev, KS_PMECR);
580 pmecr &= ~PMECR_WKEVT_MASK;
581 ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
582 }
583
584 return 0;
585}
586
587static int ks8851_mll_write_hwaddr(struct eth_device *dev)
588{
589 u16 addrl, addrm, addrh;
590
591 addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
592 addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
593 addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
594
595 ks_wrreg16(dev, KS_MARH, addrh);
596 ks_wrreg16(dev, KS_MARM, addrm);
597 ks_wrreg16(dev, KS_MARL, addrl);
598
599 return 0;
600}
601
602int ks8851_mll_initialize(u8 dev_num, int base_addr)
603{
604 struct eth_device *dev;
605
606 dev = malloc(sizeof(*dev));
607 if (!dev) {
608 printf("Error: Failed to allocate memory\n");
609 return -1;
610 }
611 memset(dev, 0, sizeof(*dev));
612
613 dev->iobase = base_addr;
614
615 ks = &ks_str;
616
617 /* Try to detect chip. Will fail if not present. */
618 if (ks8851_mll_detect_chip(dev)) {
619 free(dev);
620 return -1;
621 }
622
623 dev->init = ks8851_mll_init;
624 dev->halt = ks8851_mll_halt;
625 dev->send = ks8851_mll_send;
626 dev->recv = ks8851_mll_recv;
627 dev->write_hwaddr = ks8851_mll_write_hwaddr;
628 sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
629
630 eth_register(dev);
631
632 return 0;
633}