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wdenk3bac3512003-03-12 10:41:04 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk3bac3512003-03-12 10:41:04 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the CPC45 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8245 1
46#define CONFIG_CPC45 1
47
48
49#define CONFIG_CONS_INDEX 1
50#define CONFIG_BAUDRATE 9600
51#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
52
wdenk3bac3512003-03-12 10:41:04 +000053#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
54
55#define CONFIG_BOOTDELAY 5
56
57#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
58
59#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk49822e22004-06-19 21:19:10 +000060 CFG_CMD_BEDBUG | \
61 CFG_CMD_DATE | \
wdenk3bac3512003-03-12 10:41:04 +000062 CFG_CMD_DHCP | \
wdenk49822e22004-06-19 21:19:10 +000063 CFG_CMD_EEPROM | \
wdenk436be292005-01-31 22:09:11 +000064 CFG_CMD_EXT2 | \
wdenke2ffd592004-12-31 09:32:47 +000065 CFG_CMD_FAT | \
66 CFG_CMD_FLASH | \
wdenk49822e22004-06-19 21:19:10 +000067 CFG_CMD_I2C | \
wdenke2ffd592004-12-31 09:32:47 +000068 CFG_CMD_IDE | \
wdenk436be292005-01-31 22:09:11 +000069 CFG_CMD_NFS | \
wdenk3bac3512003-03-12 10:41:04 +000070 CFG_CMD_PCI | \
wdenk436be292005-01-31 22:09:11 +000071 CFG_CMD_PING | \
wdenk414eec32005-04-02 22:37:54 +000072 CFG_CMD_SDRAM | \
73 CFG_CMD_SNTP )
wdenk3bac3512003-03-12 10:41:04 +000074
75/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
76 */
77#include <cmd_confdefs.h>
78
79
80/*
81 * Miscellaneous configurable options
82 */
83#define CFG_LONGHELP /* undef to save memory */
84#define CFG_PROMPT "=> " /* Monitor Command Prompt */
85#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
86
87#if 1
wdenk49822e22004-06-19 21:19:10 +000088#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
wdenk3bac3512003-03-12 10:41:04 +000089#endif
90#ifdef CFG_HUSH_PARSER
wdenk49822e22004-06-19 21:19:10 +000091#define CFG_PROMPT_HUSH_PS2 "> "
wdenk3bac3512003-03-12 10:41:04 +000092#endif
93
94/* Print Buffer Size
95 */
96#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
97
wdenk49822e22004-06-19 21:19:10 +000098#define CFG_MAXARGS 16 /* max number of command args */
wdenk3bac3512003-03-12 10:41:04 +000099#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
100#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
101
102/*-----------------------------------------------------------------------
103 * Start addresses for the final memory configuration
104 * (Set up by the startup code)
105 * Please note that CFG_SDRAM_BASE _must_ start at 0
106 */
107
wdenk49822e22004-06-19 21:19:10 +0000108#define CFG_SDRAM_BASE 0x00000000
wdenk3bac3512003-03-12 10:41:04 +0000109
110#if defined(CONFIG_BOOT_ROM)
wdenk49822e22004-06-19 21:19:10 +0000111#define CFG_FLASH_BASE 0xFF000000
wdenk3bac3512003-03-12 10:41:04 +0000112#else
wdenk49822e22004-06-19 21:19:10 +0000113#define CFG_FLASH_BASE 0xFF800000
wdenk3bac3512003-03-12 10:41:04 +0000114#endif
115
wdenk49822e22004-06-19 21:19:10 +0000116#define CFG_RESET_ADDRESS 0xFFF00100
wdenk3bac3512003-03-12 10:41:04 +0000117
wdenk49822e22004-06-19 21:19:10 +0000118#define CFG_EUMB_ADDR 0xFCE00000
wdenk3bac3512003-03-12 10:41:04 +0000119
wdenk49822e22004-06-19 21:19:10 +0000120#define CFG_MONITOR_BASE TEXT_BASE
wdenk3bac3512003-03-12 10:41:04 +0000121
wdenk49822e22004-06-19 21:19:10 +0000122#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
123#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk3bac3512003-03-12 10:41:04 +0000124
wdenk49822e22004-06-19 21:19:10 +0000125#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
126#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenk3bac3512003-03-12 10:41:04 +0000127
wdenk49822e22004-06-19 21:19:10 +0000128/* Maximum amount of RAM.
129 */
130#define CFG_MAX_RAM_SIZE 0x10000000
wdenk3bac3512003-03-12 10:41:04 +0000131
132
133#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
134#undef CFG_RAMBOOT
135#else
136#define CFG_RAMBOOT
137#endif
138
139
140/*-----------------------------------------------------------------------
141 * Definitions for initial stack pointer and data area
142 */
143
wdenk49822e22004-06-19 21:19:10 +0000144/* Size in bytes reserved for initial data
145 */
146#define CFG_GBL_DATA_SIZE 128
wdenk3bac3512003-03-12 10:41:04 +0000147
wdenk49822e22004-06-19 21:19:10 +0000148#define CFG_INIT_RAM_ADDR 0x40000000
149#define CFG_INIT_RAM_END 0x1000
150#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenk3bac3512003-03-12 10:41:04 +0000151
152/*
153 * NS16550 Configuration
154 */
stroese53cf9432003-06-05 15:39:44 +0000155#define CFG_NS16550
wdenk3bac3512003-03-12 10:41:04 +0000156#define CFG_NS16550_SERIAL
157
158#define CFG_NS16550_REG_SIZE 1
159
160#define CFG_NS16550_CLK get_bus_freq(0)
161
162#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
163#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
wdenk49822e22004-06-19 21:19:10 +0000164#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
165
166/*
167 * I2C configuration
168 */
169#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
170
171#define CFG_I2C_SPEED 100000 /* 100 kHz */
172#define CFG_I2C_SLAVE 0x7F
173
174/*
175 * RTC configuration
176 */
177#define CONFIG_RTC_PCF8563
178#define CFG_I2C_RTC_ADDR 0x51
179
180/*
181 * EEPROM configuration
182 */
183#define CFG_I2C_EEPROM_ADDR 0x58
184#define CFG_I2C_EEPROM_ADDR_LEN 1
185#define CFG_EEPROM_PAGE_WRITE_BITS 4
186#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
187#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
wdenk3bac3512003-03-12 10:41:04 +0000188
189/*
190 * Low Level Configuration Settings
191 * (address mappings, register initial values, etc.)
192 * You should know what you are doing if you make changes here.
193 * For the detail description refer to the MPC8240 user's manual.
194 */
195
wdenk49822e22004-06-19 21:19:10 +0000196#define CONFIG_SYS_CLK_FREQ 33000000
197#define CFG_HZ 1000
198
199
200/* Bit-field values for MCCR1.
201 */
202#define CFG_ROMNAL 0
203#define CFG_ROMFAL 8
204
205#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
206#define CFG_BANK1_ROW 0
207#define CFG_BANK2_ROW 0
208#define CFG_BANK3_ROW 0
209#define CFG_BANK4_ROW 0
210#define CFG_BANK5_ROW 0
211#define CFG_BANK6_ROW 0
212#define CFG_BANK7_ROW 0
213
214/* Bit-field values for MCCR2.
wdenk3bac3512003-03-12 10:41:04 +0000215 */
stroese53cf9432003-06-05 15:39:44 +0000216
wdenk49822e22004-06-19 21:19:10 +0000217#define CFG_REFINT 0x2ec
wdenk3bac3512003-03-12 10:41:04 +0000218
wdenk49822e22004-06-19 21:19:10 +0000219/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
220 */
221#define CFG_BSTOPRE 160
wdenk3bac3512003-03-12 10:41:04 +0000222
wdenk49822e22004-06-19 21:19:10 +0000223/* Bit-field values for MCCR3.
224 */
225#define CFG_REFREC 2 /* Refresh to activate interval */
226#define CFG_RDLAT 0 /* Data latancy from read command */
wdenk3bac3512003-03-12 10:41:04 +0000227
wdenk49822e22004-06-19 21:19:10 +0000228/* Bit-field values for MCCR4.
229 */
230#define CFG_PRETOACT 2 /* Precharge to activate interval */
231#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
232#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
233#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
234#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
235#define CFG_ACTORW 2
wdenk3bac3512003-03-12 10:41:04 +0000236#define CFG_REGISTERD_TYPE_BUFFER 1
wdenk49822e22004-06-19 21:19:10 +0000237#define CFG_EXTROM 0
238#define CFG_REGDIMM 0
wdenk3bac3512003-03-12 10:41:04 +0000239
240/* Memory bank settings.
241 * Only bits 20-29 are actually used from these vales to set the
242 * start/end addresses. The upper two bits will always be 0, and the lower
243 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
244 * address. Refer to the MPC8240 book.
245 */
246
wdenk49822e22004-06-19 21:19:10 +0000247#define CFG_BANK0_START 0x00000000
248#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
249#define CFG_BANK0_ENABLE 1
250#define CFG_BANK1_START 0x3ff00000
251#define CFG_BANK1_END 0x3fffffff
252#define CFG_BANK1_ENABLE 0
253#define CFG_BANK2_START 0x3ff00000
254#define CFG_BANK2_END 0x3fffffff
255#define CFG_BANK2_ENABLE 0
256#define CFG_BANK3_START 0x3ff00000
257#define CFG_BANK3_END 0x3fffffff
258#define CFG_BANK3_ENABLE 0
259#define CFG_BANK4_START 0x3ff00000
260#define CFG_BANK4_END 0x3fffffff
261#define CFG_BANK4_ENABLE 0
262#define CFG_BANK5_START 0x3ff00000
263#define CFG_BANK5_END 0x3fffffff
264#define CFG_BANK5_ENABLE 0
265#define CFG_BANK6_START 0x3ff00000
266#define CFG_BANK6_END 0x3fffffff
267#define CFG_BANK6_ENABLE 0
268#define CFG_BANK7_START 0x3ff00000
269#define CFG_BANK7_END 0x3fffffff
270#define CFG_BANK7_ENABLE 0
wdenk3bac3512003-03-12 10:41:04 +0000271
wdenk49822e22004-06-19 21:19:10 +0000272#define CFG_ODCR 0xff
273#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
274 /* currently accessed page in memory */
275 /* see 8240 book for details */
wdenk3bac3512003-03-12 10:41:04 +0000276
277#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
278#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
279
280#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
281#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
282
283#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
284#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
285
286#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
287#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
288
289#define CFG_DBAT0L CFG_IBAT0L
290#define CFG_DBAT0U CFG_IBAT0U
291#define CFG_DBAT1L CFG_IBAT1L
292#define CFG_DBAT1U CFG_IBAT1U
293#define CFG_DBAT2L CFG_IBAT2L
294#define CFG_DBAT2U CFG_IBAT2U
295#define CFG_DBAT3L CFG_IBAT3L
296#define CFG_DBAT3U CFG_IBAT3U
297
298/*
299 * For booting Linux, the board info and command line data
300 * have to be in the first 8 MB of memory, since this is
301 * the maximum mapped by the Linux kernel during initialization.
302 */
wdenk49822e22004-06-19 21:19:10 +0000303#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk3bac3512003-03-12 10:41:04 +0000304
305/*-----------------------------------------------------------------------
306 * FLASH organization
307 */
308#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
309#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
310#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
311#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
312#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
313
314 /* Warining: environment is not EMBEDDED in the ppcboot code.
315 * It's stored in flash separately.
316 */
317#define CFG_ENV_IS_IN_FLASH 1
318
wdenk49822e22004-06-19 21:19:10 +0000319#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000)
wdenk3bac3512003-03-12 10:41:04 +0000320#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
321#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
322#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
323
324/*-----------------------------------------------------------------------
325 * Cache Configuration
326 */
327#define CFG_CACHELINE_SIZE 32
328#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
329# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
330#endif
331
332/*
333 * Internal Definitions
334 *
335 * Boot Flags
336 */
337#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
338#define BOOTFLAG_WARM 0x02 /* Software reboot */
339
340
wdenk49822e22004-06-19 21:19:10 +0000341#define SRAM_BASE 0x80000000 /* SRAM base address */
342#define SRAM_END 0x801FFFFF
wdenk3bac3512003-03-12 10:41:04 +0000343
wdenk49822e22004-06-19 21:19:10 +0000344/*----------------------------------------------------------------------*/
345/* CPC45 Memory Map */
346/*----------------------------------------------------------------------*/
347#define SRAM_BASE 0x80000000 /* SRAM base address */
348#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
349#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
350#define BCSR_BASE 0x80600000 /* board control / status registers */
351#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
wdenke2ffd592004-12-31 09:32:47 +0000352#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
wdenk49822e22004-06-19 21:19:10 +0000353#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
wdenk3bac3512003-03-12 10:41:04 +0000354
355
356/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000357/* CPC45 Control/Status Registers */
wdenk3bac3512003-03-12 10:41:04 +0000358/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000359#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
360#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
361#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
362#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
363#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
364#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
365#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
366#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
367#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
368#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
wdenk3bac3512003-03-12 10:41:04 +0000369
370/* IRQ_ENA_1 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000371#define I_ENA_1_IERA 0x80 /* INTA enable */
372#define I_ENA_1_IERB 0x40 /* INTB enable */
373#define I_ENA_1_IERC 0x20 /* INTC enable */
374#define I_ENA_1_IERD 0x10 /* INTD enable */
wdenk3bac3512003-03-12 10:41:04 +0000375
376/* IRQ_STAT_1 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000377#define I_STAT_1_INTA 0x80 /* INTA status */
378#define I_STAT_1_INTB 0x40 /* INTB status */
379#define I_STAT_1_INTC 0x20 /* INTC status */
380#define I_STAT_1_INTD 0x10 /* INTD status */
wdenk3bac3512003-03-12 10:41:04 +0000381
382/* IRQ_ENA_2 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000383#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
384#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
385#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
386#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
387#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
388#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
389#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
390#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
wdenk3bac3512003-03-12 10:41:04 +0000391
392/* IRQ_STAT_2 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000393#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
394#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
395#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
396#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
397#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
398#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
399#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
400#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
wdenk3bac3512003-03-12 10:41:04 +0000401
402/* BOARD_CTRL bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000403#define USER_LEDS 2 /* 2 user LEDs */
wdenk3bac3512003-03-12 10:41:04 +0000404
405#if (USER_LEDS == 4)
wdenk49822e22004-06-19 21:19:10 +0000406#define B_CTRL_WRSE 0x80
407#define B_CTRL_KRSE 0x40
408#define B_CTRL_FWRE 0x20 /* Flash write enable */
409#define B_CTRL_FWPT 0x10 /* Flash write protect */
410#define B_CTRL_LED3 0x08 /* LED 3 control */
411#define B_CTRL_LED2 0x04 /* LED 2 control */
412#define B_CTRL_LED1 0x02 /* LED 1 control */
413#define B_CTRL_LED0 0x01 /* LED 0 control */
wdenk3bac3512003-03-12 10:41:04 +0000414#else
wdenk49822e22004-06-19 21:19:10 +0000415#define B_CTRL_WRSE 0x80
416#define B_CTRL_KRSE 0x40
417#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
418#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
419#define B_CTRL_LED1 0x08 /* LED 1 control */
420#define B_CTRL_LED0 0x04 /* LED 0 control */
421#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
422#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
wdenk3bac3512003-03-12 10:41:04 +0000423#endif
424
425/* BOARD_STAT bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000426#define B_STAT_WDGE 0x80
427#define B_STAT_WDGS 0x40
428#define B_STAT_WRST 0x20
429#define B_STAT_KRST 0x10
430#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
431#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
432#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
433#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
wdenk3bac3512003-03-12 10:41:04 +0000434
435/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000436/* Display addresses */
wdenk3bac3512003-03-12 10:41:04 +0000437/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000438#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
439#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
440#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
wdenk3bac3512003-03-12 10:41:04 +0000441
wdenk49822e22004-06-19 21:19:10 +0000442#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
443#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
wdenk3bac3512003-03-12 10:41:04 +0000444
wdenk49822e22004-06-19 21:19:10 +0000445#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
446#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
447#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
448#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
449#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
450#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
451#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
452#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
wdenk3bac3512003-03-12 10:41:04 +0000453
454
455/*-----------------------------------------------------------------------
456 * PCI stuff
457 *-----------------------------------------------------------------------
458 */
459#define CONFIG_PCI /* include pci support */
wdenk49822e22004-06-19 21:19:10 +0000460#undef CONFIG_PCI_PNP
461#undef CONFIG_PCI_SCAN_SHOW
wdenk3bac3512003-03-12 10:41:04 +0000462
wdenk49822e22004-06-19 21:19:10 +0000463#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenk3bac3512003-03-12 10:41:04 +0000464
465#define CONFIG_EEPRO100
wdenk49822e22004-06-19 21:19:10 +0000466#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk3bac3512003-03-12 10:41:04 +0000467
wdenk49822e22004-06-19 21:19:10 +0000468#define PCI_ENET0_IOADDR 0x82000000
wdenk3bac3512003-03-12 10:41:04 +0000469#define PCI_ENET0_MEMADDR 0x82000000
wdenk49822e22004-06-19 21:19:10 +0000470#define PCI_PLX9030_IOADDR 0x82100000
471#define PCI_PLX9030_MEMADDR 0x82100000
wdenke2ffd592004-12-31 09:32:47 +0000472
473/*-----------------------------------------------------------------------
474 * PCMCIA stuff
475 *-----------------------------------------------------------------------
476 */
477
478#define CONFIG_I82365
479
480#define CFG_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
481#define CFG_PCMCIA_MEM_SIZE 0x1000
482
483#define CONFIG_PCMCIA_SLOT_A
484
485/*-----------------------------------------------------------------------
486 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
487 *-----------------------------------------------------------------------
488 */
489
490#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
491
492#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
493#undef CONFIG_IDE_RESET /* reset for IDE not supported */
494#define CONFIG_IDE_LED /* LED for IDE is supported */
495
496#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
497#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
498
499#define CFG_ATA_IDE0_OFFSET 0x0000
wdenke2ffd592004-12-31 09:32:47 +0000500
501#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
502
503#define CFG_ATA_DATA_OFFSET CFG_PCMCIA_MEM_SIZE
504
505/* Offset for normal register accesses */
wdenk1a344f22005-02-03 23:00:49 +0000506#define CFG_ATA_REG_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
wdenke2ffd592004-12-31 09:32:47 +0000507
508/* Offset for alternate registers */
509#define CFG_ATA_ALT_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x400)
510
511#define CONFIG_DOS_PARTITION
512
wdenk3bac3512003-03-12 10:41:04 +0000513#endif /* __CONFIG_H */