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wdenk71f95112003-06-15 22:40:42 +00001/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Thomas Chouabe2c932011-04-19 03:48:31 +000017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk71f95112003-06-15 22:40:42 +000018 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef _MMC_H_
27#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000028
Andy Fleming272cc702008-10-30 16:41:01 -050029#include <linux/list.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000030#include <linux/compiler.h>
Andy Fleming272cc702008-10-30 16:41:01 -050031
32#define SD_VERSION_SD 0x20000
33#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
34#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
35#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
36#define MMC_VERSION_MMC 0x10000
37#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
38#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
39#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
40#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
41#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
42#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
43
44#define MMC_MODE_HS 0x001
45#define MMC_MODE_HS_52MHz 0x010
46#define MMC_MODE_4BIT 0x100
47#define MMC_MODE_8BIT 0x200
Thomas Choud52ebf12010-12-24 13:12:21 +000048#define MMC_MODE_SPI 0x400
Łukasz Majewskib1f1e8212011-07-05 02:19:44 +000049#define MMC_MODE_HC 0x800
Andy Fleming272cc702008-10-30 16:41:01 -050050
Łukasz Majewski62722032012-03-12 22:07:18 +000051#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
52#define MMC_MODE_WIDTH_BITS_SHIFT 8
53
Andy Fleming272cc702008-10-30 16:41:01 -050054#define SD_DATA_4BIT 0x00040000
55
Albin Tonnerre79b91de2009-08-22 14:21:53 +020056#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Fleming272cc702008-10-30 16:41:01 -050057
58#define MMC_DATA_READ 1
59#define MMC_DATA_WRITE 2
60
61#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
62#define UNUSABLE_ERR -17 /* Unusable Card */
63#define COMM_ERR -18 /* Communications Error */
64#define TIMEOUT -19
65
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020066#define MMC_CMD_GO_IDLE_STATE 0
67#define MMC_CMD_SEND_OP_COND 1
68#define MMC_CMD_ALL_SEND_CID 2
69#define MMC_CMD_SET_RELATIVE_ADDR 3
70#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050071#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020072#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050073#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020074#define MMC_CMD_SEND_CSD 9
75#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050076#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020077#define MMC_CMD_SEND_STATUS 13
78#define MMC_CMD_SET_BLOCKLEN 16
79#define MMC_CMD_READ_SINGLE_BLOCK 17
80#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Fleming272cc702008-10-30 16:41:01 -050081#define MMC_CMD_WRITE_SINGLE_BLOCK 24
82#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +000083#define MMC_CMD_ERASE_GROUP_START 35
84#define MMC_CMD_ERASE_GROUP_END 36
85#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020086#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +000087#define MMC_CMD_SPI_READ_OCR 58
88#define MMC_CMD_SPI_CRC_ON_OFF 59
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020089
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020090#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -050091#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020092#define SD_CMD_SEND_IF_COND 8
93
94#define SD_CMD_APP_SET_BUS_WIDTH 6
Lei Wene6f99a52011-06-22 17:03:31 +000095#define SD_CMD_ERASE_WR_BLK_START 32
96#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020097#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -050098#define SD_CMD_APP_SEND_SCR 51
99
100/* SCR definitions in different words */
101#define SD_HIGHSPEED_BUSY 0x00020000
102#define SD_HIGHSPEED_SUPPORTED 0x00020000
103
104#define MMC_HS_TIMING 0x00000100
105#define MMC_HS_52MHZ 0x2
106
Thomas Chouabe2c932011-04-19 03:48:31 +0000107#define OCR_BUSY 0x80000000
108#define OCR_HCS 0x40000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000109#define OCR_VOLTAGE_MASK 0x007FFF80
110#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500111
Lei Wene6f99a52011-06-22 17:03:31 +0000112#define SECURE_ERASE 0x80000000
113
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000114#define MMC_STATUS_MASK (~0x0206BF7F)
Thomas Chouabe2c932011-04-19 03:48:31 +0000115#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
116#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000117#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000118
Jan Kloetzked617c422012-02-05 22:29:12 +0000119#define MMC_STATE_PRG (7 << 9)
120
Andy Fleming272cc702008-10-30 16:41:01 -0500121#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
122#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
123#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
124#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
125#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
126#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
127#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
128#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
129#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
130#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
131#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
132#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
133#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
134#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
135#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
136#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
137#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
138
139#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
140#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
141 addressed by index which are
142 1 in value field */
143#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
144 addressed by index, which are
145 1 in value field */
146#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
147
148#define SD_SWITCH_CHECK 0
149#define SD_SWITCH_SWITCH 1
150
151/*
152 * EXT_CSD fields
153 */
Lei Wen0560db12011-10-03 20:35:10 +0000154#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
155#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
156#define EXT_CSD_PART_CONF 179 /* R/W */
157#define EXT_CSD_BUS_WIDTH 183 /* R/W */
158#define EXT_CSD_HS_TIMING 185 /* R/W */
159#define EXT_CSD_REV 192 /* RO */
160#define EXT_CSD_CARD_TYPE 196 /* RO */
161#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
162#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000163#define EXT_CSD_BOOT_MULT 226 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500164
165/*
166 * EXT_CSD field definitions
167 */
168
Thomas Chouabe2c932011-04-19 03:48:31 +0000169#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
170#define EXT_CSD_CMD_SET_SECURE (1 << 1)
171#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500172
Thomas Chouabe2c932011-04-19 03:48:31 +0000173#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
174#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Andy Fleming272cc702008-10-30 16:41:01 -0500175
176#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
177#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
178#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200179
Andy Fleming1de97f92008-10-30 16:31:39 -0500180#define R1_ILLEGAL_COMMAND (1 << 22)
181#define R1_APP_CMD (1 << 5)
182
Andy Fleming272cc702008-10-30 16:41:01 -0500183#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000184#define MMC_RSP_136 (1 << 1) /* 136 bit response */
185#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
186#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
187#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500188
Thomas Chouabe2c932011-04-19 03:48:31 +0000189#define MMC_RSP_NONE (0)
190#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500191#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
192 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000193#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
194#define MMC_RSP_R3 (MMC_RSP_PRESENT)
195#define MMC_RSP_R4 (MMC_RSP_PRESENT)
196#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
197#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
198#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500199
Lei Wenbc897b12011-05-02 16:26:26 +0000200#define MMCPART_NOAVAILABLE (0xff)
201#define PART_ACCESS_MASK (0x7)
202#define PART_SUPPORT (0x1)
wdenk71f95112003-06-15 22:40:42 +0000203
Andy Fleming1de97f92008-10-30 16:31:39 -0500204struct mmc_cid {
205 unsigned long psn;
206 unsigned short oid;
207 unsigned char mid;
208 unsigned char prv;
209 unsigned char mdt;
210 char pnm[7];
211};
212
Andy Fleming272cc702008-10-30 16:41:01 -0500213struct mmc_cmd {
214 ushort cmdidx;
215 uint resp_type;
216 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530217 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500218};
219
220struct mmc_data {
221 union {
222 char *dest;
223 const char *src; /* src buffers don't get written to */
224 };
225 uint flags;
226 uint blocks;
227 uint blocksize;
228};
229
230struct mmc {
231 struct list_head link;
232 char name[32];
233 void *priv;
234 uint voltages;
235 uint version;
Lei Wenbc897b12011-05-02 16:26:26 +0000236 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500237 uint f_min;
238 uint f_max;
239 int high_capacity;
240 uint bus_width;
241 uint clock;
242 uint card_caps;
243 uint host_caps;
244 uint ocr;
245 uint scr[2];
246 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530247 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500248 ushort rca;
Lei Wenbc897b12011-05-02 16:26:26 +0000249 char part_config;
250 char part_num;
Andy Fleming272cc702008-10-30 16:41:01 -0500251 uint tran_speed;
252 uint read_bl_len;
253 uint write_bl_len;
Lei Wene6f99a52011-06-22 17:03:31 +0000254 uint erase_grp_size;
Andy Fleming272cc702008-10-30 16:41:01 -0500255 u64 capacity;
256 block_dev_desc_t block_dev;
257 int (*send_cmd)(struct mmc *mmc,
258 struct mmc_cmd *cmd, struct mmc_data *data);
259 void (*set_ios)(struct mmc *mmc);
260 int (*init)(struct mmc *mmc);
Thierry Reding48972d92012-01-02 01:15:37 +0000261 int (*getcd)(struct mmc *mmc);
Sandeep Paulraj57418d22010-12-20 20:01:21 -0500262 uint b_max;
Andy Fleming272cc702008-10-30 16:41:01 -0500263};
264
265int mmc_register(struct mmc *mmc);
266int mmc_initialize(bd_t *bis);
267int mmc_init(struct mmc *mmc);
268int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang4a6ee172010-11-25 17:06:07 +0000269void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Fleming272cc702008-10-30 16:41:01 -0500270struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700271int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500272void print_mmc_devices(char separator);
Lei Wenea6ebe22011-05-02 16:26:25 +0000273int get_mmc_num(void);
Thierry Reding314284b2012-01-02 01:15:36 +0000274int board_mmc_getcd(struct mmc *mmc);
Lei Wenbc897b12011-05-02 16:26:26 +0000275int mmc_switch_part(int dev_num, unsigned int part_num);
Thierry Reding48972d92012-01-02 01:15:37 +0000276int mmc_getcd(struct mmc *mmc);
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000277void spl_mmc_load(void) __noreturn;
Andy Fleming272cc702008-10-30 16:41:01 -0500278
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200279#ifdef CONFIG_GENERIC_MMC
Thomas Choud52ebf12010-12-24 13:12:21 +0000280#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
281struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200282#else
Andy Fleming272cc702008-10-30 16:41:01 -0500283int mmc_legacy_init(int verbose);
284#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200285
wdenk71f95112003-06-15 22:40:42 +0000286#endif /* _MMC_H_ */