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Lokesh Vutlaaebb2a42019-06-13 10:29:55 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
Vignesh Raghavendra4886f1c2019-12-04 22:17:24 +05306#include <dt-bindings/dma/k3-udma.h>
7#include <dt-bindings/net/ti-dp83867.h>
8
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +05309/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
12 tick-timer = &timer1;
13 };
Vignesh Raghavendra4886f1c2019-12-04 22:17:24 +053014
15 aliases {
16 ethernet0 = &cpsw_port1;
17 };
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +053018};
19
20&cbass_main{
21 u-boot,dm-spl;
22};
23
24&cbass_mcu_wakeup {
25 u-boot,dm-spl;
26
27 timer1: timer@40400000 {
28 compatible = "ti,omap5430-timer";
29 reg = <0x0 0x40400000 0x0 0x80>;
30 ti,timer-alwon;
31 clock-frequency = <25000000>;
32 u-boot,dm-spl;
33 };
Vignesh Raghavendra4886f1c2019-12-04 22:17:24 +053034
35 mcu_conf: scm_conf@40f00000 {
36 compatible = "syscon", "simple-mfd";
37 reg = <0x0 0x40f00000 0x0 0x20000>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges = <0x0 0x0 0x40f00000 0x20000>;
41
42 phy_sel: cpsw-phy-sel@4040 {
43 compatible = "ti,am654-cpsw-phy-sel";
44 reg = <0x4040 0x4>;
45 reg-names = "gmii-sel";
46 };
47 };
48
49 cbass_mcu_navss: mcu_navss {
50 compatible = "simple-bus";
51 #address-cells = <2>;
52 #size-cells = <2>;
53 dma-coherent;
54 dma-ranges;
55 ranges;
56
57 ti,sci-dev-id = <232>;
58 u-boot,dm-spl;
59
60 mcu_ringacc: ringacc@2b800000 {
61 compatible = "ti,am654-navss-ringacc";
62 reg = <0x0 0x2b800000 0x0 0x400000>,
63 <0x0 0x2b000000 0x0 0x400000>,
64 <0x0 0x28590000 0x0 0x100>,
65 <0x0 0x2a500000 0x0 0x40000>;
66 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
67 ti,num-rings = <286>;
68 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
69 ti,sci = <&dmsc>;
70 ti,sci-dev-id = <235>;
71 u-boot,dm-spl;
72 };
73
74 mcu_udmap: udmap@31150000 {
75 compatible = "ti,j721e-navss-mcu-udmap";
76 reg = <0x0 0x285c0000 0x0 0x100>,
77 <0x0 0x2a800000 0x0 0x40000>,
78 <0x0 0x2aa00000 0x0 0x40000>;
79 reg-names = "gcfg", "rchanrt", "tchanrt";
80 #dma-cells = <3>;
81
82 ti,ringacc = <&mcu_ringacc>;
83 ti,psil-base = <0x6000>;
84
85 ti,sci = <&dmsc>;
86 ti,sci-dev-id = <236>;
87
88 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
89 <0x0f>; /* TX_HCHAN */
90 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
91 <0x0b>; /* RX_HCHAN */
92 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
93 u-boot,dm-spl;
94 };
95 };
96
97 mcu_cpsw: ethernet@046000000 {
98 compatible = "ti,j721e-cpsw-nuss";
99 #address-cells = <2>;
100 #size-cells = <2>;
101 reg = <0x0 0x46000000 0x0 0x200000>;
102 reg-names = "cpsw_nuss";
103 ranges;
104 dma-coherent;
105 clocks = <&k3_clks 18 22>;
106 clock-names = "fck";
107 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
108 ti,psil-base = <0x7000>;
109 cpsw-phy-sel = <&phy_sel>;
110
111 dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
112 <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
113 <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
114 <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
115 <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
116 <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
117 <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
118 <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
119 <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
120 dma-names = "tx0", "tx1", "tx2", "tx3",
121 "tx4", "tx5", "tx6", "tx7",
122 "rx";
123
124 ports {
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 host: host@0 {
129 reg = <0>;
130 ti,label = "host";
131 };
132
133 cpsw_port1: port@1 {
134 reg = <1>;
135 ti,mac-only;
136 ti,label = "port1";
137 ti,syscon-efuse = <&mcu_conf 0x200>;
138 };
139 };
140
141 davinci_mdio: mdio {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 bus_freq = <1000000>;
145 };
146
147 cpts {
148 clocks = <&k3_clks 18 2>;
149 clock-names = "cpts";
150 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-names = "cpts";
152 ti,cpts-ext-ts-inputs = <4>;
153 ti,cpts-periodic-outputs = <2>;
154 };
155
156 ti,psil-config0 {
157 linux,udma-mode = <UDMA_PKT_MODE>;
158 statictr-type = <PSIL_STATIC_TR_NONE>;
159 ti,needs-epib;
160 ti,psd-size = <16>;
161 };
162
163 ti,psil-config1 {
164 linux,udma-mode = <UDMA_PKT_MODE>;
165 statictr-type = <PSIL_STATIC_TR_NONE>;
166 ti,needs-epib;
167 ti,psd-size = <16>;
168 };
169
170 ti,psil-config2 {
171 linux,udma-mode = <UDMA_PKT_MODE>;
172 statictr-type = <PSIL_STATIC_TR_NONE>;
173 ti,needs-epib;
174 ti,psd-size = <16>;
175 };
176
177 ti,psil-config3 {
178 linux,udma-mode = <UDMA_PKT_MODE>;
179 statictr-type = <PSIL_STATIC_TR_NONE>;
180 ti,needs-epib;
181 ti,psd-size = <16>;
182 };
183
184 ti,psil-config4 {
185 linux,udma-mode = <UDMA_PKT_MODE>;
186 statictr-type = <PSIL_STATIC_TR_NONE>;
187 ti,needs-epib;
188 ti,psd-size = <16>;
189 };
190
191 ti,psil-config5 {
192 linux,udma-mode = <UDMA_PKT_MODE>;
193 statictr-type = <PSIL_STATIC_TR_NONE>;
194 ti,needs-epib;
195 ti,psd-size = <16>;
196 };
197
198 ti,psil-config6 {
199 linux,udma-mode = <UDMA_PKT_MODE>;
200 statictr-type = <PSIL_STATIC_TR_NONE>;
201 ti,needs-epib;
202 ti,psd-size = <16>;
203 };
204
205 ti,psil-config7 {
206 linux,udma-mode = <UDMA_PKT_MODE>;
207 statictr-type = <PSIL_STATIC_TR_NONE>;
208 ti,needs-epib;
209 ti,psd-size = <16>;
210 };
211 };
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530212};
213
214&secure_proxy_main {
215 u-boot,dm-spl;
216};
217
218&dmsc {
219 u-boot,dm-spl;
220 k3_sysreset: sysreset-controller {
221 compatible = "ti,sci-sysreset";
222 u-boot,dm-spl;
223 };
224};
225
226&k3_pds {
227 u-boot,dm-spl;
228};
229
230&k3_clks {
231 u-boot,dm-spl;
232};
233
234&k3_reset {
235 u-boot,dm-spl;
236};
237
238&wkup_pmx0 {
239 u-boot,dm-spl;
Vignesh Raghavendra4886f1c2019-12-04 22:17:24 +0530240 mcu_cpsw_pins_default: mcu_cpsw_pins_default {
241 pinctrl-single,pins = <
242 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
243 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
244 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
245 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
246 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
247 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
248 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
249 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
250 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
251 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
252 J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
253 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
254 >;
255 };
256
257 mcu_mdio_pins_default: mcu_mdio1_pins_default {
258 pinctrl-single,pins = <
259 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
260 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
261 >;
262 };
Lokesh Vutlaaebb2a42019-06-13 10:29:55 +0530263};
264
265&main_pmx0 {
266 u-boot,dm-spl;
267};
268
269&main_uart0 {
270 u-boot,dm-spl;
271};
272
273&mcu_uart0 {
274 u-boot,dm-spl;
275};
276
277&main_sdhci0 {
278 u-boot,dm-spl;
279};
280
281&main_sdhci1 {
282 u-boot,dm-spl;
283};
Vignesh Raghavendra4886f1c2019-12-04 22:17:24 +0530284
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530285&main_usbss0_pins_default {
286 u-boot,dm-spl;
287};
288
289&usbss0 {
290 u-boot,dm-spl;
291 ti,usb2-only;
292};
293
294&usb0 {
295 dr_mode = "peripheral";
296 u-boot,dm-spl;
297};
298
Vignesh Raghavendra4886f1c2019-12-04 22:17:24 +0530299&mcu_cpsw {
300 pinctrl-names = "default";
301 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
302};
303
304&davinci_mdio {
305 phy0: ethernet-phy@0 {
306 reg = <0>;
307 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
308 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
309 };
310};
311
312&cpsw_port1 {
313 phy-mode = "rgmii-rxid";
314 phy-handle = <&phy0>;
315};
316
317&mcu_cpsw {
318 reg = <0x0 0x46000000 0x0 0x200000>,
319 <0x0 0x40f00200 0x0 0x2>;
320 reg-names = "cpsw_nuss", "mac_efuse";
321
322 cpsw-phy-sel@40f04040 {
323 compatible = "ti,am654-cpsw-phy-sel";
324 reg= <0x0 0x40f04040 0x0 0x4>;
325 reg-names = "gmii-sel";
326 };
327};
Faiz Abbasccc855e2020-01-16 19:42:21 +0530328
329&main_mmc1_pins_default {
330 u-boot,dm-spl;
331};
Andreas Dannenbergc44fb272020-01-07 13:15:56 +0530332
333&wkup_i2c0_pins_default {
334 u-boot,dm-spl;
335};
336
337&wkup_i2c0 {
338 u-boot,dm-spl;
339};
Vignesh Raghavendrab6427782020-01-27 23:22:15 +0530340
341&main_i2c0 {
342 u-boot,dm-spl;
343};
344
345&main_i2c0_pins_default {
346 u-boot,dm-spl;
347};
348
349&exp2 {
350 u-boot,dm-spl;
351};
Vignesh Raghavendra224d7fe2020-02-04 11:09:52 +0530352
353&mcu_fss0_ospi0_pins_default {
354 u-boot,dm-spl;
355};
356
357&fss {
358 u-boot,dm-spl;
359};
360
361&ospi0 {
362 u-boot,dm-spl;
363
364 flash@0 {
365 u-boot,dm-spl;
366 };
367};
Keerthy896cf0e2020-03-04 10:09:59 +0530368
369&ospi1 {
370 u-boot,dm-spl;
371
372 flash@0 {
373 u-boot,dm-spl;
374 };
375};
376
377&mcu_fss0_ospi1_pins_default {
378 u-boot,dm-spl;
379};