blob: f37ab430b325bc2a2fc2c7df2a6859d36964baaf [file] [log] [blame]
Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27#include <i2c.h>
28#include <spd.h>
29#include <asm/mmu.h>
30
31
32#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
33extern void dma_init(void);
34extern uint dma_check(void);
35extern int dma_xfer(void *dest, uint count, void *src);
36#endif
37
38#ifdef CONFIG_SPD_EEPROM
39
40#ifndef CFG_READ_SPD
41#define CFG_READ_SPD i2c_read
42#endif
43
44/*
Jon Loeliger9a655872006-05-19 13:26:34 -050045 * Only one of the following three should be 1; others should be 0
46 * By default the cache line interleaving is selected if
John Traill91a414c2006-08-08 11:32:43 +010047 * the CONFIG_DDR_INTERLEAVE flag is defined
Jon Loeliger9a655872006-05-19 13:26:34 -050048 */
49#define CFG_PAGE_INTERLEAVING 0
50#define CFG_BANK_INTERLEAVING 0
51#define CFG_SUPER_BANK_INTERLEAVING 0
52
53/*
James Yangc1ab8262007-03-16 13:02:53 -050054 * Convert picoseconds into DRAM clock cycles (rounding up if needed).
Jon Loeligerdebb7352006-04-26 17:58:56 -050055 */
56
James Yangc1ab8262007-03-16 13:02:53 -050057static unsigned int
58picos_to_clk(unsigned int picos)
Jon Loeligerdebb7352006-04-26 17:58:56 -050059{
James Yangc1ab8262007-03-16 13:02:53 -050060 /* use unsigned long long to avoid rounding errors */
61 const unsigned long long ULL_2e12 = 2000000000000ULL;
62 unsigned long long clks;
63 unsigned long long clks_temp;
Jon Loeligerdebb7352006-04-26 17:58:56 -050064
James Yangc1ab8262007-03-16 13:02:53 -050065 if (! picos)
66 return 0;
67
68 clks = get_bus_freq(0) * (unsigned long long) picos;
69 clks_temp = clks;
70 clks = clks / ULL_2e12;
71 if (clks_temp % ULL_2e12) {
Jon Loeligerdebb7352006-04-26 17:58:56 -050072 clks++;
73 }
74
James Yangc1ab8262007-03-16 13:02:53 -050075 if (clks > 0xFFFFFFFFULL) {
76 clks = 0xFFFFFFFFULL;
77 }
78
79 return (unsigned int) clks;
Jon Loeligerdebb7352006-04-26 17:58:56 -050080}
81
82
83/*
84 * Calculate the Density of each Physical Rank.
85 * Returned size is in bytes.
86 *
87 * Study these table from Byte 31 of JEDEC SPD Spec.
88 *
89 * DDR I DDR II
90 * Bit Size Size
91 * --- ----- ------
92 * 7 high 512MB 512MB
93 * 6 256MB 256MB
94 * 5 128MB 128MB
95 * 4 64MB 16GB
96 * 3 32MB 8GB
97 * 2 16MB 4GB
98 * 1 2GB 2GB
99 * 0 low 1GB 1GB
100 *
101 * Reorder Table to be linear by stripping the bottom
102 * 2 or 5 bits off and shifting them up to the top.
103 */
104
105unsigned int
106compute_banksize(unsigned int mem_type, unsigned char row_dens)
107{
108 unsigned int bsize;
109
110 if (mem_type == SPD_MEMTYPE_DDR) {
111 /* Bottom 2 bits up to the top. */
112 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
113 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
114 } else {
115 /* Bottom 5 bits up to the top. */
116 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
117 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
118 }
119 return bsize;
120}
121
122
123/*
124 * Convert a two-nibble BCD value into a cycle time.
125 * While the spec calls for nano-seconds, picos are returned.
126 *
127 * This implements the tables for bytes 9, 23 and 25 for both
128 * DDR I and II. No allowance for distinguishing the invalid
129 * fields absent for DDR I yet present in DDR II is made.
130 * (That is, cycle times of .25, .33, .66 and .75 ns are
131 * allowed for both DDR II and I.)
132 */
133
134unsigned int
135convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
136{
137 /*
138 * Table look up the lower nibble, allow DDR I & II.
139 */
140 unsigned int tenths_ps[16] = {
141 0,
142 100,
143 200,
144 300,
145 400,
146 500,
147 600,
148 700,
149 800,
150 900,
151 250,
John Traill91a414c2006-08-08 11:32:43 +0100152 330,
153 660,
Jon Loeligerdebb7352006-04-26 17:58:56 -0500154 750,
155 0, /* undefined */
156 0 /* undefined */
157 };
158
159 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
160 unsigned int tenth_ns = spd_val & 0x0F;
161 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
162
163 return ps;
164}
165
166
Jon Loeliger1fd56992006-10-10 17:19:03 -0500167/*
168 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
169 * Table from SPD Spec, Byte 12, converted to picoseconds and
170 * filled in with "default" normal values.
171 */
172unsigned int determine_refresh_rate(unsigned int spd_refresh)
173{
174 unsigned int refresh_time_ns[8] = {
175 15625000, /* 0 Normal 1.00x */
176 3900000, /* 1 Reduced .25x */
177 7800000, /* 2 Extended .50x */
178 31300000, /* 3 Extended 2.00x */
179 62500000, /* 4 Extended 4.00x */
180 125000000, /* 5 Extended 8.00x */
181 15625000, /* 6 Normal 1.00x filler */
182 15625000, /* 7 Normal 1.00x filler */
183 };
184
185 return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
186}
187
188
Jon Loeligerdebb7352006-04-26 17:58:56 -0500189long int
Jon Loeliger9a655872006-05-19 13:26:34 -0500190spd_init(unsigned char i2c_address, unsigned int ddr_num,
191 unsigned int dimm_num, unsigned int start_addr)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500192{
193 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Jon Loeliger9a655872006-05-19 13:26:34 -0500194 volatile ccsr_ddr_t *ddr;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500195 volatile ccsr_gur_t *gur = &immap->im_gur;
196 spd_eeprom_t spd;
197 unsigned int n_ranks;
198 unsigned int rank_density;
199 unsigned int odt_rd_cfg, odt_wr_cfg;
200 unsigned int odt_cfg, mode_odt_enable;
Jon Loeliger1fd56992006-10-10 17:19:03 -0500201 unsigned int refresh_clk;
202#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
203 unsigned char clk_adjust;
204#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500205 unsigned int dqs_cfg;
206 unsigned char twr_clk, twtr_clk, twr_auto_clk;
207 unsigned int tCKmin_ps, tCKmax_ps;
John Traill91a414c2006-08-08 11:32:43 +0100208 unsigned int max_data_rate;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500209 unsigned int busfreq;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500210 unsigned int memsize;
211 unsigned char caslat, caslat_ctrl;
212 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
213 unsigned int trcd_clk;
214 unsigned int trtp_clk;
215 unsigned char cke_min_clk;
216 unsigned char add_lat;
217 unsigned char wr_lat;
218 unsigned char wr_data_delay;
219 unsigned char four_act;
220 unsigned char cpo;
221 unsigned char burst_len;
222 unsigned int mode_caslat;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500223 unsigned char d_init;
John Traill91a414c2006-08-08 11:32:43 +0100224 unsigned int tCycle_ps, modfreq;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500225
Jon Loeliger9a655872006-05-19 13:26:34 -0500226 if (ddr_num == 1)
227 ddr = &immap->im_ddr1;
228 else
229 ddr = &immap->im_ddr2;
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500230
Jon Loeligerdebb7352006-04-26 17:58:56 -0500231 /*
232 * Read SPD information.
233 */
Jon Loeliger9a655872006-05-19 13:26:34 -0500234 debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address);
235 memset((void *)&spd, 0, sizeof(spd));
236 CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd));
Jon Loeligerdebb7352006-04-26 17:58:56 -0500237
238 /*
239 * Check for supported memory module types.
240 */
241 if (spd.mem_type != SPD_MEMTYPE_DDR &&
242 spd.mem_type != SPD_MEMTYPE_DDR2) {
Jon Loeliger9a655872006-05-19 13:26:34 -0500243 debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n"
244 " Fundamental memory type is 0x%0x\n",
245 dimm_num,
246 ddr_num,
247 spd.mem_type);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500248 return 0;
249 }
250
Jon Loeliger9a655872006-05-19 13:26:34 -0500251 debug("\nFound memory of type 0x%02lx ", spd.mem_type);
252 if (spd.mem_type == SPD_MEMTYPE_DDR)
253 debug("DDR I\n");
254 else
255 debug("DDR II\n");
256
Jon Loeligerdebb7352006-04-26 17:58:56 -0500257 /*
258 * These test gloss over DDR I and II differences in interpretation
259 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
260 * are not supported on DDR I; and not encoded on DDR II.
261 *
262 * Also note that the 8548 controller can support:
263 * 12 <= nrow <= 16
264 * and
265 * 8 <= ncol <= 11 (still, for DDR)
266 * 6 <= ncol <= 9 (for FCRAM)
267 */
268 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
269 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
270 spd.nrow_addr);
271 return 0;
272 }
273 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
274 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
275 spd.ncol_addr);
276 return 0;
277 }
278
279 /*
280 * Determine the number of physical banks controlled by
281 * different Chip Select signals. This is not quite the
282 * same as the number of DIMM modules on the board. Feh.
283 */
284 if (spd.mem_type == SPD_MEMTYPE_DDR) {
285 n_ranks = spd.nrows;
286 } else {
287 n_ranks = (spd.nrows & 0x7) + 1;
288 }
289
290 debug("DDR: number of ranks = %d\n", n_ranks);
291
292 if (n_ranks > 2) {
293 printf("DDR: Only 2 chip selects are supported: %d\n",
294 n_ranks);
295 return 0;
296 }
297
298 /*
Ed Swarthout2ccceac2006-12-07 10:34:14 -0600299 * Adjust DDR II IO voltage biasing. Rev1 only
Jon Loeligerdebb7352006-04-26 17:58:56 -0500300 */
Ed Swarthout2ccceac2006-12-07 10:34:14 -0600301 if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) {
Jon Loeligerdebb7352006-04-26 17:58:56 -0500302 gur->ddrioovcr = (0
303 | 0x80000000 /* Enable */
304 | 0x10000000 /* VSEL to 1.8V */
305 );
306 }
307
308 /*
309 * Determine the size of each Rank in bytes.
310 */
311 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
312
Jon Loeliger9a655872006-05-19 13:26:34 -0500313 debug("Start address for this controller is 0x%08lx\n", start_addr);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500314
315 /*
316 * ODT configuration recommendation from DDR Controller Chapter.
317 */
318 odt_rd_cfg = 0; /* Never assert ODT */
319 odt_wr_cfg = 0; /* Never assert ODT */
320 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
321 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
322 }
323
Jon Loeliger9a655872006-05-19 13:26:34 -0500324#ifdef CONFIG_DDR_INTERLEAVE
John Traill91a414c2006-08-08 11:32:43 +0100325
Jon Loeliger9a655872006-05-19 13:26:34 -0500326 if (dimm_num != 1) {
327 printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
328 return 0;
329 } else {
Jon Loeligerdebb7352006-04-26 17:58:56 -0500330 /*
Jon Loeliger9a655872006-05-19 13:26:34 -0500331 * Since interleaved memory only uses CS0, the
332 * memory sticks have to be identical in size and quantity
333 * of ranks. That essentially gives double the size on
334 * one rank, i.e on CS0 for both controllers put together.
335 * Confirm this???
Jon Loeligerdebb7352006-04-26 17:58:56 -0500336 */
Jon Loeliger9a655872006-05-19 13:26:34 -0500337 rank_density *= 2;
338
339 /*
340 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
341 */
342 start_addr = 0;
343 ddr->cs0_bnds = (start_addr >> 8)
344 | (((start_addr + rank_density - 1) >> 24));
345 /*
346 * Default interleaving mode to cache-line interleaving.
347 */
348 ddr->cs0_config = ( 1 << 31
349#if (CFG_PAGE_INTERLEAVING == 1)
350 | (PAGE_INTERLEAVING)
351#elif (CFG_BANK_INTERLEAVING == 1)
352 | (BANK_INTERLEAVING)
353#elif (CFG_SUPER_BANK_INTERLEAVING == 1)
354 | (SUPER_BANK_INTERLEAVING)
355#else
356 | (CACHE_LINE_INTERLEAVING)
357#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500358 | (odt_rd_cfg << 20)
359 | (odt_wr_cfg << 16)
360 | (spd.nrow_addr - 12) << 8
361 | (spd.ncol_addr - 8) );
Jon Loeligerdebb7352006-04-26 17:58:56 -0500362
Jon Loeliger9a655872006-05-19 13:26:34 -0500363 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
364 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
365
366 /*
367 * Adjustment for dual rank memory to get correct memory
368 * size (return value of this function).
369 */
370 if (n_ranks == 2) {
371 n_ranks = 1;
372 rank_density /= 2;
373 } else {
374 rank_density /= 2;
375 }
376 }
Jon Loeliger9a655872006-05-19 13:26:34 -0500377#else /* CONFIG_DDR_INTERLEAVE */
378
379 if (dimm_num == 1) {
380 /*
381 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
382 */
383 ddr->cs0_bnds = (start_addr >> 8)
384 | (((start_addr + rank_density - 1) >> 24));
385
386 ddr->cs0_config = ( 1 << 31
387 | (odt_rd_cfg << 20)
388 | (odt_wr_cfg << 16)
389 | (spd.nrow_addr - 12) << 8
390 | (spd.ncol_addr - 8) );
391
392 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
393 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
394
395 if (n_ranks == 2) {
396 /*
397 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
398 * second 256 Meg
399 */
400 ddr->cs1_bnds = (((start_addr + rank_density) >> 8)
401 | (( start_addr + 2*rank_density - 1)
402 >> 24));
403 ddr->cs1_config = ( 1<<31
404 | (odt_rd_cfg << 20)
405 | (odt_wr_cfg << 16)
406 | (spd.nrow_addr - 12) << 8
407 | (spd.ncol_addr - 8) );
408 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
409 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
410 }
411
412 } else {
413 /*
414 * This is the 2nd DIMM slot for this controller
415 */
416 /*
417 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
418 */
419 ddr->cs2_bnds = (start_addr >> 8)
420 | (((start_addr + rank_density - 1) >> 24));
421
422 ddr->cs2_config = ( 1 << 31
423 | (odt_rd_cfg << 20)
424 | (odt_wr_cfg << 16)
425 | (spd.nrow_addr - 12) << 8
426 | (spd.ncol_addr - 8) );
427
428 debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds);
429 debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config);
430
431 if (n_ranks == 2) {
432 /*
433 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
434 * second 256 Meg
435 */
436 ddr->cs3_bnds = (((start_addr + rank_density) >> 8)
437 | (( start_addr + 2*rank_density - 1)
438 >> 24));
439 ddr->cs3_config = ( 1<<31
440 | (odt_rd_cfg << 20)
441 | (odt_wr_cfg << 16)
442 | (spd.nrow_addr - 12) << 8
443 | (spd.ncol_addr - 8) );
444 debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);
445 debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config);
446 }
447 }
448#endif /* CONFIG_DDR_INTERLEAVE */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500449
450 /*
451 * Find the largest CAS by locating the highest 1 bit
452 * in the spd.cas_lat field. Translate it to a DDR
453 * controller field value:
454 *
455 * CAS Lat DDR I DDR II Ctrl
456 * Clocks SPD Bit SPD Bit Value
457 * ------- ------- ------- -----
458 * 1.0 0 0001
459 * 1.5 1 0010
460 * 2.0 2 2 0011
461 * 2.5 3 0100
462 * 3.0 4 3 0101
463 * 3.5 5 0110
464 * 4.0 4 0111
465 * 4.5 1000
466 * 5.0 5 1001
467 */
468 caslat = __ilog2(spd.cas_lat);
469 if ((spd.mem_type == SPD_MEMTYPE_DDR)
470 && (caslat > 5)) {
471 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
472 return 0;
473
474 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
475 && (caslat < 2 || caslat > 5)) {
476 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
477 spd.cas_lat);
478 return 0;
479 }
480 debug("DDR: caslat SPD bit is %d\n", caslat);
481
482 /*
483 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
484 * The SPD clk_cycle field (tCKmin) is measured in tenths of
485 * nanoseconds and represented as BCD.
486 */
487 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
488 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
489
490 /*
491 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
492 */
493 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
494 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
495
496
497 /*
498 * Adjust the CAS Latency to allow for bus speeds that
499 * are slower than the DDR module.
500 */
501 busfreq = get_bus_freq(0) / 1000000; /* MHz */
John Traillf55df182006-09-29 08:23:12 +0100502 tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3);
503 modfreq = 2 * 1000 * 1000 / tCycle_ps;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500504
John Traill91a414c2006-08-08 11:32:43 +0100505 if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) {
506 printf("DDR: platform frequency too low for correct DDR2 controller operation\n");
Jon Loeligerdebb7352006-04-26 17:58:56 -0500507 return 0;
John Traill91a414c2006-08-08 11:32:43 +0100508 } else if (busfreq < 90) {
509 printf("DDR: platform frequency too low for correct DDR1 operation\n");
Jon Loeligerdebb7352006-04-26 17:58:56 -0500510 return 0;
511 }
512
John Traill91a414c2006-08-08 11:32:43 +0100513 if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) {
514 caslat -= 2;
515 } else {
516 tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2);
517 modfreq = 2 * 1000 * 1000 / tCycle_ps;
518 if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1))))
519 caslat -= 1;
520 else if (busfreq > max_data_rate) {
521 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
522 busfreq, max_data_rate);
523 return 0;
524 }
525 }
526
527 /*
528 * Empirically set ~MCAS-to-preamble override for DDR 2.
529 * Your milage will vary.
530 */
531 cpo = 0;
532 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
533 if (busfreq <= 333) {
534 cpo = 0x7;
535 } else if (busfreq <= 400) {
536 cpo = 0x9;
537 } else {
538 cpo = 0xa;
539 }
540 }
Jon Loeligerdebb7352006-04-26 17:58:56 -0500541
542 /*
543 * Convert caslat clocks to DDR controller value.
544 * Force caslat_ctrl to be DDR Controller field-sized.
545 */
546 if (spd.mem_type == SPD_MEMTYPE_DDR) {
547 caslat_ctrl = (caslat + 1) & 0x07;
548 } else {
549 caslat_ctrl = (2 * caslat - 1) & 0x0f;
550 }
551
Jon Loeligerdebb7352006-04-26 17:58:56 -0500552 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
553 caslat, caslat_ctrl);
554
555 /*
556 * Timing Config 0.
557 * Avoid writing for DDR I. The new PQ38 DDR controller
558 * dreams up non-zero default values to be backwards compatible.
559 */
560 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
561 unsigned char taxpd_clk = 8; /* By the book. */
562 unsigned char tmrd_clk = 2; /* By the book. */
563 unsigned char act_pd_exit = 2; /* Empirical? */
564 unsigned char pre_pd_exit = 6; /* Empirical? */
565
Jon Loeliger9a655872006-05-19 13:26:34 -0500566 ddr->timing_cfg_0 = (0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500567 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
568 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
569 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
570 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
571 );
Jon Loeliger9a655872006-05-19 13:26:34 -0500572 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500573
Jon Loeligerdebb7352006-04-26 17:58:56 -0500574 }
575
576
577 /*
578 * Some Timing Config 1 values now.
579 * Sneak Extended Refresh Recovery in here too.
580 */
581
582 /*
583 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
584 * use conservative value.
585 * For DDR II, they are bytes 36 and 37, in quarter nanos.
586 */
587
588 if (spd.mem_type == SPD_MEMTYPE_DDR) {
589 twr_clk = 3; /* Clocks */
590 twtr_clk = 1; /* Clocks */
591 } else {
592 twr_clk = picos_to_clk(spd.twr * 250);
593 twtr_clk = picos_to_clk(spd.twtr * 250);
594 }
595
596 /*
597 * Calculate Trfc, in picos.
598 * DDR I: Byte 42 straight up in ns.
599 * DDR II: Byte 40 and 42 swizzled some, in ns.
600 */
601 if (spd.mem_type == SPD_MEMTYPE_DDR) {
602 trfc = spd.trfc * 1000; /* up to ps */
603 } else {
604 unsigned int byte40_table_ps[8] = {
605 0,
606 250,
607 330,
608 500,
609 660,
610 750,
611 0,
612 0
613 };
614
615 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
616 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
617 }
618 trfc_clk = picos_to_clk(trfc);
619
620 /*
621 * Trcd, Byte 29, from quarter nanos to ps and clocks.
622 */
623 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
624
625 /*
626 * Convert trfc_clk to DDR controller fields. DDR I should
627 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
628 * 8548 controller has an extended REFREC field of three bits.
629 * The controller automatically adds 8 clocks to this value,
630 * so preadjust it down 8 first before splitting it up.
631 */
632 trfc_low = (trfc_clk - 8) & 0xf;
633 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
634
635 /*
636 * Sneak in some Extended Refresh Recovery.
637 */
Jon Loeliger9a655872006-05-19 13:26:34 -0500638 ddr->ext_refrec = (trfc_high << 16);
639 debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500640
Jon Loeliger9a655872006-05-19 13:26:34 -0500641 ddr->timing_cfg_1 =
Jon Loeligerdebb7352006-04-26 17:58:56 -0500642 (0
643 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
644 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
645 | (trcd_clk << 20) /* ACTTORW */
646 | (caslat_ctrl << 16) /* CASLAT */
647 | (trfc_low << 12) /* REFEC */
648 | ((twr_clk & 0x07) << 8) /* WRRREC */
649 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
650 | ((twtr_clk & 0x07) << 0) /* WRTORD */
651 );
652
Jon Loeliger9a655872006-05-19 13:26:34 -0500653 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500654
655
656 /*
657 * Timing_Config_2
658 * Was: 0x00000800;
659 */
660
661 /*
662 * Additive Latency
663 * For DDR I, 0.
664 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
665 * which comes from Trcd, and also note that:
666 * add_lat + caslat must be >= 4
667 */
668 add_lat = 0;
669 if (spd.mem_type == SPD_MEMTYPE_DDR2
670 && (odt_wr_cfg || odt_rd_cfg)
671 && (caslat < 4)) {
672 add_lat = 4 - caslat;
John Traill91a414c2006-08-08 11:32:43 +0100673 if (add_lat >= trcd_clk) {
Jon Loeligerdebb7352006-04-26 17:58:56 -0500674 add_lat = trcd_clk - 1;
675 }
676 }
677
678 /*
679 * Write Data Delay
680 * Historically 0x2 == 4/8 clock delay.
681 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
682 */
683 wr_data_delay = 3;
684
685 /*
686 * Write Latency
687 * Read to Precharge
688 * Minimum CKE Pulse Width.
689 * Four Activate Window
690 */
691 if (spd.mem_type == SPD_MEMTYPE_DDR) {
692 /*
693 * This is a lie. It should really be 1, but if it is
694 * set to 1, bits overlap into the old controller's
695 * otherwise unused ACSM field. If we leave it 0, then
696 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
697 */
698 wr_lat = 0;
699
700 trtp_clk = 2; /* By the book. */
701 cke_min_clk = 1; /* By the book. */
702 four_act = 1; /* By the book. */
703
704 } else {
705 wr_lat = caslat - 1;
706
707 /* Convert SPD value from quarter nanos to picos. */
708 trtp_clk = picos_to_clk(spd.trtp * 250);
709
710 cke_min_clk = 3; /* By the book. */
711 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
712 }
713
Jon Loeliger9a655872006-05-19 13:26:34 -0500714 ddr->timing_cfg_2 = (0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500715 | ((add_lat & 0x7) << 28) /* ADD_LAT */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500716 | ((cpo & 0x1f) << 23) /* CPO */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500717 | ((wr_lat & 0x7) << 19) /* WR_LAT */
718 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
719 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
720 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
721 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
722 );
723
Jon Loeliger9a655872006-05-19 13:26:34 -0500724 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500725
726
727 /*
728 * Determine the Mode Register Set.
729 *
730 * This is nominally part specific, but it appears to be
731 * consistent for all DDR I devices, and for all DDR II devices.
732 *
733 * caslat must be programmed
734 * burst length is always 4
735 * burst type is sequential
736 *
737 * For DDR I:
738 * operating mode is "normal"
739 *
740 * For DDR II:
741 * other stuff
742 */
743
744 mode_caslat = 0;
745
746 /*
747 * Table lookup from DDR I or II Device Operation Specs.
748 */
749 if (spd.mem_type == SPD_MEMTYPE_DDR) {
750 if (1 <= caslat && caslat <= 4) {
751 unsigned char mode_caslat_table[4] = {
752 0x5, /* 1.5 clocks */
753 0x2, /* 2.0 clocks */
754 0x6, /* 2.5 clocks */
755 0x3 /* 3.0 clocks */
756 };
757 mode_caslat = mode_caslat_table[caslat - 1];
758 } else {
759 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
760 "2.5 and 3.0 clocks are supported.\n");
761 return 0;
762 }
763
764 } else {
765 if (2 <= caslat && caslat <= 5) {
766 mode_caslat = caslat;
767 } else {
768 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
769 "4.0 and 5.0 clocks are supported.\n");
770 return 0;
771 }
772 }
773
774 /*
Jon Loeliger9a655872006-05-19 13:26:34 -0500775 * Encoded Burst Length of 4.
Jon Loeligerdebb7352006-04-26 17:58:56 -0500776 */
777 burst_len = 2; /* Fiat. */
778
779 if (spd.mem_type == SPD_MEMTYPE_DDR) {
780 twr_auto_clk = 0; /* Historical */
781 } else {
782 /*
783 * Determine tCK max in picos. Grab tWR and convert to picos.
784 * Auto-precharge write recovery is:
785 * WR = roundup(tWR_ns/tCKmax_ns).
786 *
787 * Ponder: Is twr_auto_clk different than twr_clk?
788 */
789 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
790 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
791 }
792
Jon Loeligerdebb7352006-04-26 17:58:56 -0500793 /*
794 * Mode Reg in bits 16 ~ 31,
795 * Extended Mode Reg 1 in bits 0 ~ 15.
796 */
797 mode_odt_enable = 0x0; /* Default disabled */
798 if (odt_wr_cfg || odt_rd_cfg) {
799 /*
800 * Bits 6 and 2 in Extended MRS(1)
801 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
802 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
803 */
804 mode_odt_enable = 0x40; /* 150 Ohm */
805 }
806
Jon Loeliger9a655872006-05-19 13:26:34 -0500807 ddr->sdram_mode_1 =
Jon Loeligerdebb7352006-04-26 17:58:56 -0500808 (0
809 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
810 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
811 | (twr_auto_clk << 9) /* Write Recovery Autopre */
812 | (mode_caslat << 4) /* caslat */
813 | (burst_len << 0) /* Burst length */
814 );
815
Jon Loeliger9a655872006-05-19 13:26:34 -0500816 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500817
Jon Loeligerdebb7352006-04-26 17:58:56 -0500818 /*
819 * Clear EMRS2 and EMRS3.
820 */
Jon Loeliger9a655872006-05-19 13:26:34 -0500821 ddr->sdram_mode_2 = 0;
822 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500823
Jon Loeliger1fd56992006-10-10 17:19:03 -0500824 /*
825 * Determine Refresh Rate.
826 */
827 refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500828
829 /*
Jon Loeliger1fd56992006-10-10 17:19:03 -0500830 * Set BSTOPRE to 0x100 for page mode
831 * If auto-charge is used, set BSTOPRE = 0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500832 */
Jon Loeliger1fd56992006-10-10 17:19:03 -0500833 ddr->sdram_interval =
834 (0
835 | (refresh_clk & 0x3fff) << 16
836 | 0x100
837 );
838 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500839
Jon Loeligerdebb7352006-04-26 17:58:56 -0500840
841 /*
842 * Is this an ECC DDR chip?
843 * But don't mess with it if the DDR controller will init mem.
844 */
845#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
846 if (spd.config == 0x02) {
Jon Loeliger9a655872006-05-19 13:26:34 -0500847 ddr->err_disable = 0x0000000d;
848 ddr->err_sbe = 0x00ff0000;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500849 }
Jon Loeliger9a655872006-05-19 13:26:34 -0500850 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
851 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500852#endif
853
Jon Loeligercd6d73d2006-08-29 09:48:49 -0500854 asm volatile("sync;isync");
Jon Loeligerdebb7352006-04-26 17:58:56 -0500855 udelay(500);
856
857 /*
858 * SDRAM Cfg 2
859 */
860
861 /*
862 * When ODT is enabled, Chap 9 suggests asserting ODT to
863 * internal IOs only during reads.
864 */
865 odt_cfg = 0;
866 if (odt_rd_cfg | odt_wr_cfg) {
867 odt_cfg = 0x2; /* ODT to IOs during reads */
868 }
869
870 /*
871 * Try to use differential DQS with DDR II.
872 */
873 if (spd.mem_type == SPD_MEMTYPE_DDR) {
874 dqs_cfg = 0; /* No Differential DQS for DDR I */
875 } else {
876 dqs_cfg = 0x1; /* Differential DQS for DDR II */
877 }
878
879#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
880 /*
881 * Use the DDR controller to auto initialize memory.
882 */
883 d_init = 1;
Jon Loeliger9a655872006-05-19 13:26:34 -0500884 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
885 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500886#else
887 /*
888 * Memory will be initialized via DMA, or not at all.
889 */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500890 d_init = 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500891#endif
892
Jon Loeliger9a655872006-05-19 13:26:34 -0500893 ddr->sdram_cfg_2 = (0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500894 | (dqs_cfg << 26) /* Differential DQS */
895 | (odt_cfg << 21) /* ODT */
896 | (d_init << 4) /* D_INIT auto init DDR */
897 );
898
Jon Loeliger9a655872006-05-19 13:26:34 -0500899 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500900
901
902#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
Jon Loeliger1fd56992006-10-10 17:19:03 -0500903 /*
904 * Setup the clock control.
905 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
906 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
907 * 0110 3/4 cycle late
908 * 0111 7/8 cycle late
909 */
910 if (spd.mem_type == SPD_MEMTYPE_DDR)
911 clk_adjust = 0x6;
912 else
913 clk_adjust = 0x7;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500914
Jon Loeliger1fd56992006-10-10 17:19:03 -0500915 ddr->sdram_clk_cntl = (0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500916 | 0x80000000
917 | (clk_adjust << 23)
918 );
Jon Loeliger1fd56992006-10-10 17:19:03 -0500919 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500920#endif
921
Jon Loeligerdebb7352006-04-26 17:58:56 -0500922 /*
923 * Figure out memory size in Megabytes.
924 */
Jon Loeliger9a655872006-05-19 13:26:34 -0500925 debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500926 memsize = n_ranks * rank_density / 0x100000;
Jon Loeliger9a655872006-05-19 13:26:34 -0500927 return memsize;
928}
Jon Loeligerdebb7352006-04-26 17:58:56 -0500929
930
Jon Loeliger9a655872006-05-19 13:26:34 -0500931unsigned int enable_ddr(unsigned int ddr_num)
932{
933 volatile immap_t *immap = (immap_t *)CFG_IMMR;
934 spd_eeprom_t spd1,spd2;
935 volatile ccsr_ddr_t *ddr;
936 unsigned sdram_cfg_1;
937 unsigned char sdram_type, mem_type, config, mod_attr;
938 unsigned char d_init;
939 unsigned int no_dimm1=0, no_dimm2=0;
940
941 /* Set up pointer to enable the current ddr controller */
942 if (ddr_num == 1)
943 ddr = &immap->im_ddr1;
944 else
945 ddr = &immap->im_ddr2;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500946
947 /*
Jon Loeliger9a655872006-05-19 13:26:34 -0500948 * Read both dimm slots and decide whether
949 * or not to enable this controller.
Jon Loeligerdebb7352006-04-26 17:58:56 -0500950 */
Jon Loeliger9a655872006-05-19 13:26:34 -0500951 memset((void *)&spd1,0,sizeof(spd1));
952 memset((void *)&spd2,0,sizeof(spd2));
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500953
Jon Loeliger9a655872006-05-19 13:26:34 -0500954 if (ddr_num == 1) {
955 CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
956 0, 1, (uchar *) &spd1, sizeof(spd1));
957 CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
958 0, 1, (uchar *) &spd2, sizeof(spd2));
959 } else {
960 CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
961 0, 1, (uchar *) &spd1, sizeof(spd1));
962 CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
963 0, 1, (uchar *) &spd2, sizeof(spd2));
964 }
965
966 /*
967 * Check for supported memory module types.
968 */
969 if (spd1.mem_type != SPD_MEMTYPE_DDR
970 && spd1.mem_type != SPD_MEMTYPE_DDR2) {
971 no_dimm1 = 1;
972 } else {
973 debug("\nFound memory of type 0x%02lx ",spd1.mem_type );
974 if (spd1.mem_type == SPD_MEMTYPE_DDR)
975 debug("DDR I\n");
976 else
977 debug("DDR II\n");
978 }
979
980 if (spd2.mem_type != SPD_MEMTYPE_DDR &&
981 spd2.mem_type != SPD_MEMTYPE_DDR2) {
982 no_dimm2 = 1;
983 } else {
984 debug("\nFound memory of type 0x%02lx ",spd2.mem_type );
985 if (spd2.mem_type == SPD_MEMTYPE_DDR)
986 debug("DDR I\n");
987 else
988 debug("DDR II\n");
989 }
990
991#ifdef CONFIG_DDR_INTERLEAVE
992 if (no_dimm1) {
993 printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n");
994 return 0;
995 }
996#endif
997
998 /*
999 * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn
1000 */
1001 if (no_dimm1 && no_dimm2) {
1002 printf("No memory modules found for DDR controller %d!!\n", ddr_num);
1003 return 0;
1004 } else {
1005 mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
1006
1007 /*
1008 * Figure out the settings for the sdram_cfg register.
1009 * Build up the entire register in 'sdram_cfg' before
1010 * writing since the write into the register will
1011 * actually enable the memory controller; all settings
1012 * must be done before enabling.
1013 *
1014 * sdram_cfg[0] = 1 (ddr sdram logic enable)
1015 * sdram_cfg[1] = 1 (self-refresh-enable)
1016 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
1017 * 010 DDR 1 SDRAM
1018 * 011 DDR 2 SDRAM
1019 */
1020 sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
1021 sdram_cfg_1 = (0
1022 | (1 << 31) /* Enable */
1023 | (1 << 30) /* Self refresh */
1024 | (sdram_type << 24) /* SDRAM type */
1025 );
1026
1027 /*
1028 * sdram_cfg[3] = RD_EN - registered DIMM enable
1029 * A value of 0x26 indicates micron registered
1030 * DIMMS (micron.com)
1031 */
1032 mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr;
1033 if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) {
1034 sdram_cfg_1 |= 0x10000000; /* RD_EN */
1035 }
1036
1037#if defined(CONFIG_DDR_ECC)
1038
1039 config = no_dimm2 ? spd1.config : spd2.config;
1040
1041 /*
1042 * If the user wanted ECC (enabled via sdram_cfg[2])
1043 */
1044 if (config == 0x02) {
Haiying Wang70205e52006-05-30 08:51:19 -05001045 ddr->err_disable = 0x00000000;
Jon Loeligercd6d73d2006-08-29 09:48:49 -05001046 asm volatile("sync;isync;");
Haiying Wang70205e52006-05-30 08:51:19 -05001047 ddr->err_sbe = 0x00ff0000;
1048 ddr->err_int_en = 0x0000000d;
Jon Loeliger9a655872006-05-19 13:26:34 -05001049 sdram_cfg_1 |= 0x20000000; /* ECC_EN */
1050 }
1051#endif
1052
1053 /*
Haiying Wang70205e52006-05-30 08:51:19 -05001054 * Set 1T or 2T timing based on 1 or 2 modules
Jon Loeliger9a655872006-05-19 13:26:34 -05001055 */
1056 {
Haiying Wang70205e52006-05-30 08:51:19 -05001057 if (!(no_dimm1 || no_dimm2)) {
Jon Loeliger9a655872006-05-19 13:26:34 -05001058 /*
Haiying Wang70205e52006-05-30 08:51:19 -05001059 * 2T timing,because both DIMMS are present.
Jon Loeliger9a655872006-05-19 13:26:34 -05001060 * Enable 2T timing by setting sdram_cfg[16].
1061 */
1062 sdram_cfg_1 |= 0x8000; /* 2T_EN */
Jon Loeliger9a655872006-05-19 13:26:34 -05001063 }
1064 }
1065
1066 /*
1067 * 200 painful micro-seconds must elapse between
1068 * the DDR clock setup and the DDR config enable.
1069 */
1070 udelay(200);
1071
1072 /*
1073 * Go!
1074 */
1075 ddr->sdram_cfg_1 = sdram_cfg_1;
1076
1077 asm volatile("sync;isync");
1078 udelay(500);
1079
1080 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1);
1081
1082
1083#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1084 d_init = 1;
1085 debug("DDR: memory initializing\n");
1086
1087 /*
1088 * Poll until memory is initialized.
1089 * 512 Meg at 400 might hit this 200 times or so.
1090 */
1091 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
1092 udelay(1000);
1093 }
1094 debug("DDR: memory initialized\n\n");
1095#endif
1096
1097 debug("Enabled DDR Controller %d\n", ddr_num);
1098 return 1;
1099 }
Jon Loeligerdebb7352006-04-26 17:58:56 -05001100}
1101
Jon Loeliger9a655872006-05-19 13:26:34 -05001102
1103long int
1104spd_sdram(void)
1105{
1106 int memsize_ddr1_dimm1 = 0;
1107 int memsize_ddr1_dimm2 = 0;
1108 int memsize_ddr2_dimm1 = 0;
1109 int memsize_ddr2_dimm2 = 0;
1110 int memsize_total = 0;
1111 int memsize_ddr1 = 0;
1112 int memsize_ddr2 = 0;
1113 unsigned int ddr1_enabled = 0;
1114 unsigned int ddr2_enabled = 0;
1115 unsigned int law_size_ddr1;
1116 unsigned int law_size_ddr2;
1117 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Jon Loeliger9a655872006-05-19 13:26:34 -05001118 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
1119
1120#ifdef CONFIG_DDR_INTERLEAVE
1121 unsigned int law_size_interleaved;
Jon Loeligerea08ff62006-10-27 07:47:22 -05001122 volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
1123 volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
Jon Loeliger9a655872006-05-19 13:26:34 -05001124
1125 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1126 1, 1,
1127 (unsigned int)memsize_total * 1024*1024);
1128 memsize_total += memsize_ddr1_dimm1;
1129
1130 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1131 2, 1,
1132 (unsigned int)memsize_total * 1024*1024);
1133 memsize_total += memsize_ddr2_dimm1;
1134
1135 if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) {
1136 if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1)
1137 memsize_total -= memsize_ddr1_dimm1;
1138 else
1139 memsize_total -= memsize_ddr2_dimm1;
1140 debug("Total memory available for interleaving 0x%08lx\n",
1141 memsize_total * 1024 * 1024);
1142 debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n");
1143 ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1144 ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1145 debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds);
1146 debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds);
1147 }
1148
1149 ddr1_enabled = enable_ddr(1);
1150 ddr2_enabled = enable_ddr(2);
1151
1152 /*
1153 * Both controllers need to be enabled for interleaving.
1154 */
1155 if (ddr1_enabled && ddr2_enabled) {
1156 law_size_interleaved = 19 + __ilog2(memsize_total);
1157
1158 /*
1159 * Set up LAWBAR for DDR 1 space.
1160 */
1161 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1162 mcm->lawar1 = (LAWAR_EN
1163 | LAWAR_TRGT_IF_DDR_INTERLEAVED
1164 | (LAWAR_SIZE & law_size_interleaved));
1165 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1166 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1167 debug("Interleaved memory size is 0x%08lx\n", memsize_total);
1168
1169#ifdef CONFIG_DDR_INTERLEAVE
1170#if (CFG_PAGE_INTERLEAVING == 1)
1171 printf("Page ");
1172#elif (CFG_BANK_INTERLEAVING == 1)
1173 printf("Bank ");
1174#elif (CFG_SUPER_BANK_INTERLEAVING == 1)
1175 printf("Super-bank ");
1176#else
1177 printf("Cache-line ");
1178#endif
1179#endif
1180 printf("Interleaved");
1181 return memsize_total * 1024 * 1024;
1182 } else {
1183 printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n");
1184 return 0;
1185 }
1186
1187#else
1188 /*
1189 * Call spd_sdram() routine to init ddr1 - pass I2c address,
1190 * controller number, dimm number, and starting address.
1191 */
1192 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1193 1, 1,
1194 (unsigned int)memsize_total * 1024*1024);
1195 memsize_total += memsize_ddr1_dimm1;
1196
1197 memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
1198 1, 2,
1199 (unsigned int)memsize_total * 1024*1024);
1200 memsize_total += memsize_ddr1_dimm2;
1201
1202 /*
1203 * Enable the DDR controller - pass ddr controller number.
1204 */
1205 ddr1_enabled = enable_ddr(1);
1206
1207 /* Keep track of memory to be addressed by DDR1 */
1208 memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2;
1209
1210 /*
1211 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1212 */
1213 if (ddr1_enabled) {
1214 law_size_ddr1 = 19 + __ilog2(memsize_ddr1);
1215
1216 /*
1217 * Set up LAWBAR for DDR 1 space.
1218 */
1219 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1220 mcm->lawar1 = (LAWAR_EN
1221 | LAWAR_TRGT_IF_DDR1
1222 | (LAWAR_SIZE & law_size_ddr1));
1223 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1224 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1225 }
1226
1227#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
1228 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1229 2, 1,
1230 (unsigned int)memsize_total * 1024*1024);
1231 memsize_total += memsize_ddr2_dimm1;
1232
1233 memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4,
1234 2, 2,
1235 (unsigned int)memsize_total * 1024*1024);
1236 memsize_total += memsize_ddr2_dimm2;
1237
1238 ddr2_enabled = enable_ddr(2);
1239
1240 /* Keep track of memory to be addressed by DDR2 */
1241 memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2;
1242
1243 if (ddr2_enabled) {
1244 law_size_ddr2 = 19 + __ilog2(memsize_ddr2);
1245
1246 /*
1247 * Set up LAWBAR for DDR 2 space.
1248 */
1249 if (ddr1_enabled)
1250 mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
1251 & 0xfffff);
1252 else
1253 mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1254
1255 mcm->lawar8 = (LAWAR_EN
1256 | LAWAR_TRGT_IF_DDR2
1257 | (LAWAR_SIZE & law_size_ddr2));
1258 debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
1259 debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
1260 }
1261#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
1262
1263 debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
1264 memsize_ddr1, memsize_ddr2);
1265
1266 /*
1267 * If neither DDR controller is enabled return 0.
1268 */
1269 if (!ddr1_enabled && !ddr2_enabled)
1270 return 0;
Jon Loeliger1fd56992006-10-10 17:19:03 -05001271
1272 printf("Non-interleaved");
1273 return memsize_total * 1024 * 1024;
Jon Loeliger9a655872006-05-19 13:26:34 -05001274
1275#endif /* CONFIG_DDR_INTERLEAVE */
1276}
1277
1278
Jon Loeligerdebb7352006-04-26 17:58:56 -05001279#endif /* CONFIG_SPD_EEPROM */
1280
1281
1282#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1283
1284/*
1285 * Initialize all of memory for ECC, then enable errors.
1286 */
1287
1288void
1289ddr_enable_ecc(unsigned int dram_size)
1290{
1291 uint *p = 0;
1292 uint i = 0;
1293 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1294 volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
1295
1296 dma_init();
1297
1298 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1299 if (((unsigned int)p & 0x1f) == 0) {
1300 ppcDcbz((unsigned long) p);
1301 }
1302 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1303 if (((unsigned int)p & 0x1c) == 0x1c) {
1304 ppcDcbf((unsigned long) p);
1305 }
1306 }
1307
Jon Loeliger1fd56992006-10-10 17:19:03 -05001308 dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
1309 dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
1310 dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
1311 dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
1312 dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
1313 dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
1314 dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
1315 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
1316 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
1317 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
Jon Loeligerdebb7352006-04-26 17:58:56 -05001318
1319 for (i = 1; i < dram_size / 0x800000; i++) {
1320 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1321 }
1322
1323 /*
1324 * Enable errors for ECC.
1325 */
1326 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1327 ddr1->err_disable = 0x00000000;
Jon Loeligercd6d73d2006-08-29 09:48:49 -05001328 asm volatile("sync;isync");
Jon Loeligerdebb7352006-04-26 17:58:56 -05001329 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1330}
1331
1332#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */