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Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Wolfgang Denk843efb12009-05-16 10:47:43 +02002 * (C) Copyright 2007-2009 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <common.h>
Rafal Jaworowski8993e542007-07-27 14:43:59 +020025#include <asm/bitops.h>
26#include <command.h>
Wolfgang Denk843efb12009-05-16 10:47:43 +020027#include <asm/io.h>
John Rigby8a490422008-08-28 13:17:07 -060028#include <asm/processor.h>
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020029#include <asm/mpc512x.h>
Wolfgang Denke343ab82008-01-13 00:55:47 +010030#include <fdt_support.h>
Martha Marxf31c49d2008-05-29 14:23:25 -040031#ifdef CONFIG_MISC_INIT_R
32#include <i2c.h>
33#endif
Martha M Stana5aa3992009-09-21 14:08:00 -040034#include <net.h>
Wolfgang Denk9b55a252008-07-11 01:16:00 +020035
Stefan Roese229549a2009-06-09 16:57:47 +020036#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38
Ralph Kondziella70a4da42009-01-26 12:34:36 -070039DECLARE_GLOBAL_DATA_PTR;
40
Rafal Jaworowski8993e542007-07-27 14:43:59 +020041/* Clocks in use */
42#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
Rafal Jaworowski8993e542007-07-27 14:43:59 +020043 CLOCK_SCCR1_DDR_EN | \
Wolfgang Denk8d103072008-01-13 23:37:50 +010044 CLOCK_SCCR1_FEC_EN | \
Stefan Roese229549a2009-06-09 16:57:47 +020045 CLOCK_SCCR1_LPC_EN | \
46 CLOCK_SCCR1_NFC_EN | \
Ralph Kondziella70a4da42009-01-26 12:34:36 -070047 CLOCK_SCCR1_PATA_EN | \
John Rigby5f91db72008-02-26 09:38:14 -070048 CLOCK_SCCR1_PCI_EN | \
Stefan Roese229549a2009-06-09 16:57:47 +020049 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
50 CLOCK_SCCR1_PSCFIFO_EN | \
Wolfgang Denk8d103072008-01-13 23:37:50 +010051 CLOCK_SCCR1_TPR_EN)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020052
Stefan Roese229549a2009-06-09 16:57:47 +020053#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
54 CLOCK_SCCR2_I2C_EN | \
55 CLOCK_SCCR2_MEM_EN | \
Damien Dusha29c6fbe2010-10-14 15:27:06 +020056 CLOCK_SCCR2_SPDIF_EN | \
57 CLOCK_SCCR2_USB1_EN | \
58 CLOCK_SCCR2_USB2_EN)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020059
Stefan Roese229549a2009-06-09 16:57:47 +020060void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
61
62/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
63extern int mpc5121_nfc_chip;
64
65/* Control chips select signal on MPC5121ADS board */
66void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
67{
68 unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
69 u8 v;
70
71 v = in_8(csreg);
72 v |= 0x0F;
73
74 if (chip >= 0) {
75 __mpc5121_nfc_select_chip(mtd, 0);
76 v &= ~(1 << mpc5121_nfc_chip);
77 } else {
78 __mpc5121_nfc_select_chip(mtd, -1);
79 }
80
81 out_8(csreg, v);
82}
Rafal Jaworowski8993e542007-07-27 14:43:59 +020083
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020084int board_early_init_f(void)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020085{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020087 u32 spridr;
Rafal Jaworowski8993e542007-07-27 14:43:59 +020088
89 /*
90 * Initialize Local Window for the CPLD registers access (CS2 selects
91 * the CPLD chip)
92 */
Wolfgang Denk843efb12009-05-16 10:47:43 +020093 out_be32(&im->sysconf.lpcs2aw,
94 CSAW_START(CONFIG_SYS_CPLD_BASE) |
95 CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
96 );
97 out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020098 sync_law(&im->sysconf.lpcs2aw);
Rafal Jaworowski8993e542007-07-27 14:43:59 +020099
100 /*
101 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
102 *
103 * Without this the flash identification routine fails, as it needs to issue
104 * write commands in order to establish the device ID.
105 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200106
mark.vels@team-embedded.nl812493a2010-10-05 17:46:19 +0200107#ifdef CONFIG_MPC5121ADS_REV2
Wolfgang Denk843efb12009-05-16 10:47:43 +0200108 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
Martha Marxf31c49d2008-05-29 14:23:25 -0400109#else
Wolfgang Denk843efb12009-05-16 10:47:43 +0200110 if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
111 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
Martha Marxf31c49d2008-05-29 14:23:25 -0400112 } else {
113 /* running from Backup flash */
Wolfgang Denk843efb12009-05-16 10:47:43 +0200114 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
Martha Marxf31c49d2008-05-29 14:23:25 -0400115 }
116#endif
117 /*
118 * Configure Flash Speed
119 */
Wolfgang Denk843efb12009-05-16 10:47:43 +0200120 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
121
122 spridr = in_be32(&im->sysconf.spridr);
123
124 if (SVR_MJREV (spridr) >= 2)
125 out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
126
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200127 /*
128 * Enable clocks
129 */
Wolfgang Denk843efb12009-05-16 10:47:43 +0200130 out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
131 out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700132#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
Wolfgang Denk843efb12009-05-16 10:47:43 +0200133 setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700134#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200135
136 return 0;
137}
138
Martha M Stana5aa3992009-09-21 14:08:00 -0400139int is_micron(void){
140
141 ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
142 uchar macaddr[6];
143 u32 brddate, macchk, ismicron;
144
145 /*
146 * MAC address has serial number with date of manufacture
147 * Boards made before Nov-08 #1180 use Micron memory;
148 * 001e59 is the STx vendor #
149 * Default is Elpida since it works for both but is slightly slower
150 */
151 ismicron = 0;
152 if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
153 brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
154 macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
155 debug("brddate = %d\n\t", brddate);
156
157 if (macchk == 0x001e59 && brddate <= 8111180)
158 ismicron = 1;
159 } else if (brd_rev < 0x400) {
160 ismicron = 1;
161 }
162 debug("Using %s Memory settings\n\t",
163 ismicron ? "Micron" : "Elpida");
164 return(ismicron);
165}
166
Wolfgang Denk7629f1c2009-06-14 20:58:47 +0200167phys_size_t initdram(int board_type)
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200168{
169 u32 msize = 0;
Martha M Stana5aa3992009-09-21 14:08:00 -0400170 /*
171 * Elpida MDDRC and initialization settings are an alternative
172 * to the Default Micron ones for all but the earliest Rev 4 boards
173 */
Wolfgang Denkda01f532009-10-04 22:56:08 +0200174 ddr512x_config_t elpida_mddrc_config = {
175 .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
176 .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
177 .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
178 .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
Martha M Stana5aa3992009-09-21 14:08:00 -0400179 };
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200180
Martha M Stana5aa3992009-09-21 14:08:00 -0400181 u32 elpida_init_sequence[] = {
182 CONFIG_SYS_DDRCMD_NOP,
183 CONFIG_SYS_DDRCMD_NOP,
184 CONFIG_SYS_DDRCMD_NOP,
185 CONFIG_SYS_DDRCMD_NOP,
186 CONFIG_SYS_DDRCMD_NOP,
187 CONFIG_SYS_DDRCMD_NOP,
188 CONFIG_SYS_DDRCMD_NOP,
189 CONFIG_SYS_DDRCMD_NOP,
190 CONFIG_SYS_DDRCMD_NOP,
191 CONFIG_SYS_DDRCMD_NOP,
192 CONFIG_SYS_DDRCMD_PCHG_ALL,
193 CONFIG_SYS_DDRCMD_NOP,
194 CONFIG_SYS_DDRCMD_RFSH,
195 CONFIG_SYS_DDRCMD_NOP,
196 CONFIG_SYS_DDRCMD_RFSH,
197 CONFIG_SYS_DDRCMD_NOP,
198 CONFIG_SYS_DDRCMD_EM2,
199 CONFIG_SYS_DDRCMD_EM3,
200 CONFIG_SYS_DDRCMD_EN_DLL,
201 CONFIG_SYS_ELPIDA_RES_DLL,
202 CONFIG_SYS_DDRCMD_PCHG_ALL,
203 CONFIG_SYS_DDRCMD_RFSH,
204 CONFIG_SYS_DDRCMD_RFSH,
205 CONFIG_SYS_DDRCMD_RFSH,
206 CONFIG_SYS_ELPIDA_INIT_DEV_OP,
207 CONFIG_SYS_DDRCMD_NOP,
208 CONFIG_SYS_DDRCMD_NOP,
209 CONFIG_SYS_DDRCMD_NOP,
210 CONFIG_SYS_DDRCMD_NOP,
211 CONFIG_SYS_DDRCMD_NOP,
212 CONFIG_SYS_DDRCMD_NOP,
213 CONFIG_SYS_DDRCMD_NOP,
214 CONFIG_SYS_DDRCMD_NOP,
215 CONFIG_SYS_DDRCMD_NOP,
216 CONFIG_SYS_DDRCMD_NOP,
217 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
218 CONFIG_SYS_ELPIDA_OCD_EXIT,
219 CONFIG_SYS_DDRCMD_NOP,
220 CONFIG_SYS_DDRCMD_NOP,
221 CONFIG_SYS_DDRCMD_NOP,
222 CONFIG_SYS_DDRCMD_NOP,
223 CONFIG_SYS_DDRCMD_NOP,
224 CONFIG_SYS_DDRCMD_NOP,
225 CONFIG_SYS_DDRCMD_NOP,
226 CONFIG_SYS_DDRCMD_NOP,
227 CONFIG_SYS_DDRCMD_NOP,
228 CONFIG_SYS_DDRCMD_NOP
229 };
230
231 if (is_micron()) {
232 msize = fixed_sdram(NULL, NULL, 0);
233 } else {
Wolfgang Denkda01f532009-10-04 22:56:08 +0200234 msize = fixed_sdram(&elpida_mddrc_config,
Martha M Stana5aa3992009-09-21 14:08:00 -0400235 elpida_init_sequence,
236 sizeof(elpida_init_sequence)/sizeof(u32));
237 }
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200238
239 return msize;
240}
241
York Sun0e1bad42008-05-05 10:20:01 -0500242int misc_init_r(void)
243{
244 u8 tmp_val;
245
246 /* Using this for DIU init before the driver in linux takes over
247 * Enable the TFP410 Encoder (I2C address 0x38)
248 */
249
250 i2c_set_bus_num(2);
251 tmp_val = 0xBF;
252 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
253 /* Verify if enabled */
254 tmp_val = 0;
255 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
256 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
257
258 tmp_val = 0x10;
259 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
260 /* Verify if enabled */
261 tmp_val = 0;
262 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
263 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
264
York Sun0e1bad42008-05-05 10:20:01 -0500265 return 0;
266}
Wolfgang Denk72601d02009-05-16 10:47:41 +0200267
Kenneth Johansson66894842008-07-15 12:13:38 +0200268static iopin_t ioregs_init[] = {
269 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
270 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200271 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200272 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
273 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
274 },
275 /* Set highest Slew on 9 PATA pins */
276 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200277 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
Kenneth Johansson66894842008-07-15 12:13:38 +0200278 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
279 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
280 },
281 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
282 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200283 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200284 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
285 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
286 },
287 /* FUNC1=SPDIF_TXCLK */
288 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200289 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200290 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
291 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
292 },
293 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
294 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200295 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200296 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
297 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
298 },
299 /* FUNC2=DIU CLK */
300 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200301 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200302 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
303 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
304 },
305 /* FUNC2=DIU_HSYNC */
306 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200307 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200308 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
309 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
310 },
311 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
312 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200313 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200314 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
315 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
316 }
317};
York Sun0e1bad42008-05-05 10:20:01 -0500318
John Rigby14d19cd2009-01-23 10:33:15 -0700319static iopin_t rev2_silicon_pci_ioregs_init[] = {
320 /* FUNC0=PCI Sets next 54 to PCI pads */
321 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200322 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
John Rigby14d19cd2009-01-23 10:33:15 -0700323 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
324 }
325};
326
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200327int checkboard (void)
328{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329 ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
330 uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
John Rigby14d19cd2009-01-23 10:33:15 -0700331 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk843efb12009-05-16 10:47:43 +0200332 u32 spridr = in_be32(&im->sysconf.spridr);
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200333
mark.vels@team-embedded.nl812493a2010-10-05 17:46:19 +0200334 printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
Wolfgang Denkb1b54e32007-08-02 21:27:46 +0200335 brd_rev, cpld_rev);
Kenneth Johansson66894842008-07-15 12:13:38 +0200336
Wolfgang Denk72601d02009-05-16 10:47:41 +0200337 /* initialize function mux & slew rate IO inter alia on IO Pins */
338 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
339
Wolfgang Denk843efb12009-05-16 10:47:43 +0200340 if (SVR_MJREV (spridr) >= 2)
John Rigby14d19cd2009-01-23 10:33:15 -0700341 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
John Rigby51b67d02007-08-24 18:18:43 -0600342
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200343 return 0;
344}
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100345
346#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
347void ft_board_setup(void *blob, bd_t *bd)
348{
349 ft_cpu_setup(blob, bd);
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100350}
351#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */