Carlo Caione | 4b3ab59 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Configuration for Amlogic Meson GXBB SoCs |
| 3 | * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef __MESON_GXBB_COMMON_CONFIG_H |
| 9 | #define __MESON_GXBB_COMMON_CONFIG_H |
| 10 | |
| 11 | #define CONFIG_CPU_ARMV8 |
| 12 | #define CONFIG_REMAKE_ELF |
xypron.glpk@gmx.de | e42f096 | 2017-06-09 22:13:59 +0200 | [diff] [blame] | 13 | #define CONFIG_NR_DRAM_BANKS 2 |
Carlo Caione | 4b3ab59 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 14 | #define CONFIG_ENV_SIZE 0x2000 |
| 15 | #define CONFIG_SYS_MAXARGS 32 |
| 16 | #define CONFIG_SYS_MALLOC_LEN (32 << 20) |
| 17 | #define CONFIG_SYS_CBSIZE 1024 |
Carlo Caione | 4b3ab59 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 18 | |
| 19 | #define CONFIG_SYS_SDRAM_BASE 0 |
| 20 | #define CONFIG_SYS_TEXT_BASE 0x01000000 |
| 21 | #define CONFIG_SYS_INIT_SP_ADDR 0x20000000 |
| 22 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE |
| 23 | |
| 24 | /* Generic Interrupt Controller Definitions */ |
| 25 | #define GICD_BASE 0xc4301000 |
| 26 | #define GICC_BASE 0xc4302000 |
| 27 | |
Carlo Caione | 4b3ab59 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 28 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 29 | #define CONFIG_SYS_LONGHELP |
| 30 | #define CONFIG_CMDLINE_EDITING |
| 31 | |
| 32 | #include <config_distro_defaults.h> |
| 33 | |
Andreas Färber | 70b8bd7 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 34 | #define BOOT_TARGET_DEVICES(func) \ |
xypron.glpk@gmx.de | 1f677e4 | 2017-04-15 21:30:39 +0200 | [diff] [blame] | 35 | func(MMC, mmc, 0) \ |
| 36 | func(MMC, mmc, 1) \ |
| 37 | func(MMC, mmc, 2) \ |
Vagrant Cascadian | e320d37 | 2017-05-05 14:11:26 -0700 | [diff] [blame] | 38 | func(PXE, pxe, na) \ |
Andreas Färber | 70b8bd7 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 39 | func(DHCP, dhcp, na) |
| 40 | |
| 41 | #include <config_distro_bootcmd.h> |
| 42 | |
| 43 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 44 | "fdt_addr_r=0x01000000\0" \ |
| 45 | "scriptaddr=0x1f000000\0" \ |
| 46 | "kernel_addr_r=0x01080000\0" \ |
| 47 | "pxefile_addr_r=0x01080000\0" \ |
xypron.glpk@gmx.de | d038574 | 2017-04-14 20:04:46 +0200 | [diff] [blame] | 48 | "ramdisk_addr_r=0x13000000\0" \ |
Andreas Färber | 70b8bd7 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 49 | MESON_FDTFILE_SETTING \ |
| 50 | BOOTENV |
| 51 | |
xypron.glpk@gmx.de | cc93834 | 2017-04-14 19:54:40 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ |
| 53 | |
Carlo Caione | 4b3ab59 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 54 | #endif /* __MESON_GXBB_COMMON_CONFIG_H */ |