Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 2 | /* |
TsiChungLiew | 2bd806f | 2007-07-05 23:17:36 -0500 | [diff] [blame] | 3 | * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 4 | * TsiChung Liew, Tsi-Chung.Liew@freescale.com. |
| 5 | * |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 6 | * Modified to add device model (DM) support |
| 7 | * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> |
Angelo Dureghello | 461ea07 | 2019-03-13 21:46:49 +0100 | [diff] [blame] | 8 | * |
| 9 | * Modified to add DM and fdt support, removed non DM code |
| 10 | * (C) Copyright 2018 Angelo Dureghello <angelo@sysam.it> |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Minimal serial functions needed to use one of the uart ports |
| 15 | * as serial console interface. |
| 16 | */ |
| 17 | |
| 18 | #include <common.h> |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 19 | #include <dm.h> |
| 20 | #include <dm/platform_data/serial_coldfire.h> |
Alison Wang | 39c7a26 | 2012-10-18 16:54:38 +0000 | [diff] [blame] | 21 | #include <serial.h> |
| 22 | #include <linux/compiler.h> |
TsiChungLiew | 2bd806f | 2007-07-05 23:17:36 -0500 | [diff] [blame] | 23 | #include <asm/immap.h> |
| 24 | #include <asm/uart.h> |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
TsiChung Liew | fa9da59 | 2010-03-09 19:24:43 -0600 | [diff] [blame] | 28 | extern void uart_port_conf(int port); |
TsiChungLiew | 8d1d66a | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 29 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 30 | static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate) |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 31 | { |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 32 | u32 counter; |
| 33 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 34 | uart_port_conf(port_idx); |
TsiChungLiew | 8d1d66a | 2007-08-05 03:55:21 -0500 | [diff] [blame] | 35 | |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 36 | /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 37 | writeb(UART_UCR_RESET_RX, &uart->ucr); |
| 38 | writeb(UART_UCR_RESET_TX, &uart->ucr); |
| 39 | writeb(UART_UCR_RESET_ERROR, &uart->ucr); |
| 40 | writeb(UART_UCR_RESET_MR, &uart->ucr); |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 41 | __asm__("nop"); |
| 42 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 43 | writeb(0, &uart->uimr); |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 44 | |
| 45 | /* write to CSR: RX/TX baud rate from timers */ |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 46 | writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 47 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 48 | writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); |
| 49 | writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 50 | |
| 51 | /* Setting up BaudRate */ |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 52 | counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2)); |
| 53 | counter = counter / baudrate; |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 54 | |
| 55 | /* write to CTUR: divide counter upper byte */ |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 56 | writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1); |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 57 | /* write to CTLR: divide counter lower byte */ |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 58 | writeb((u8)(counter & 0x00ff), &uart->ubg2); |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 59 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 60 | writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); |
TsiChung Liew | 8e585f0 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 61 | |
| 62 | return (0); |
| 63 | } |
| 64 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 65 | static void mcf_serial_setbrg_common(uart_t *uart, int baudrate) |
| 66 | { |
| 67 | u32 counter; |
| 68 | |
| 69 | /* Setting up BaudRate */ |
| 70 | counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2)); |
| 71 | counter = counter / baudrate; |
| 72 | |
| 73 | /* write to CTUR: divide counter upper byte */ |
| 74 | writeb(((counter & 0xff00) >> 8), &uart->ubg1); |
| 75 | /* write to CTLR: divide counter lower byte */ |
| 76 | writeb((counter & 0x00ff), &uart->ubg2); |
| 77 | |
| 78 | writeb(UART_UCR_RESET_RX, &uart->ucr); |
| 79 | writeb(UART_UCR_RESET_TX, &uart->ucr); |
| 80 | |
| 81 | writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); |
| 82 | } |
| 83 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 84 | static int coldfire_serial_probe(struct udevice *dev) |
| 85 | { |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 86 | struct coldfire_serial_plat *plat = dev->plat; |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 87 | |
Angelo Durgehello | ce5e3ea | 2020-02-29 01:01:32 +0100 | [diff] [blame] | 88 | plat->port = dev->seq; |
| 89 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 90 | return mcf_serial_init_common((uart_t *)plat->base, |
| 91 | plat->port, plat->baudrate); |
| 92 | } |
| 93 | |
| 94 | static int coldfire_serial_putc(struct udevice *dev, const char ch) |
| 95 | { |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 96 | struct coldfire_serial_plat *plat = dev->plat; |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 97 | uart_t *uart = (uart_t *)plat->base; |
| 98 | |
| 99 | /* Wait for last character to go. */ |
| 100 | if (!(readb(&uart->usr) & UART_USR_TXRDY)) |
| 101 | return -EAGAIN; |
| 102 | |
| 103 | writeb(ch, &uart->utb); |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | static int coldfire_serial_getc(struct udevice *dev) |
| 109 | { |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 110 | struct coldfire_serial_plat *plat = dev->plat; |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 111 | uart_t *uart = (uart_t *)(plat->base); |
| 112 | |
| 113 | /* Wait for a character to arrive. */ |
| 114 | if (!(readb(&uart->usr) & UART_USR_RXRDY)) |
| 115 | return -EAGAIN; |
| 116 | |
| 117 | return readb(&uart->urb); |
| 118 | } |
| 119 | |
| 120 | int coldfire_serial_setbrg(struct udevice *dev, int baudrate) |
| 121 | { |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 122 | struct coldfire_serial_plat *plat = dev->plat; |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 123 | uart_t *uart = (uart_t *)(plat->base); |
| 124 | |
| 125 | mcf_serial_setbrg_common(uart, baudrate); |
| 126 | |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | static int coldfire_serial_pending(struct udevice *dev, bool input) |
| 131 | { |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 132 | struct coldfire_serial_plat *plat = dev->plat; |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 133 | uart_t *uart = (uart_t *)(plat->base); |
| 134 | |
| 135 | if (input) |
| 136 | return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0; |
| 137 | else |
| 138 | return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1; |
| 139 | |
| 140 | return 0; |
| 141 | } |
| 142 | |
Simon Glass | d1998a9 | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 143 | static int coldfire_of_to_plat(struct udevice *dev) |
Angelo Dureghello | 461ea07 | 2019-03-13 21:46:49 +0100 | [diff] [blame] | 144 | { |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 145 | struct coldfire_serial_plat *plat = dev_get_plat(dev); |
Angelo Dureghello | 461ea07 | 2019-03-13 21:46:49 +0100 | [diff] [blame] | 146 | fdt_addr_t addr_base; |
| 147 | |
Masahiro Yamada | 2548493 | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 148 | addr_base = dev_read_addr(dev); |
Angelo Dureghello | 461ea07 | 2019-03-13 21:46:49 +0100 | [diff] [blame] | 149 | if (addr_base == FDT_ADDR_T_NONE) |
| 150 | return -ENODEV; |
| 151 | |
| 152 | plat->base = (uint32_t)addr_base; |
Angelo Dureghello | 461ea07 | 2019-03-13 21:46:49 +0100 | [diff] [blame] | 153 | plat->baudrate = gd->baudrate; |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 158 | static const struct dm_serial_ops coldfire_serial_ops = { |
| 159 | .putc = coldfire_serial_putc, |
| 160 | .pending = coldfire_serial_pending, |
| 161 | .getc = coldfire_serial_getc, |
| 162 | .setbrg = coldfire_serial_setbrg, |
| 163 | }; |
| 164 | |
Angelo Dureghello | 461ea07 | 2019-03-13 21:46:49 +0100 | [diff] [blame] | 165 | static const struct udevice_id coldfire_serial_ids[] = { |
| 166 | { .compatible = "fsl,mcf-uart" }, |
| 167 | { } |
| 168 | }; |
| 169 | |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 170 | U_BOOT_DRIVER(serial_coldfire) = { |
| 171 | .name = "serial_coldfire", |
| 172 | .id = UCLASS_SERIAL, |
Angelo Dureghello | 461ea07 | 2019-03-13 21:46:49 +0100 | [diff] [blame] | 173 | .of_match = coldfire_serial_ids, |
Simon Glass | d1998a9 | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 174 | .of_to_plat = coldfire_of_to_plat, |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 175 | .plat_auto = sizeof(struct coldfire_serial_plat), |
angelo@sysam.it | e27802a | 2016-04-27 21:51:13 +0200 | [diff] [blame] | 176 | .probe = coldfire_serial_probe, |
| 177 | .ops = &coldfire_serial_ops, |
| 178 | .flags = DM_FLAG_PRE_RELOC, |
| 179 | }; |