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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +00002/*
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Padmavathi Venna <padma.v@samsung.com>
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +00005 */
6
7#include <common.h>
Simon Glass73186c92014-10-13 23:42:01 -06008#include <dm.h>
9#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000011#include <malloc.h>
12#include <spi.h>
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000013#include <fdtdec.h>
Simon Glass10453152019-11-14 12:57:30 -070014#include <time.h>
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000015#include <asm/arch/clk.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/cpu.h>
18#include <asm/arch/gpio.h>
19#include <asm/arch/pinmux.h>
Thomas Abraham77b55e82015-08-03 17:58:00 +053020#include <asm/arch/spi.h>
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000021#include <asm/io.h>
Simon Glassc05ed002020-05-10 11:40:11 -060022#include <linux/delay.h>
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000023
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000024DECLARE_GLOBAL_DATA_PTR;
25
Simon Glass8a8d24b2020-12-03 16:55:23 -070026struct exynos_spi_plat {
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000027 enum periph_id periph_id;
28 s32 frequency; /* Default clock frequency, -1 for none */
29 struct exynos_spi *regs;
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +053030 uint deactivate_delay_us; /* Delay to wait after deactivate */
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000031};
32
Simon Glass73186c92014-10-13 23:42:01 -060033struct exynos_spi_priv {
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000034 struct exynos_spi *regs;
35 unsigned int freq; /* Default frequency */
36 unsigned int mode;
37 enum periph_id periph_id; /* Peripheral ID for this device */
38 unsigned int fifo_size;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +000039 int skip_preamble;
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +053040 ulong last_transaction_us; /* Time of last transaction end */
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000041};
42
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000043/**
44 * Flush spi tx, rx fifos and reset the SPI controller
45 *
Simon Glass73186c92014-10-13 23:42:01 -060046 * @param regs Pointer to SPI registers
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000047 */
Simon Glass73186c92014-10-13 23:42:01 -060048static void spi_flush_fifo(struct exynos_spi *regs)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000049{
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000050 clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
51 clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
52 setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
53}
54
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000055static void spi_get_fifo_levels(struct exynos_spi *regs,
56 int *rx_lvl, int *tx_lvl)
57{
58 uint32_t spi_sts = readl(&regs->spi_sts);
59
60 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
61 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
62}
63
64/**
65 * If there's something to transfer, do a software reset and set a
66 * transaction size.
67 *
68 * @param regs SPI peripheral registers
69 * @param count Number of bytes to transfer
Rajeshwari Shindec4a79632013-10-08 16:20:06 +053070 * @param step Number of bytes to transfer in each packet (1 or 4)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000071 */
Rajeshwari Shindec4a79632013-10-08 16:20:06 +053072static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000073{
Simon Glass73186c92014-10-13 23:42:01 -060074 debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
75
Rajeshwari Shindec4a79632013-10-08 16:20:06 +053076 /* For word address we need to swap bytes */
77 if (step == 4) {
78 setbits_le32(&regs->mode_cfg,
79 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
80 count /= 4;
81 setbits_le32(&regs->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
82 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
83 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
84 } else {
85 /* Select byte access and clear the swap configuration */
86 clrbits_le32(&regs->mode_cfg,
87 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
88 writel(0, &regs->swap_cfg);
89 }
90
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000091 assert(count && count < (1 << 16));
92 setbits_le32(&regs->ch_cfg, SPI_CH_RST);
93 clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +053094
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000095 writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
96}
97
Simon Glass73186c92014-10-13 23:42:01 -060098static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +000099 void **dinp, void const **doutp, unsigned long flags)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000100{
Simon Glass73186c92014-10-13 23:42:01 -0600101 struct exynos_spi *regs = priv->regs;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000102 uchar *rxp = *dinp;
103 const uchar *txp = *doutp;
104 int rx_lvl, tx_lvl;
105 uint out_bytes, in_bytes;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000106 int toread;
107 unsigned start = get_timer(0);
108 int stopping;
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530109 int step;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000110
111 out_bytes = in_bytes = todo;
112
Simon Glass73186c92014-10-13 23:42:01 -0600113 stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
114 !(priv->mode & SPI_SLAVE);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000115
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000116 /*
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530117 * Try to transfer words if we can. This helps read performance at
118 * SPI clock speeds above about 20MHz.
119 */
120 step = 1;
121 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
Simon Glass73186c92014-10-13 23:42:01 -0600122 !priv->skip_preamble)
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530123 step = 4;
124
125 /*
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000126 * If there's something to send, do a software reset and set a
127 * transaction size.
128 */
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530129 spi_request_bytes(regs, todo, step);
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000130
131 /*
132 * Bytes are transmitted/received in pairs. Wait to receive all the
133 * data because then transmission will be done as well.
134 */
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000135 toread = in_bytes;
136
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000137 while (in_bytes) {
138 int temp;
139
140 /* Keep the fifos full/empty. */
141 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530142
143 /*
144 * Don't completely fill the txfifo, since we don't want our
145 * rxfifo to overflow, and it may already contain data.
146 */
Simon Glass73186c92014-10-13 23:42:01 -0600147 while (tx_lvl < priv->fifo_size/2 && out_bytes) {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530148 if (!txp)
149 temp = -1;
150 else if (step == 4)
151 temp = *(uint32_t *)txp;
152 else
153 temp = *txp;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000154 writel(temp, &regs->tx_data);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530155 out_bytes -= step;
156 if (txp)
157 txp += step;
158 tx_lvl += step;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000159 }
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530160 if (rx_lvl >= step) {
161 while (rx_lvl >= step) {
Rajeshwari Shinde120af152013-10-08 16:20:05 +0530162 temp = readl(&regs->rx_data);
Simon Glass73186c92014-10-13 23:42:01 -0600163 if (priv->skip_preamble) {
Rajeshwari Shinde120af152013-10-08 16:20:05 +0530164 if (temp == SPI_PREAMBLE_END_BYTE) {
Simon Glass73186c92014-10-13 23:42:01 -0600165 priv->skip_preamble = 0;
Rajeshwari Shinde120af152013-10-08 16:20:05 +0530166 stopping = 0;
167 }
168 } else {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530169 if (rxp || stopping) {
Akshay Saraswate76d2a82014-06-18 17:52:41 +0530170 if (step == 4)
171 *(uint32_t *)rxp = temp;
172 else
173 *rxp = temp;
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530174 rxp += step;
175 }
176 in_bytes -= step;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000177 }
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530178 toread -= step;
179 rx_lvl -= step;
180 }
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000181 } else if (!toread) {
182 /*
183 * We have run out of input data, but haven't read
184 * enough bytes after the preamble yet. Read some more,
185 * and make sure that we transmit dummy bytes too, to
186 * keep things going.
187 */
188 assert(!out_bytes);
189 out_bytes = in_bytes;
190 toread = in_bytes;
191 txp = NULL;
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530192 spi_request_bytes(regs, toread, step);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000193 }
Simon Glass73186c92014-10-13 23:42:01 -0600194 if (priv->skip_preamble && get_timer(start) > 100) {
Simon Glassc7d50e72015-07-02 18:16:11 -0600195 debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
196 in_bytes, out_bytes);
197 return -ETIMEDOUT;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000198 }
199 }
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000200
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000201 *dinp = rxp;
202 *doutp = txp;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000203
204 return 0;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000205}
206
207/**
Simon Glass73186c92014-10-13 23:42:01 -0600208 * Activate the CS by driving it LOW
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000209 *
Simon Glass73186c92014-10-13 23:42:01 -0600210 * @param slave Pointer to spi_slave to which controller has to
211 * communicate with
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000212 */
Simon Glass73186c92014-10-13 23:42:01 -0600213static void spi_cs_activate(struct udevice *dev)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000214{
Simon Glass73186c92014-10-13 23:42:01 -0600215 struct udevice *bus = dev->parent;
Simon Glass8a8d24b2020-12-03 16:55:23 -0700216 struct exynos_spi_plat *pdata = dev_get_plat(bus);
Simon Glass73186c92014-10-13 23:42:01 -0600217 struct exynos_spi_priv *priv = dev_get_priv(bus);
218
219 /* If it's too soon to do another transaction, wait */
220 if (pdata->deactivate_delay_us &&
221 priv->last_transaction_us) {
222 ulong delay_us; /* The delay completed so far */
223 delay_us = timer_get_us() - priv->last_transaction_us;
224 if (delay_us < pdata->deactivate_delay_us)
225 udelay(pdata->deactivate_delay_us - delay_us);
226 }
227
228 clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
229 debug("Activate CS, bus '%s'\n", bus->name);
230 priv->skip_preamble = priv->mode & SPI_PREAMBLE;
231}
232
233/**
234 * Deactivate the CS by driving it HIGH
235 *
236 * @param slave Pointer to spi_slave to which controller has to
237 * communicate with
238 */
239static void spi_cs_deactivate(struct udevice *dev)
240{
241 struct udevice *bus = dev->parent;
Simon Glass8a8d24b2020-12-03 16:55:23 -0700242 struct exynos_spi_plat *pdata = dev_get_plat(bus);
Simon Glass73186c92014-10-13 23:42:01 -0600243 struct exynos_spi_priv *priv = dev_get_priv(bus);
244
245 setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
246
247 /* Remember time of this transaction so we can honour the bus delay */
248 if (pdata->deactivate_delay_us)
249 priv->last_transaction_us = timer_get_us();
250
251 debug("Deactivate CS, bus '%s'\n", bus->name);
252}
253
Simon Glassd1998a92020-12-03 16:55:21 -0700254static int exynos_spi_of_to_plat(struct udevice *bus)
Simon Glass73186c92014-10-13 23:42:01 -0600255{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700256 struct exynos_spi_plat *plat = bus->plat;
Simon Glass73186c92014-10-13 23:42:01 -0600257 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700258 int node = dev_of_offset(bus);
Simon Glass73186c92014-10-13 23:42:01 -0600259
Masahiro Yamada8613c8d2020-07-17 14:36:46 +0900260 plat->regs = dev_read_addr_ptr(bus);
Simon Glass73186c92014-10-13 23:42:01 -0600261 plat->periph_id = pinmux_decode_periph_id(blob, node);
262
263 if (plat->periph_id == PERIPH_ID_NONE) {
264 debug("%s: Invalid peripheral ID %d\n", __func__,
265 plat->periph_id);
266 return -FDT_ERR_NOTFOUND;
267 }
268
269 /* Use 500KHz as a suitable default */
270 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
271 500000);
272 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
273 "spi-deactivate-delay", 0);
274 debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
275 __func__, plat->regs, plat->periph_id, plat->frequency,
276 plat->deactivate_delay_us);
277
278 return 0;
279}
280
281static int exynos_spi_probe(struct udevice *bus)
282{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700283 struct exynos_spi_plat *plat = dev_get_plat(bus);
Simon Glass73186c92014-10-13 23:42:01 -0600284 struct exynos_spi_priv *priv = dev_get_priv(bus);
285
286 priv->regs = plat->regs;
287 if (plat->periph_id == PERIPH_ID_SPI1 ||
288 plat->periph_id == PERIPH_ID_SPI2)
289 priv->fifo_size = 64;
290 else
291 priv->fifo_size = 256;
292
293 priv->skip_preamble = 0;
294 priv->last_transaction_us = timer_get_us();
295 priv->freq = plat->frequency;
296 priv->periph_id = plat->periph_id;
297
298 return 0;
299}
300
Simon Glass9694b722015-04-19 09:05:40 -0600301static int exynos_spi_claim_bus(struct udevice *dev)
Simon Glass73186c92014-10-13 23:42:01 -0600302{
Simon Glass9694b722015-04-19 09:05:40 -0600303 struct udevice *bus = dev->parent;
Simon Glass73186c92014-10-13 23:42:01 -0600304 struct exynos_spi_priv *priv = dev_get_priv(bus);
305
306 exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
307 spi_flush_fifo(priv->regs);
308
309 writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
310
311 return 0;
312}
313
Simon Glass9694b722015-04-19 09:05:40 -0600314static int exynos_spi_release_bus(struct udevice *dev)
Simon Glass73186c92014-10-13 23:42:01 -0600315{
Simon Glass9694b722015-04-19 09:05:40 -0600316 struct udevice *bus = dev->parent;
Simon Glass73186c92014-10-13 23:42:01 -0600317 struct exynos_spi_priv *priv = dev_get_priv(bus);
318
319 spi_flush_fifo(priv->regs);
320
321 return 0;
322}
323
324static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
325 const void *dout, void *din, unsigned long flags)
326{
327 struct udevice *bus = dev->parent;
328 struct exynos_spi_priv *priv = dev_get_priv(bus);
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000329 int upto, todo;
330 int bytelen;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000331 int ret = 0;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000332
333 /* spi core configured to do 8 bit transfers */
334 if (bitlen % 8) {
335 debug("Non byte aligned SPI transfer.\n");
336 return -1;
337 }
338
339 /* Start the transaction, if necessary. */
340 if ((flags & SPI_XFER_BEGIN))
Simon Glass73186c92014-10-13 23:42:01 -0600341 spi_cs_activate(dev);
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000342
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530343 /*
344 * Exynos SPI limits each transfer to 65535 transfers. To keep
345 * things simple, allow a maximum of 65532 bytes. We could allow
346 * more in word mode, but the performance difference is small.
347 */
Simon Glass73186c92014-10-13 23:42:01 -0600348 bytelen = bitlen / 8;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000349 for (upto = 0; !ret && upto < bytelen; upto += todo) {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530350 todo = min(bytelen - upto, (1 << 16) - 4);
Simon Glass73186c92014-10-13 23:42:01 -0600351 ret = spi_rx_tx(priv, todo, &din, &dout, flags);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000352 if (ret)
353 break;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000354 }
355
356 /* Stop the transaction, if necessary. */
Simon Glass73186c92014-10-13 23:42:01 -0600357 if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
358 spi_cs_deactivate(dev);
359 if (priv->skip_preamble) {
360 assert(!priv->skip_preamble);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000361 debug("Failed to complete premable transaction\n");
362 ret = -1;
363 }
364 }
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000365
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000366 return ret;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000367}
368
Simon Glass73186c92014-10-13 23:42:01 -0600369static int exynos_spi_set_speed(struct udevice *bus, uint speed)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000370{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700371 struct exynos_spi_plat *plat = bus->plat;
Simon Glass73186c92014-10-13 23:42:01 -0600372 struct exynos_spi_priv *priv = dev_get_priv(bus);
373 int ret;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000374
Simon Glass73186c92014-10-13 23:42:01 -0600375 if (speed > plat->frequency)
376 speed = plat->frequency;
377 ret = set_spi_clk(priv->periph_id, speed);
378 if (ret)
379 return ret;
380 priv->freq = speed;
381 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000382
383 return 0;
384}
385
Simon Glass73186c92014-10-13 23:42:01 -0600386static int exynos_spi_set_mode(struct udevice *bus, uint mode)
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000387{
Simon Glass73186c92014-10-13 23:42:01 -0600388 struct exynos_spi_priv *priv = dev_get_priv(bus);
389 uint32_t reg;
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000390
Simon Glass73186c92014-10-13 23:42:01 -0600391 reg = readl(&priv->regs->ch_cfg);
392 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000393
Simon Glass73186c92014-10-13 23:42:01 -0600394 if (mode & SPI_CPHA)
395 reg |= SPI_CH_CPHA_B;
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000396
Simon Glass73186c92014-10-13 23:42:01 -0600397 if (mode & SPI_CPOL)
398 reg |= SPI_CH_CPOL_L;
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000399
Simon Glass73186c92014-10-13 23:42:01 -0600400 writel(reg, &priv->regs->ch_cfg);
401 priv->mode = mode;
402 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000403
404 return 0;
405}
406
Simon Glass73186c92014-10-13 23:42:01 -0600407static const struct dm_spi_ops exynos_spi_ops = {
408 .claim_bus = exynos_spi_claim_bus,
409 .release_bus = exynos_spi_release_bus,
410 .xfer = exynos_spi_xfer,
411 .set_speed = exynos_spi_set_speed,
412 .set_mode = exynos_spi_set_mode,
413 /*
414 * cs_info is not needed, since we require all chip selects to be
415 * in the device tree explicitly
416 */
417};
Hung-ying Tyanf3424c52013-05-15 18:27:30 +0800418
Simon Glass73186c92014-10-13 23:42:01 -0600419static const struct udevice_id exynos_spi_ids[] = {
420 { .compatible = "samsung,exynos-spi" },
421 { }
422};
Hung-ying Tyanf3424c52013-05-15 18:27:30 +0800423
Simon Glass73186c92014-10-13 23:42:01 -0600424U_BOOT_DRIVER(exynos_spi) = {
425 .name = "exynos_spi",
426 .id = UCLASS_SPI,
427 .of_match = exynos_spi_ids,
428 .ops = &exynos_spi_ops,
Simon Glassd1998a92020-12-03 16:55:21 -0700429 .of_to_plat = exynos_spi_of_to_plat,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700430 .plat_auto = sizeof(struct exynos_spi_plat),
Simon Glass41575d82020-12-03 16:55:17 -0700431 .priv_auto = sizeof(struct exynos_spi_priv),
Simon Glass73186c92014-10-13 23:42:01 -0600432 .probe = exynos_spi_probe,
433};