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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -05002/*
Nikita Kiryanov9fc376b2012-01-02 04:01:30 +00003 * (C) Copyright 2011 CompuLab, Ltd.
Mike Rapoport36b4e2d2010-12-18 17:43:19 -05004 * Mike Rapoport <mike@compulab.co.il>
Igor Grinbergdccd9a02011-04-18 17:48:31 -04005 * Igor Grinberg <grinberg@compulab.co.il>
Mike Rapoport36b4e2d2010-12-18 17:43:19 -05006 *
7 * Based on omap3_beagle.h
8 * (C) Copyright 2006-2008
9 * Texas Instruments.
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <x0khasim@ti.com>
12 *
Igor Grinbergb65a77a2011-04-18 17:55:21 -040013 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050014 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
Albert ARIBAUD37098442016-01-27 08:46:11 +010019#define CONFIG_SYS_CACHELINE_SIZE 64
20
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050021/*
22 * High Level Configuration Options
23 */
Nikita Kiryanov9fc376b2012-01-02 04:01:30 +000024#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050025
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050026#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menon987ec582015-03-09 17:12:04 -050027#include <asm/arch/omap.h>
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050028
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050029/* Clock Defines */
30#define V_OSCK 26000000 /* Clock output from T2 */
31#define V_SCLK (V_OSCK >> 1)
32
Nikita Kiryanov9fc376b2012-01-02 04:01:30 +000033#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
34#define CONFIG_SETUP_MEMORY_TAGS
35#define CONFIG_INITRD_TAG
36#define CONFIG_REVISION_TAG
Nikita Kiryanov82309252012-01-12 03:26:30 +000037#define CONFIG_SERIAL_TAG
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050038
39/*
40 * Size of malloc() pool
41 */
Igor Grinberg390cdcd2012-05-24 04:01:21 +000042#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
Nikita Kiryanov9fc376b2012-01-02 04:01:30 +000043 /* Sector */
44#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050045
46/*
47 * Hardware drivers
48 */
49
50/*
51 * NS16550 Configuration
52 */
53#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
54
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050055#define CONFIG_SYS_NS16550_SERIAL
56#define CONFIG_SYS_NS16550_REG_SIZE (-4)
57#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
58
59/*
60 * select serial console configuration
61 */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050062#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050063
64/* allow to overwrite serial and ethaddr */
65#define CONFIG_ENV_OVERWRITE
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050066#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
67 115200}
Nikita Kiryanov9fc376b2012-01-02 04:01:30 +000068
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050069/* USB device configuration */
Nikita Kiryanov9fc376b2012-01-02 04:01:30 +000070#define CONFIG_USB_DEVICE
71#define CONFIG_USB_TTY
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050072
73/* commands to include */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050074
Heiko Schocher6789e842013-10-22 11:03:18 +020075#define CONFIG_SYS_I2C
Nikita Kiryanov82309252012-01-12 03:26:30 +000076#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
77#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Nikita Kiryanov52658fd2014-08-20 15:08:52 +030078#define CONFIG_SYS_I2C_EEPROM_BUS 0
Nikita Kiryanov79874ae2012-04-02 02:29:31 +000079#define CONFIG_I2C_MULTI_BUS
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050080
81/*
82 * TWL4030
83 */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050084
85/*
86 * Board NAND Info.
87 */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050088#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
89 /* to access nand at */
90 /* CS0 */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050091#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
92 /* devices */
Stefan Roese7bb6e292014-03-11 17:04:45 +010093
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050094/* Environment information */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050095#define CONFIG_EXTRA_ENV_SETTINGS \
96 "loadaddr=0x82000000\0" \
97 "usbtty=cdc_acm\0" \
Nikita Kiryanovf3ef3602013-12-11 18:04:40 +020098 "console=ttyO2,115200n8\0" \
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050099 "mpurate=500\0" \
100 "vram=12M\0" \
101 "dvimode=1024x768MR-16@60\0" \
102 "defaultdisplay=dvi\0" \
103 "mmcdev=0\0" \
104 "mmcroot=/dev/mmcblk0p2 rw\0" \
Igor Grinberg0b800a62013-04-22 01:06:55 +0000105 "mmcrootfstype=ext4 rootwait\0" \
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500106 "nandroot=/dev/mtdblock4 rw\0" \
Igor Grinberg0b800a62013-04-22 01:06:55 +0000107 "nandrootfstype=ubifs\0" \
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500108 "mmcargs=setenv bootargs console=${console} " \
109 "mpurate=${mpurate} " \
110 "vram=${vram} " \
111 "omapfb.mode=dvi:${dvimode} " \
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500112 "omapdss.def_disp=${defaultdisplay} " \
113 "root=${mmcroot} " \
114 "rootfstype=${mmcrootfstype}\0" \
115 "nandargs=setenv bootargs console=${console} " \
116 "mpurate=${mpurate} " \
117 "vram=${vram} " \
118 "omapfb.mode=dvi:${dvimode} " \
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500119 "omapdss.def_disp=${defaultdisplay} " \
120 "root=${nandroot} " \
121 "rootfstype=${nandrootfstype}\0" \
122 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
123 "bootscript=echo Running bootscript from mmc ...; " \
124 "source ${loadaddr}\0" \
125 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
126 "mmcboot=echo Booting from mmc ...; " \
127 "run mmcargs; " \
128 "bootm ${loadaddr}\0" \
129 "nandboot=echo Booting from nand ...; " \
130 "run nandargs; " \
Igor Grinberg0b800a62013-04-22 01:06:55 +0000131 "nand read ${loadaddr} 2a0000 400000; " \
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500132 "bootm ${loadaddr}\0" \
133
134#define CONFIG_BOOTCOMMAND \
Andrew Bradford66968112012-10-01 05:06:52 +0000135 "mmc dev ${mmcdev}; if mmc rescan; then " \
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500136 "if run loadbootscript; then " \
137 "run bootscript; " \
138 "else " \
139 "if run loaduimage; then " \
140 "run mmcboot; " \
141 "else run nandboot; " \
142 "fi; " \
143 "fi; " \
144 "else run nandboot; fi"
145
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500146/*
147 * Miscellaneous configurable options
148 */
Igor Grinberg41d7e702011-04-18 17:48:28 -0400149#define CONFIG_TIMESTAMP
Nikita Kiryanov9fc376b2012-01-02 04:01:30 +0000150#define CONFIG_SYS_AUTOLOAD "no"
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500151
152#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
153 /* works on */
154#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
155 0x01F00000) /* 31MB */
156
157#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
158 /* load address */
159
160/*
161 * OMAP3 has 12 GP timers, they can be driven by the system clock
162 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
163 * This rate is divided by a local divisor.
164 */
165#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
166#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500167
168/*-----------------------------------------------------------------------
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500169 * Physical Memory Map
170 */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500171#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500172
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500173/*-----------------------------------------------------------------------
174 * FLASH and environment organization
175 */
176
177/* **** PISMO SUPPORT *** */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500178/* Monitor at start of flash */
179#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Igor Grinberg3530a352012-10-07 01:17:34 +0000180#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500181
Adam Ford7672d9d2017-09-04 21:08:02 -0500182#define CONFIG_ENV_OFFSET 0x260000
183#define CONFIG_ENV_ADDR 0x260000
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500184
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500185/* additions for new relocation code, must be added to all boards */
186#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
187#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
188#define CONFIG_SYS_INIT_RAM_SIZE 0x800
189#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
190 CONFIG_SYS_INIT_RAM_SIZE - \
191 GENERATED_GBL_DATA_SIZE)
192
Igor Grinberg2b8754b2011-04-18 17:54:33 -0400193/* Status LED */
Igor Grinbergebc18af2013-11-06 16:39:47 +0200194#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
Igor Grinberg2b8754b2011-04-18 17:54:33 -0400195
Nikita Kiryanov60e6bdc2013-02-24 06:19:23 +0000196#define CONFIG_SPLASHIMAGE_GUARD
197
Nikita Kiryanov7878ca52013-01-30 21:39:58 +0000198/* Display Configuration */
Nikita Kiryanov7878ca52013-01-30 21:39:58 +0000199#define LCD_BPP LCD_COLOR16
200
Nikita Kiryanovf35034f2012-12-22 21:03:48 +0000201#define CONFIG_SPLASH_SCREEN
Nikita Kiryanovf82eb2f2015-01-14 10:42:54 +0200202#define CONFIG_SPLASH_SOURCE
Nikita Kiryanovf35034f2012-12-22 21:03:48 +0000203#define CONFIG_BMP_16BPP
Nikita Kiryanov63c4f172013-10-16 17:23:29 +0300204#define CONFIG_SCF0403_LCD
205
Stefan Roese3e51b7c2013-12-04 13:54:18 +0100206/* Defines for SPL */
Stefan Roese3e51b7c2013-12-04 13:54:18 +0100207
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +0100208#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200209#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Stefan Roese3e51b7c2013-12-04 13:54:18 +0100210
Stefan Roese3e51b7c2013-12-04 13:54:18 +0100211#define CONFIG_SPL_NAND_BASE
212#define CONFIG_SPL_NAND_DRIVERS
213#define CONFIG_SPL_NAND_ECC
Stefan Roese3e51b7c2013-12-04 13:54:18 +0100214
215/* NAND boot config */
216#define CONFIG_SYS_NAND_5_ADDR_CYCLE
217#define CONFIG_SYS_NAND_PAGE_COUNT 64
218#define CONFIG_SYS_NAND_PAGE_SIZE 2048
219#define CONFIG_SYS_NAND_OOBSIZE 64
220#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
221#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
222/*
223 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
224 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
225 */
226#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
227 10, 11, 12 }
228#define CONFIG_SYS_NAND_ECCSIZE 512
229#define CONFIG_SYS_NAND_ECCBYTES 3
230#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
231
232#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
233#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
234
235#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rinifa2f81b2016-08-26 13:30:43 -0400236#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
237 CONFIG_SPL_TEXT_BASE)
Stefan Roese3e51b7c2013-12-04 13:54:18 +0100238
239/*
240 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
241 * older x-loader implementations. And move the BSS area so that it
242 * doesn't overlap with TEXT_BASE.
243 */
Stefan Roese3e51b7c2013-12-04 13:54:18 +0100244#define CONFIG_SPL_BSS_START_ADDR 0x80100000
245#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
246
247#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
248#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
249
Nikita Kiryanovbcb447e2016-04-16 17:55:09 +0300250/* EEPROM */
Nikita Kiryanovbcb447e2016-04-16 17:55:09 +0300251#define CONFIG_ENV_EEPROM_IS_ON_I2C
252#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
253#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
254#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
255#define CONFIG_SYS_EEPROM_SIZE 256
256
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500257#endif /* __CONFIG_H */