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Heiko Schocherf5e0d032006-06-19 11:02:41 +02001/*
2 * ppmc7xx.h
3 * ---------
Wolfgang Denkb87dfd22006-07-19 13:50:38 +02004 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +02005 * Wind River PPMC 7xx/74xx board configuration file.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +02006 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +02007 * By Richard Danter (richard.danter@windriver.com)
8 * Copyright (C) 2005 Wind River Systems
9 */
10
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_PPMC7XX
16
17
18/*===================================================================
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020019 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020020 * User configurable settings - Modify to your preference
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020021 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020022 *===================================================================
23 */
24
25/*
26 * Debug
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020027 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020028 * DEBUG - Define this is you want extra debug info
29 * GTREGREAD - Required to build with debug
30 * do_bdinfo - Required to build with debug
Heiko Schocherf5e0d032006-06-19 11:02:41 +020031 */
32
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020033#ifdef DEBUG
34#define GTREGREAD(x) 0xFFFFFFFF
Heiko Schocherf5e0d032006-06-19 11:02:41 +020035#define do_bdinfo(a,b,c,d)
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020036#endif
Heiko Schocherf5e0d032006-06-19 11:02:41 +020037
38/*
39 * CPU type
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020040 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020041 * CONFIG_7xx - We have a 750 or 755 CPU
42 * CONFIG_74xx - We have a 7400 CPU
43 * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
44 * CONFIG_BUS_CLK - System bus clock in Hz
Heiko Schocherf5e0d032006-06-19 11:02:41 +020045 */
46
47#define CONFIG_7xx
48#undef CONFIG_74xx
49#undef CONFIG_ALTIVEC
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020050#define CONFIG_BUS_CLK 66000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +020051
Wolfgang Denk2ae18242010-10-06 09:05:45 +020052#define CONFIG_SYS_TEXT_BASE 0xFFF00000
Heiko Schocherf5e0d032006-06-19 11:02:41 +020053
Marek Vasut0aa27652011-10-21 14:17:33 +000054#ifndef __ASSEMBLY__
55#include <galileo/core.h>
56#endif
57
Heiko Schocherf5e0d032006-06-19 11:02:41 +020058/*
59 * Monitor configuration
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020060 *
Jon Loeliger26a34562007-07-04 22:33:17 -050061 * List of command sets to include in shell
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020062 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020063 * The following command sets have been tested and known to work:
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020064 *
Jon Loeliger26a34562007-07-04 22:33:17 -050065 * CMD_CACHE - Cache control commands
66 * CMD_MEMORY - Memory display, change and test commands
67 * CMD_FLASH - Erase and program flash
68 * CMD_ENV - Environment commands
69 * CMD_RUN - Run commands stored in env vars
70 * CMD_ELF - Load ELF files
71 * CMD_NET - Networking/file download commands
72 * CMD_PIN - ICMP Echo Request command
73 * CMD_PCI - PCI Bus scanning command
Heiko Schocherf5e0d032006-06-19 11:02:41 +020074 */
75
Jon Loeliger26a34562007-07-04 22:33:17 -050076/*
Jon Loeliger079a1362007-07-10 10:12:10 -050077 * BOOTP options
78 */
79#define CONFIG_BOOTP_BOOTFILESIZE
80#define CONFIG_BOOTP_BOOTPATH
81#define CONFIG_BOOTP_GATEWAY
82#define CONFIG_BOOTP_HOSTNAME
83
84
85/*
Jon Loeliger26a34562007-07-04 22:33:17 -050086 * Command line configuration.
87 */
88#include <config_cmd_default.h>
89
90#define CONFIG_CMD_FLASH
Mike Frysingerbdab39d2009-01-28 19:08:14 -050091#define CONFIG_CMD_SAVEENV
Jon Loeliger26a34562007-07-04 22:33:17 -050092#define CONFIG_CMD_RUN
93#define CONFIG_CMD_ELF
94#define CONFIG_CMD_NET
95#define CONFIG_CMD_PING
96#define CONFIG_CMD_PCI
97
98#undef CONFIG_CMD_KGDB
Heiko Schocherf5e0d032006-06-19 11:02:41 +020099
100
101/*
102 * Serial configuration
103 *
104 * CONFIG_CONS_INDEX - Serial console port number (COM1)
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200105 * CONFIG_BAUDRATE - Serial speed
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200106 */
107
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200108#define CONFIG_CONS_INDEX 1
109#define CONFIG_BAUDRATE 9600
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200110
111
112/*
113 * PCI config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200114 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200115 * CONFIG_PCI - Enable PCI bus
116 * CONFIG_PCI_PNP - Enable Plug & Play support
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200117 * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
118 */
119
120#define CONFIG_PCI
121#define CONFIG_PCI_PNP
122#undef CONFIG_PCI_SCAN_SHOW
123
124
125/*
126 * Network config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200127 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200128 * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
129 * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200130 */
131
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200132#define CONFIG_EEPRO100
133#define CONFIG_EEPRO100_SROM_WRITE
134
135
136/*
137 * Enable extra init functions
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200138 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200139 * CONFIG_MISC_INIT_F - Call pre-relocation init functions
140 * CONFIG_MISC_INIT_R - Call post relocation init functions
141 */
142
143#undef CONFIG_MISC_INIT_F
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200144#define CONFIG_MISC_INIT_R
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200145
146
147/*
148 * Boot config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200149 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200150 * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200151 * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200152 */
153
154#define CONFIG_BOOTCOMMAND \
155 "bootp;" \
156 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
157 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
158 "bootm"
159#define CONFIG_BOOTDELAY 5
160
161
162/*===================================================================
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200163 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200164 * Board configuration settings - You should not need to modify these
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200165 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200166 *===================================================================
167 */
168
169
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200170/*
171 * Memory map
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200172 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200173 * This board runs in a standard CHRP (Map-B) configuration.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200174 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200175 * Type Start End Size Width Chip Sel
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200176 * ----------- ----------- ----------- ------- ------- --------
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200177 * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
178 * User LED's 0x78000000 RCS3
179 * UART 0x7C000000 RCS2
180 * Mailbox 0xFF000000 RCS1
181 * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200182 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200183 * Flash sectors are laid out as follows.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200184 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200185 * Sector Start End Size Comments
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200186 * ------- ----------- ----------- ------- -----------
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200187 * 0 0xFFC00000 0xFFC3FFFF 256KB
188 * 1 0xFFC40000 0xFFC7FFFF 256KB
189 * 2 0xFFC80000 0xFFCBFFFF 256KB
190 * 3 0xFFCC0000 0xFFCFFFFF 256KB
191 * 4 0xFFD00000 0xFFD3FFFF 256KB
192 * 5 0xFFD40000 0xFFD7FFFF 256KB
193 * 6 0xFFD80000 0xFFDBFFFF 256KB
194 * 7 0xFFDC0000 0xFFDFFFFF 256KB
195 * 8 0xFFE00000 0xFFE3FFFF 256KB
196 * 9 0xFFE40000 0xFFE7FFFF 256KB
197 * 10 0xFFE80000 0xFFEBFFFF 256KB
198 * 11 0xFFEC0000 0xFFEFFFFF 256KB
199 * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
200 * 13 0xFFF40000 0xFFF7FFFF 256KB
201 * 14 0xFFF80000 0xFFFBFFFF 256KB
202 * 15 0xFFFC0000 0xFFFDFFFF 128KB
203 * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
204 * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
205 * 18 0xFFFF0000 0xFFFFFFFF 64KB
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200206 */
207
208
209/*
210 * SDRAM config - see memory map details above.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200211 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 * CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
213 * CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200214 */
215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_SDRAM_BASE 0x00000000
217#define CONFIG_SYS_SDRAM_SIZE 0x04000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200218
219
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200220/*
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200221 * Flash config - see memory map details above.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200222 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 * CONFIG_SYS_FLASH_BASE - Start address of flash memory
224 * CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem
225 * CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms
226 * CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms
227 * CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board
228 * CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200229 */
230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_BASE 0xFFC00000
232#define CONFIG_SYS_FLASH_SIZE 0x00400000
233#define CONFIG_SYS_FLASH_ERASE_TOUT 250000
234#define CONFIG_SYS_FLASH_WRITE_TOUT 5000
235#define CONFIG_SYS_MAX_FLASH_BANKS 1
236#define CONFIG_SYS_MAX_FLASH_SECT 19
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200237
238
239/*
240 * Monitor config - see memory map details above
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200241 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 * CONFIG_SYS_MONITOR_BASE - Base address of monitor code
243 * CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200244 */
245
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200246#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_MALLOC_LEN 0x20000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200248
249
250/*
251 * Command shell settings
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200252 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253 * CONFIG_SYS_BARGSIZE - Boot Argument buffer size
254 * CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
255 * CONFIG_SYS_CBSIZE - Console Buffer (input) size
256 * CONFIG_SYS_LOAD_ADDR - Default load address
257 * CONFIG_SYS_LONGHELP - Provide more detailed help
258 * CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands
259 * CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM
260 * CONFIG_SYS_MEMTEST_END - End address of RAM test
261 * CONFIG_SYS_PBSIZE - Print Buffer (output) size
262 * CONFIG_SYS_PROMPT - Prompt string
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200263 */
264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_BARGSIZE 1024
266#define CONFIG_SYS_BOOTMAPSZ 0x800000
267#define CONFIG_SYS_CBSIZE 1024
268#define CONFIG_SYS_LOAD_ADDR 0x100000
269#define CONFIG_SYS_LONGHELP
270#define CONFIG_SYS_MAXARGS 16
271#define CONFIG_SYS_MEMTEST_START 0x00040000
272#define CONFIG_SYS_MEMTEST_END 0x00040100
273#define CONFIG_SYS_PBSIZE 1024
274#define CONFIG_SYS_PROMPT "=> "
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200275
276
277/*
278 * Environment config - see memory map details above
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200279 *
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200280 * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200281 * CONFIG_ENV_ADDR - Address of the sector containing env vars
282 * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
283 * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200284 */
285
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200286#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200287#define CONFIG_ENV_ADDR 0xFFFE0000
288#define CONFIG_ENV_SIZE 0x1000
289#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000
290#define CONFIG_ENV_SIZE_REDUND 0x1000
291#define CONFIG_ENV_SECT_SIZE 0x8000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200292
293
294/*
295 * Initial RAM config
296 *
297 * Since the main system RAM is initialised very early, we place the INIT_RAM
298 * in the main system RAM just above the exception vectors. The contents are
299 * copied to top of RAM by the init code.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200300 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301 * CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect
Wolfgang Denk553f0982010-10-26 13:32:32 +0200302 * CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200303 * GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304 * CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200305 */
306
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200308#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200309#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200310
311
312/*
313 * Initial BAT config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200314 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200315 * BAT0 - System SDRAM
316 * BAT1 - LED's and Serial Port
317 * BAT2 - PCI Memory
318 * BAT3 - PCI I/O including Flash Memory
319 */
320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
322#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
323#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
324#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
327#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
328#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
329#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
332#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
333#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
334#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
337#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
338#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
339#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200340
341
342/*
343 * Cache config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200344 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345 * CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific)
346 * CONFIG_SYS_L2 - L2 cache enabled if defined
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200347 * L2_INIT - L2 cache init flags
348 * L2_ENABLE - L2 cache enable flags
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200349 */
350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_CACHELINE_SIZE 32
352#undef CONFIG_SYS_L2
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200353#define L2_INIT 0
354#define L2_ENABLE 0
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200355
356
357/*
358 * Clocks config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200359 *
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200360 * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361 * CONFIG_SYS_HZ - Decrementer freq in Hz
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200362 */
363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK
365#define CONFIG_SYS_HZ 1000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200366
367
368/*
369 * Serial port config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200370 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371 * CONFIG_SYS_BAUDRATE_TABLE - List of valid baud rates
372 * CONFIG_SYS_NS16550 - Include the NS16550 driver
373 * CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver
374 * CONFIG_SYS_NS16550_CLK - Frequency of reference clock
375 * CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
376 * CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200377 */
378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
380#define CONFIG_SYS_NS16550
381#define CONFIG_SYS_NS16550_SERIAL
382#define CONFIG_SYS_NS16550_CLK 3686400
383#define CONFIG_SYS_NS16550_REG_SIZE -8
384#define CONFIG_SYS_NS16550_COM1 0x7C000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200385
386
387/*
388 * PCI Config - Address Map B (CHRP)
389 */
390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
392#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
393#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
394#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
395#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
396#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000
397#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
398#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000
399#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
400#define CONFIG_SYS_PCI_IO_BUS 0x00800000
401#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000
402#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
403#define CONFIG_SYS_ISA_IO_BUS 0x00000000
404#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000
405#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
406#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
407#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
408#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200409
410
411/*
412 * Extra init functions
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200413 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414 * CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200415 */
416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_BOARD_ASM_INIT
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200418
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200419#endif /* __CONFIG_H */