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wdenk384cc682005-04-03 22:35:21 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * pm854 board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
38#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41#define CONFIG_MPC8540 1 /* MPC8540 specific */
42#define CONFIG_PM854 1 /* PM854 board specific */
43
44#define CONFIG_PCI
45#define CONFIG_TSEC_ENET /* tsec ethernet support */
46#define CONFIG_ENV_OVERWRITE
Jon Loeligerd9b94f22005-07-25 14:05:07 -050047
Kumar Gala45f21662008-01-16 09:06:48 -060048#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk384cc682005-04-03 22:35:21 +000049
50/*
51 * sysclk for MPC85xx
52 *
53 * Two valid values are:
54 * 33000000
55 * 66000000
56 *
57 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
58 * is likely the desired value here, so that is now the default.
59 * The board, however, can run at 66MHz. In any event, this value
60 * must match the settings of some switches. Details can be found
61 * in the README.mpc85xxads.
62 */
63
64#ifndef CONFIG_SYS_CLK_FREQ
65#define CONFIG_SYS_CLK_FREQ 66000000
66#endif
67
68
69/*
70 * These can be toggled for performance analysis, otherwise use default.
71 */
72#define CONFIG_L2_CACHE /* toggle L2 cache */
73#define CONFIG_BTB /* toggle branch predition */
wdenk384cc682005-04-03 22:35:21 +000074
75#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
76
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
78#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
79#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk384cc682005-04-03 22:35:21 +000080
81
82/*
83 * Base addresses -- Note these are effective addresses where the
84 * actual resources get mapped (not physical addresses)
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
87#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
88#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
89#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk384cc682005-04-03 22:35:21 +000090
91
Kumar Galad53bd3e2008-08-26 23:51:49 -050092/* DDR Setup */
93#define CONFIG_FSL_DDR1
94#undef CONFIG_FSL_DDR_INTERACTIVE
95#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
96#undef CONFIG_DDR_SPD
97#define CONFIG_DDR_DLL /* possible DLL fix needed */
98#define CONFIG_DDR_ECC /* only for ECC DDR module */
99
100#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Galad53bd3e2008-08-26 23:51:49 -0500104#define CONFIG_VERY_BIG_RAM
wdenk384cc682005-04-03 22:35:21 +0000105
Kumar Galad53bd3e2008-08-26 23:51:49 -0500106#define CONFIG_NUM_DDR_CONTROLLERS 1
107#define CONFIG_DIMM_SLOTS_PER_CTLR 1
108#define CONFIG_CHIP_SELECTS_PER_CTRL 2
wdenk384cc682005-04-03 22:35:21 +0000109
Kumar Galad53bd3e2008-08-26 23:51:49 -0500110/* I2C addresses of SPD EEPROMs */
111#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */
wdenk384cc682005-04-03 22:35:21 +0000112
Kumar Galad53bd3e2008-08-26 23:51:49 -0500113/* Manually set up DDR parameters */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */
115#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
116#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
117#define CONFIG_SYS_DDR_TIMING_1 0x47444321
118#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
119#define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
120#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
121#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
wdenk384cc682005-04-03 22:35:21 +0000122
123/*
124 * SDRAM on the Local Bus
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
127#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
wdenk384cc682005-04-03 22:35:21 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */
130#define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */
wdenk384cc682005-04-03 22:35:21 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */
133#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
134#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
135#undef CONFIG_SYS_FLASH_CHECKSUM
136#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
137#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk384cc682005-04-03 22:35:21 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenk384cc682005-04-03 22:35:21 +0000140
141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
143#define CONFIG_SYS_RAMBOOT
wdenk384cc682005-04-03 22:35:21 +0000144#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#undef CONFIG_SYS_RAMBOOT
wdenk384cc682005-04-03 22:35:21 +0000146#endif
147
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200148#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_CFI
150#define CONFIG_SYS_FLASH_EMPTY_INFO
Wolfgang Denk992b4022005-08-05 11:47:10 +0200151
152#undef CONFIG_CLOCKS_IN_MHZ
153
wdenk384cc682005-04-03 22:35:21 +0000154/*
155 * Local Bus Definitions
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
158#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
159#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
160#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk8b0bfc62005-04-03 23:11:38 +0000161
wdenk384cc682005-04-03 22:35:21 +0000162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_INIT_RAM_LOCK 1
164#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
165#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk384cc682005-04-03 22:35:21 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
168#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
169#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk384cc682005-04-03 22:35:21 +0000170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
172#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk384cc682005-04-03 22:35:21 +0000173
174/* Serial Port */
175#define CONFIG_CONS_INDEX 1
176#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_NS16550
178#define CONFIG_SYS_NS16550_SERIAL
179#define CONFIG_SYS_NS16550_REG_SIZE 1
180#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk384cc682005-04-03 22:35:21 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk384cc682005-04-03 22:35:21 +0000183 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
186#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk384cc682005-04-03 22:35:21 +0000187
188/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_HUSH_PARSER
190#ifdef CONFIG_SYS_HUSH_PARSER
191#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk384cc682005-04-03 22:35:21 +0000192#endif
193
Jon Loeliger20476722006-10-20 15:50:15 -0500194/*
195 * I2C
196 */
197#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
198#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk384cc682005-04-03 22:35:21 +0000199#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
201#define CONFIG_SYS_I2C_SLAVE 0x7F
202#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
203#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk384cc682005-04-03 22:35:21 +0000204
205/*
206 * EEPROM configuration
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
209#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
210#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
211#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenk384cc682005-04-03 22:35:21 +0000212
213/*
214 * RTC configuration
215 */
216#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk384cc682005-04-03 22:35:21 +0000218
219/* RapidIO MMU */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
221#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
222#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk384cc682005-04-03 22:35:21 +0000223
224/*
225 * General PCI
226 * Addresses are mapped 1-1.
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
229#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
230#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
231#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
232#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
233#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
wdenk384cc682005-04-03 22:35:21 +0000234
235#if defined(CONFIG_PCI)
236
237#define CONFIG_NET_MULTI
238#define CONFIG_PCI_PNP /* do pci plug-and-play */
239
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200240#define CONFIG_EEPRO100
Wolfgang Denk29fe1c02005-09-21 09:59:55 +0200241#define CONFIG_E1000
242#undef CONFIG_TULIP
wdenk384cc682005-04-03 22:35:21 +0000243
244#if !defined(CONFIG_PCI_PNP)
245 #define PCI_ENET0_IOADDR 0xe0000000
246 #define PCI_ENET0_MEMADDR 0xe0000000
247 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
248#endif
249
250#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk384cc682005-04-03 22:35:21 +0000252
253#endif /* CONFIG_PCI */
254
255
256#if defined(CONFIG_TSEC_ENET)
257
258#ifndef CONFIG_NET_MULTI
259#define CONFIG_NET_MULTI 1
260#endif
261
262#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500263#define CONFIG_TSEC1 1
264#define CONFIG_TSEC1_NAME "TSEC0"
265#define CONFIG_TSEC2 1
266#define CONFIG_TSEC2_NAME "TSEC1"
Wolfgang Denk992b4022005-08-05 11:47:10 +0200267#define TSEC1_PHY_ADDR 0
268#define TSEC2_PHY_ADDR 1
wdenk384cc682005-04-03 22:35:21 +0000269#define TSEC1_PHYIDX 0
270#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500271#define TSEC1_FLAGS TSEC_GIGABIT
272#define TSEC2_FLAGS TSEC_GIGABIT
wdenk384cc682005-04-03 22:35:21 +0000273
274#define CONFIG_MPC85XX_FEC 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500275#define CONFIG_MPC85XX_FEC_NAME "FEC"
Wolfgang Denk992b4022005-08-05 11:47:10 +0200276#define FEC_PHY_ADDR 3
wdenk384cc682005-04-03 22:35:21 +0000277#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500278#define FEC_FLAGS 0
wdenk384cc682005-04-03 22:35:21 +0000279
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500280/* Options are: TSEC[0-1] */
281#define CONFIG_ETHPRIME "TSEC0"
wdenk384cc682005-04-03 22:35:21 +0000282
Andy Fleming10327dc2007-08-16 16:35:02 -0500283#define CONFIG_HAS_ETH0
wdenk384cc682005-04-03 22:35:21 +0000284#define CONFIG_HAS_ETH1 1
285#define CONFIG_HAS_ETH2 1
286
287#endif /* CONFIG_TSEC_ENET */
288
289
290/*
291 * Environment
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200294 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200296 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
297 #define CONFIG_ENV_SIZE 0x2000
wdenk384cc682005-04-03 22:35:21 +0000298#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200300 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200302 #define CONFIG_ENV_SIZE 0x2000
wdenk384cc682005-04-03 22:35:21 +0000303#endif
304
305#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk384cc682005-04-03 22:35:21 +0000307
Jon Loeliger2835e512007-06-13 13:22:08 -0500308
309/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500310 * BOOTP options
311 */
312#define CONFIG_BOOTP_BOOTFILESIZE
313#define CONFIG_BOOTP_BOOTPATH
314#define CONFIG_BOOTP_GATEWAY
315#define CONFIG_BOOTP_HOSTNAME
316
317
318/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500319 * Command line configuration.
320 */
321#include <config_cmd_default.h>
322
323#define CONFIG_CMD_PING
324#define CONFIG_CMD_I2C
325#define CONFIG_CMD_MII
326#define CONFIG_CMD_DATE
327#define CONFIG_CMD_EEPROM
328
329#if defined(CONFIG_PCI)
330 #define CONFIG_CMD_PCI
wdenk384cc682005-04-03 22:35:21 +0000331#endif
332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger2835e512007-06-13 13:22:08 -0500334 #undef CONFIG_CMD_ENV
335 #undef CONFIG_CMD_LOADS
336#endif
337
wdenk384cc682005-04-03 22:35:21 +0000338
339#undef CONFIG_WATCHDOG /* watchdog disabled */
340
341/*
342 * Miscellaneous configurable options
343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_LONGHELP /* undef to save memory */
345#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
346#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk384cc682005-04-03 22:35:21 +0000347
Jon Loeliger2835e512007-06-13 13:22:08 -0500348#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk384cc682005-04-03 22:35:21 +0000350#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk384cc682005-04-03 22:35:21 +0000352#endif
353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
355#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
356#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
357#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk384cc682005-04-03 22:35:21 +0000358#define CONFIG_LOOPW
359
360/*
361 * For booting Linux, the board info and command line data
362 * have to be in the first 8 MB of memory, since this is
363 * the maximum mapped by the Linux kernel during initialization.
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
wdenk384cc682005-04-03 22:35:21 +0000366
wdenk384cc682005-04-03 22:35:21 +0000367/*
368 * Internal Definitions
369 *
370 * Boot Flags
371 */
372#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
373#define BOOTFLAG_WARM 0x02 /* Software reboot */
374
Jon Loeliger2835e512007-06-13 13:22:08 -0500375#if defined(CONFIG_CMD_KGDB)
wdenk384cc682005-04-03 22:35:21 +0000376#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
377#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
378#endif
379
380
381/*
382 * Environment Configuration
383 */
384
385/* The mac addresses for all ethernet interface */
386#if defined(CONFIG_TSEC_ENET)
387#define CONFIG_ETHADDR 00:40:42:01:00:00
388#define CONFIG_ETH1ADDR 00:40:42:01:00:01
389#define CONFIG_ETH2ADDR 00:40:42:01:00:02
390#endif
391
Wolfgang Denk992b4022005-08-05 11:47:10 +0200392
393#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
394#define CONFIG_BOOTFILE pm854/uImage
395
396#define CONFIG_HOSTNAME pm854
wdenk384cc682005-04-03 22:35:21 +0000397#define CONFIG_IPADDR 192.168.0.103
Wolfgang Denk992b4022005-08-05 11:47:10 +0200398#define CONFIG_SERVERIP 192.168.0.64
wdenk384cc682005-04-03 22:35:21 +0000399#define CONFIG_GATEWAYIP 192.168.0.1
400#define CONFIG_NETMASK 255.255.255.0
401
402#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
403
404#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
405#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
406
407#define CONFIG_BAUDRATE 9600
408
409#define CONFIG_EXTRA_ENV_SETTINGS \
410 "netdev=eth0\0" \
411 "consoledev=ttyS0\0" \
412 "ramdiskaddr=400000\0" \
Wolfgang Denk992b4022005-08-05 11:47:10 +0200413 "ramdiskfile=pm854/uRamdisk\0"
wdenk384cc682005-04-03 22:35:21 +0000414
415#define CONFIG_NFSBOOTCOMMAND \
416 "setenv bootargs root=/dev/nfs rw " \
417 "nfsroot=$serverip:$rootpath " \
418 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
419 "console=$consoledev,$baudrate $othbootargs;" \
420 "tftp $loadaddr $bootfile;" \
421 "bootm $loadaddr"
422
423#define CONFIG_RAMBOOTCOMMAND \
424 "setenv bootargs root=/dev/ram rw " \
425 "console=$consoledev,$baudrate $othbootargs;" \
426 "tftp $ramdiskaddr $ramdiskfile;" \
427 "tftp $loadaddr $bootfile;" \
428 "bootm $loadaddr $ramdiskaddr"
429
430#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
431
432#endif /* __CONFIG_H */