Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * ISEE 2007 SL, <www.iseebcn.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | #include <common.h> |
| 24 | #include <netdev.h> |
| 25 | #include <twl4030.h> |
| 26 | #include <asm/io.h> |
Sanjeev Premi | 84c3b63 | 2011-09-08 10:51:01 -0400 | [diff] [blame] | 27 | #include <asm/gpio.h> |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 28 | #include <asm/arch/mem.h> |
Enric Balletbo i Serra | f49d7b6 | 2010-11-04 15:34:33 -0400 | [diff] [blame] | 29 | #include <asm/arch/mmc_host_def.h> |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 30 | #include <asm/arch/mux.h> |
| 31 | #include <asm/arch/sys_proto.h> |
Philip Balister | 5213d24 | 2011-09-14 13:32:22 -0400 | [diff] [blame] | 32 | #include <asm/arch/omap_gpmc.h> |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 33 | #include <asm/mach-types.h> |
| 34 | #include "igep0020.h" |
| 35 | |
John Rigby | 2956532 | 2010-12-20 18:27:51 -0700 | [diff] [blame] | 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 38 | /* GPMC definitions for LAN9221 chips */ |
| 39 | static const u32 gpmc_lan_config[] = { |
| 40 | NET_LAN9221_GPMC_CONFIG1, |
| 41 | NET_LAN9221_GPMC_CONFIG2, |
| 42 | NET_LAN9221_GPMC_CONFIG3, |
| 43 | NET_LAN9221_GPMC_CONFIG4, |
| 44 | NET_LAN9221_GPMC_CONFIG5, |
| 45 | NET_LAN9221_GPMC_CONFIG6, |
| 46 | }; |
| 47 | |
| 48 | /* |
| 49 | * Routine: board_init |
| 50 | * Description: Early hardware init. |
| 51 | */ |
| 52 | int board_init(void) |
| 53 | { |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 54 | gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 55 | /* boot param addr */ |
| 56 | gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
| 57 | |
| 58 | return 0; |
| 59 | } |
| 60 | |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 61 | #ifdef CONFIG_SPL_BUILD |
| 62 | /* |
| 63 | * Routine: omap_rev_string |
| 64 | * Description: For SPL builds output board rev |
| 65 | */ |
| 66 | void omap_rev_string(void) |
| 67 | { |
| 68 | } |
| 69 | |
| 70 | /* |
| 71 | * Routine: get_board_mem_timings |
| 72 | * Description: If we use SPL then there is no x-loader nor config header |
| 73 | * so we have to setup the DDR timings ourself on both banks. |
| 74 | */ |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame^] | 75 | void get_board_mem_timings(struct board_sdrc_timings *timings) |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 76 | { |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame^] | 77 | timings->mr = MICRON_V_MR_165; |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 78 | #ifdef CONFIG_BOOT_NAND |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame^] | 79 | timings->mcfg = MICRON_V_MCFG_200(256 << 20); |
| 80 | timings->ctrla = MICRON_V_ACTIMA_200; |
| 81 | timings->ctrlb = MICRON_V_ACTIMB_200; |
| 82 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 83 | #else |
| 84 | if (get_cpu_family() == CPU_OMAP34XX) { |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame^] | 85 | timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); |
| 86 | timings->ctrla = NUMONYX_V_ACTIMA_165; |
| 87 | timings->ctrlb = NUMONYX_V_ACTIMB_165; |
| 88 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 89 | |
| 90 | } else { |
Peter Barada | 8c4445d | 2012-11-13 07:40:28 +0000 | [diff] [blame^] | 91 | timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); |
| 92 | timings->ctrla = NUMONYX_V_ACTIMA_200; |
| 93 | timings->ctrlb = NUMONYX_V_ACTIMB_200; |
| 94 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 95 | } |
| 96 | #endif |
| 97 | } |
| 98 | #endif |
| 99 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 100 | /* |
| 101 | * Routine: setup_net_chip |
| 102 | * Description: Setting up the configuration GPMC registers specific to the |
| 103 | * Ethernet hardware. |
| 104 | */ |
| 105 | #if defined(CONFIG_CMD_NET) |
| 106 | static void setup_net_chip(void) |
| 107 | { |
| 108 | struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
| 109 | |
| 110 | enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, |
| 111 | GPMC_SIZE_16M); |
| 112 | |
| 113 | /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ |
| 114 | writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
| 115 | /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ |
| 116 | writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); |
| 117 | /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ |
| 118 | writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, |
| 119 | &ctrl_base->gpmc_nadv_ale); |
| 120 | |
| 121 | /* Make GPIO 64 as output pin and send a magic pulse through it */ |
Sanjeev Premi | 84c3b63 | 2011-09-08 10:51:01 -0400 | [diff] [blame] | 122 | if (!gpio_request(64, "")) { |
| 123 | gpio_direction_output(64, 0); |
| 124 | gpio_set_value(64, 1); |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 125 | udelay(1); |
Sanjeev Premi | 84c3b63 | 2011-09-08 10:51:01 -0400 | [diff] [blame] | 126 | gpio_set_value(64, 0); |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 127 | udelay(1); |
Sanjeev Premi | 84c3b63 | 2011-09-08 10:51:01 -0400 | [diff] [blame] | 128 | gpio_set_value(64, 1); |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 129 | } |
| 130 | } |
| 131 | #endif |
| 132 | |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 133 | #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) |
Enric Balletbo i Serra | f49d7b6 | 2010-11-04 15:34:33 -0400 | [diff] [blame] | 134 | int board_mmc_init(bd_t *bis) |
| 135 | { |
Jonathan Solnit | bbbc1ae | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 136 | omap_mmc_init(0, 0, 0); |
Enric Balletbo i Serra | f49d7b6 | 2010-11-04 15:34:33 -0400 | [diff] [blame] | 137 | return 0; |
| 138 | } |
| 139 | #endif |
| 140 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 141 | /* |
| 142 | * Routine: misc_init_r |
| 143 | * Description: Configure board specific parts |
| 144 | */ |
| 145 | int misc_init_r(void) |
| 146 | { |
| 147 | twl4030_power_init(); |
| 148 | |
| 149 | #if defined(CONFIG_CMD_NET) |
| 150 | setup_net_chip(); |
| 151 | #endif |
| 152 | |
| 153 | dieid_num_r(); |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
| 158 | /* |
| 159 | * Routine: set_muxconf_regs |
| 160 | * Description: Setting up the configuration Mux registers specific to the |
| 161 | * hardware. Many pins need to be moved from protect to primary |
| 162 | * mode. |
| 163 | */ |
| 164 | void set_muxconf_regs(void) |
| 165 | { |
| 166 | MUX_DEFAULT(); |
| 167 | } |
| 168 | |
| 169 | int board_eth_init(bd_t *bis) |
| 170 | { |
| 171 | int rc = 0; |
| 172 | #ifdef CONFIG_SMC911X |
| 173 | rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
| 174 | #endif |
| 175 | return rc; |
| 176 | } |