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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* sdram_init.c - automatic memory sizing */
25
26#include <common.h>
27#include <74xx_7xx.h>
28#include <galileo/memory.h>
29#include <galileo/pci.h>
30#include <galileo/gt64260R.h>
31#include <net.h>
32
33#include "eth.h"
34#include "mpsc.h"
35#include "i2c.h"
36#include "64260.h"
37
38/* #define DEBUG */
39#define MAP_PCI
40
41#ifdef DEBUG
42#define DP(x) x
43#else
44#define DP(x)
45#endif
46
47#define GB (1 << 30)
48
49/* structure to store the relevant information about an sdram bank */
50typedef struct sdram_info {
51 uchar drb_size;
52 uchar registered, ecc;
53 uchar tpar;
54 uchar tras_clocks;
55 uchar burst_len;
56 uchar banks, slot;
wdenkbf9e3b32004-02-12 00:47:09 +000057 int size; /* detected size, not from I2C but from dram_size() */
wdenkc6097192002-11-03 00:24:07 +000058} sdram_info_t;
59
60#ifdef DEBUG
wdenkbf9e3b32004-02-12 00:47:09 +000061void dump_dimm_info (struct sdram_info *d)
wdenkc6097192002-11-03 00:24:07 +000062{
wdenkbf9e3b32004-02-12 00:47:09 +000063 static const char *ecc_legend[] = { "", " Parity", " ECC" };
64
65 printf ("dimm%s %sDRAM: %dMibytes:\n",
66 ecc_legend[d->ecc],
67 d->registered ? "R" : "", (d->size >> 20));
68 printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
69 d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
70 d->banks, d->slot);
wdenkc6097192002-11-03 00:24:07 +000071}
72#endif
73
74static int
wdenkbf9e3b32004-02-12 00:47:09 +000075memory_map_bank (unsigned int bankNo,
76 unsigned int bankBase, unsigned int bankLength)
wdenkc6097192002-11-03 00:24:07 +000077{
78#ifdef DEBUG
79 if (bankLength > 0) {
wdenkbf9e3b32004-02-12 00:47:09 +000080 printf ("mapping bank %d at %08x - %08x\n",
81 bankNo, bankBase, bankBase + bankLength - 1);
wdenkc6097192002-11-03 00:24:07 +000082 } else {
wdenkbf9e3b32004-02-12 00:47:09 +000083 printf ("unmapping bank %d\n", bankNo);
wdenkc6097192002-11-03 00:24:07 +000084 }
85#endif
86
wdenkbf9e3b32004-02-12 00:47:09 +000087 memoryMapBank (bankNo, bankBase, bankLength);
wdenkc6097192002-11-03 00:24:07 +000088
89 return 0;
90}
91
92#ifdef MAP_PCI
93static int
wdenkbf9e3b32004-02-12 00:47:09 +000094memory_map_bank_pci (unsigned int bankNo,
95 unsigned int bankBase, unsigned int bankLength)
wdenkc6097192002-11-03 00:24:07 +000096{
97 PCI_HOST host;
wdenkbf9e3b32004-02-12 00:47:09 +000098
99 for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
100 const int features =
wdenkc6097192002-11-03 00:24:07 +0000101 PREFETCH_ENABLE |
102 DELAYED_READ_ENABLE |
103 AGGRESSIVE_PREFETCH |
104 READ_LINE_AGGRESSIVE_PREFETCH |
105 READ_MULTI_AGGRESSIVE_PREFETCH |
wdenkbf9e3b32004-02-12 00:47:09 +0000106 MAX_BURST_4 | PCI_NO_SWAP;
wdenkc6097192002-11-03 00:24:07 +0000107
wdenkbf9e3b32004-02-12 00:47:09 +0000108 pciMapMemoryBank (host, bankNo, bankBase, bankLength);
wdenkc6097192002-11-03 00:24:07 +0000109
wdenkbf9e3b32004-02-12 00:47:09 +0000110 pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
111 bankLength);
wdenkc6097192002-11-03 00:24:07 +0000112
wdenkbf9e3b32004-02-12 00:47:09 +0000113 pciSetRegionFeatures (host, bankNo, features, bankBase,
114 bankLength);
wdenkc6097192002-11-03 00:24:07 +0000115 }
116 return 0;
117}
118#endif
119
120/* ------------------------------------------------------------------------- */
121
122/* much of this code is based on (or is) the code in the pip405 port */
123/* thanks go to the authors of said port - Josh */
124
125
126/*
127 * translate ns.ns/10 coding of SPD timing values
128 * into 10 ps unit values
129 */
wdenkbf9e3b32004-02-12 00:47:09 +0000130static inline unsigned short NS10to10PS (unsigned char spd_byte)
wdenkc6097192002-11-03 00:24:07 +0000131{
132 unsigned short ns, ns10;
133
134 /* isolate upper nibble */
135 ns = (spd_byte >> 4) & 0x0F;
136 /* isolate lower nibble */
137 ns10 = (spd_byte & 0x0F);
138
wdenkbf9e3b32004-02-12 00:47:09 +0000139 return (ns * 100 + ns10 * 10);
wdenkc6097192002-11-03 00:24:07 +0000140}
141
142/*
143 * translate ns coding of SPD timing values
144 * into 10 ps unit values
145 */
wdenkbf9e3b32004-02-12 00:47:09 +0000146static inline unsigned short NSto10PS (unsigned char spd_byte)
wdenkc6097192002-11-03 00:24:07 +0000147{
wdenkbf9e3b32004-02-12 00:47:09 +0000148 return (spd_byte * 100);
wdenkc6097192002-11-03 00:24:07 +0000149}
150
151#ifdef CONFIG_ZUMA_V2
wdenkbf9e3b32004-02-12 00:47:09 +0000152static int check_dimm (uchar slot, sdram_info_t * info)
wdenkc6097192002-11-03 00:24:07 +0000153{
wdenk8bde7f72003-06-27 21:31:46 +0000154 /* assume 2 dimms, 2 banks each 256M - we dont have an
wdenkc6097192002-11-03 00:24:07 +0000155 * dimm i2c so rely on the detection routines later */
156
wdenkbf9e3b32004-02-12 00:47:09 +0000157 memset (info, 0, sizeof (*info));
wdenkc6097192002-11-03 00:24:07 +0000158
159 info->slot = slot;
160 info->banks = 2; /* Detect later */
wdenkbf9e3b32004-02-12 00:47:09 +0000161 info->registered = 0;
wdenkc6097192002-11-03 00:24:07 +0000162 info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
163 but doesn't matter, both do same
164 thing in setup_sdram() */
wdenkbf9e3b32004-02-12 00:47:09 +0000165 info->tpar = 3;
166 info->tras_clocks = 5;
167 info->burst_len = 4;
wdenkc6097192002-11-03 00:24:07 +0000168#ifdef CONFIG_ECC
169 info->ecc = 0; /* Detect later */
170#endif /* CONFIG_ECC */
171 return 0;
172}
173
wdenk12f34242003-09-02 22:48:03 +0000174#elif defined(CONFIG_P3G4)
175
wdenkbf9e3b32004-02-12 00:47:09 +0000176static int check_dimm (uchar slot, sdram_info_t * info)
wdenk12f34242003-09-02 22:48:03 +0000177{
wdenkbf9e3b32004-02-12 00:47:09 +0000178 memset (info, 0, sizeof (*info));
wdenk12f34242003-09-02 22:48:03 +0000179
180 if (slot)
181 return 0;
182
183 info->slot = slot;
184 info->banks = 1;
185 info->registered = 0;
186 info->drb_size = 4;
187 info->tpar = 3;
188 info->tras_clocks = 6;
189 info->burst_len = 4;
190#ifdef CONFIG_ECC
191 info->ecc = 2;
192#endif
193 return 0;
194}
195
wdenkbf9e3b32004-02-12 00:47:09 +0000196#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
wdenkc6097192002-11-03 00:24:07 +0000197
198/* This code reads the SPD chip on the sdram and populates
199 * the array which is passed in with the relevant information */
wdenkbf9e3b32004-02-12 00:47:09 +0000200static int check_dimm (uchar slot, sdram_info_t * info)
wdenkc6097192002-11-03 00:24:07 +0000201{
202 DECLARE_GLOBAL_DATA_PTR;
203 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
204 int ret;
205 uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
206 ulong tmemclk;
207 uchar trp_clocks, trcd_clocks;
208 uchar data[128];
209
210 get_clocks ();
211
wdenkbf9e3b32004-02-12 00:47:09 +0000212 tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
wdenkc6097192002-11-03 00:24:07 +0000213
214#ifdef CONFIG_EVB64260_750CX
215 if (0 != slot) {
wdenkbf9e3b32004-02-12 00:47:09 +0000216 printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
217 printf (" called with slot=%d insetad!\n", slot);
wdenkc6097192002-11-03 00:24:07 +0000218 return 0;
219 }
220#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000221 DP (puts ("before i2c read\n"));
wdenkc6097192002-11-03 00:24:07 +0000222
wdenkbf9e3b32004-02-12 00:47:09 +0000223 ret = i2c_read (addr, 0, 128, data, 0);
wdenkc6097192002-11-03 00:24:07 +0000224
wdenkbf9e3b32004-02-12 00:47:09 +0000225 DP (puts ("after i2c read\n"));
wdenkc6097192002-11-03 00:24:07 +0000226
227 /* zero all the values */
wdenkbf9e3b32004-02-12 00:47:09 +0000228 memset (info, 0, sizeof (*info));
wdenkc6097192002-11-03 00:24:07 +0000229
230 if (ret) {
wdenkbf9e3b32004-02-12 00:47:09 +0000231 DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
wdenkc6097192002-11-03 00:24:07 +0000232 return 0;
233 }
234
235 /* first, do some sanity checks */
236 if (data[2] != 0x4) {
wdenkbf9e3b32004-02-12 00:47:09 +0000237 printf ("Not SDRAM in slot %d\n", slot);
wdenkc6097192002-11-03 00:24:07 +0000238 return 0;
239 }
240
241 /* get various information */
242 rows = data[3];
243 cols = data[4];
244 info->banks = data[5];
245 sdram_banks = data[17];
246 width = data[13] & 0x7f;
247
wdenkbf9e3b32004-02-12 00:47:09 +0000248 DP (printf
249 ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
wdenkc6097192002-11-03 00:24:07 +0000250
251 /* check if the memory is registered */
252 if (data[21] & (BIT1 | BIT4))
253 info->registered = 1;
254
255#ifdef CONFIG_ECC
256 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
257 info->ecc = (data[11] & 2) >> 1;
258#endif
259
260 /* bit 1 is CL2, bit 2 is CL3 */
261 supp_cal = (data[18] & 0x6) >> 1;
262
263 /* compute the relevant clock values */
wdenkbf9e3b32004-02-12 00:47:09 +0000264 trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
265 trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
266 info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
wdenkc6097192002-11-03 00:24:07 +0000267
wdenkbf9e3b32004-02-12 00:47:09 +0000268 DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
269 trp_clocks, trcd_clocks, info->tras_clocks));
wdenkc6097192002-11-03 00:24:07 +0000270
271 /* try a CAS latency of 3 first... */
272 cal_val = 0;
273 if (supp_cal & 3) {
wdenkbf9e3b32004-02-12 00:47:09 +0000274 if (NS10to10PS (data[9]) <= tmemclk)
wdenkc6097192002-11-03 00:24:07 +0000275 cal_val = 3;
276 }
277
278 /* then 2... */
279 if (supp_cal & 2) {
wdenkbf9e3b32004-02-12 00:47:09 +0000280 if (NS10to10PS (data[23]) <= tmemclk)
wdenkc6097192002-11-03 00:24:07 +0000281 cal_val = 2;
282 }
283
wdenkbf9e3b32004-02-12 00:47:09 +0000284 DP (printf ("cal_val = %d\n", cal_val));
wdenkc6097192002-11-03 00:24:07 +0000285
286 /* bummer, did't work... */
287 if (cal_val == 0) {
wdenkbf9e3b32004-02-12 00:47:09 +0000288 DP (printf ("Couldn't find a good CAS latency\n"));
wdenkc6097192002-11-03 00:24:07 +0000289 return 0;
290 }
291
292 /* get the largest delay -- these values need to all be the same
293 * see Res#6 */
294 info->tpar = cal_val;
295 if (trp_clocks > info->tpar)
296 info->tpar = trp_clocks;
297 if (trcd_clocks > info->tpar)
298 info->tpar = trcd_clocks;
299
wdenkbf9e3b32004-02-12 00:47:09 +0000300 DP (printf ("tpar set to: %d\n", info->tpar));
wdenkc6097192002-11-03 00:24:07 +0000301
302#ifdef CFG_BROKEN_CL2
wdenkbf9e3b32004-02-12 00:47:09 +0000303 if (info->tpar == 2) {
wdenkc6097192002-11-03 00:24:07 +0000304 info->tpar = 3;
wdenkbf9e3b32004-02-12 00:47:09 +0000305 DP (printf ("tpar fixed-up to: %d\n", info->tpar));
wdenkc6097192002-11-03 00:24:07 +0000306 }
307#endif
308 /* compute the module DRB size */
wdenkbf9e3b32004-02-12 00:47:09 +0000309 info->drb_size =
310 (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
wdenkc6097192002-11-03 00:24:07 +0000311
wdenkbf9e3b32004-02-12 00:47:09 +0000312 DP (printf ("drb_size set to: %d\n", info->drb_size));
wdenkc6097192002-11-03 00:24:07 +0000313
314 /* find the burst len */
315 info->burst_len = data[16] & 0xf;
316 if ((info->burst_len & 8) == 8) {
317 info->burst_len = 1;
318 } else if ((info->burst_len & 4) == 4) {
319 info->burst_len = 0;
320 } else {
321 return 0;
322 }
323
324 info->slot = slot;
325 return 0;
326}
327#endif /* ! CONFIG_ZUMA_V2 */
328
wdenkbf9e3b32004-02-12 00:47:09 +0000329static int setup_sdram_common (sdram_info_t info[2])
wdenkc6097192002-11-03 00:24:07 +0000330{
wdenk8bde7f72003-06-27 21:31:46 +0000331 ulong tmp;
wdenkbf9e3b32004-02-12 00:47:09 +0000332 int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
wdenkc6097192002-11-03 00:24:07 +0000333
wdenkbf9e3b32004-02-12 00:47:09 +0000334 if (!info[0].banks && !info[1].banks)
335 return 0;
wdenkc6097192002-11-03 00:24:07 +0000336
wdenkbf9e3b32004-02-12 00:47:09 +0000337 if (info[0].banks) {
338 if (info[0].tpar > tpar)
339 tpar = info[0].tpar;
340 if (info[0].tras_clocks > tras_clocks)
341 tras_clocks = info[0].tras_clocks;
342 if (!info[0].registered)
343 registered = 0;
wdenk3f85ce22004-02-23 16:11:30 +0000344 if (info[0].ecc != 2)
wdenkbf9e3b32004-02-12 00:47:09 +0000345 ecc = 0;
wdenkc6097192002-11-03 00:24:07 +0000346 }
347
wdenkbf9e3b32004-02-12 00:47:09 +0000348 if (info[1].banks) {
349 if (info[1].tpar > tpar)
350 tpar = info[1].tpar;
351 if (info[1].tras_clocks > tras_clocks)
352 tras_clocks = info[1].tras_clocks;
353 if (!info[1].registered)
354 registered = 0;
355 if (info[1].ecc != 2)
356 ecc = 0;
wdenkc6097192002-11-03 00:24:07 +0000357 }
358
359 /* SDRAM configuration */
wdenkbf9e3b32004-02-12 00:47:09 +0000360 tmp = GTREGREAD (SDRAM_CONFIGURATION);
wdenkc6097192002-11-03 00:24:07 +0000361
362 /* Turn on physical interleave if both DIMMs
363 * have even numbers of banks. */
wdenkbf9e3b32004-02-12 00:47:09 +0000364 if ((info[0].banks == 0 || info[0].banks == 2) &&
365 (info[1].banks == 0 || info[1].banks == 2)) {
366 /* physical interleave on */
367 tmp &= ~(1 << 15);
wdenkc6097192002-11-03 00:24:07 +0000368 } else {
wdenkbf9e3b32004-02-12 00:47:09 +0000369 /* physical interleave off */
370 tmp |= (1 << 15);
wdenkc6097192002-11-03 00:24:07 +0000371 }
372
373 tmp |= (registered << 17);
374
375 /* Use buffer 1 to return read data to the CPU
376 * See Res #12 */
377 tmp |= (1 << 26);
378
wdenkbf9e3b32004-02-12 00:47:09 +0000379 GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
380 DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
wdenkc6097192002-11-03 00:24:07 +0000381
382 /* SDRAM timing */
383 tmp = (((tpar == 3) ? 2 : 1) |
384 (((tpar == 3) ? 2 : 1) << 2) |
wdenkbf9e3b32004-02-12 00:47:09 +0000385 (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
wdenkc6097192002-11-03 00:24:07 +0000386
387#ifdef CONFIG_ECC
388 /* Setup ECC */
wdenkbf9e3b32004-02-12 00:47:09 +0000389 if (ecc == 2)
390 tmp |= 1 << 13;
wdenkc6097192002-11-03 00:24:07 +0000391#endif /* CONFIG_ECC */
392
wdenkbf9e3b32004-02-12 00:47:09 +0000393 GT_REG_WRITE (SDRAM_TIMING, tmp);
394 DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
395 GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
wdenkc6097192002-11-03 00:24:07 +0000396
397 /* SDRAM address decode register */
398 /* program this with the default value */
wdenkbf9e3b32004-02-12 00:47:09 +0000399 GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
400 DP (printf ("SDRAM decode: %08x\n",
401 GTREGREAD (SDRAM_ADDRESS_DECODE)));
wdenkc6097192002-11-03 00:24:07 +0000402
403 return 0;
404}
405
406/* sets up the GT properly with information passed in */
wdenkbf9e3b32004-02-12 00:47:09 +0000407static int setup_sdram (sdram_info_t * info)
wdenkc6097192002-11-03 00:24:07 +0000408{
409 ulong tmp, check;
410 ulong *addr = 0;
411 int i;
412
413 /* sanity checking */
wdenkbf9e3b32004-02-12 00:47:09 +0000414 if (!info->banks)
415 return 0;
wdenkc6097192002-11-03 00:24:07 +0000416
417 /* ---------------------------- */
418 /* Program the GT with the discovered data */
419
420 /* bank parameters */
wdenkbf9e3b32004-02-12 00:47:09 +0000421 tmp = (0xf << 16); /* leave all virt bank pages open */
wdenkc6097192002-11-03 00:24:07 +0000422
wdenkbf9e3b32004-02-12 00:47:09 +0000423 DP (printf ("drb_size: %d\n", info->drb_size));
wdenkc6097192002-11-03 00:24:07 +0000424 switch (info->drb_size) {
425 case 1:
426 tmp |= (1 << 14);
427 break;
428 case 4:
429 case 8:
430 tmp |= (2 << 14);
431 break;
432 case 16:
433 case 32:
434 tmp |= (3 << 14);
435 break;
436 default:
wdenkbf9e3b32004-02-12 00:47:09 +0000437 printf ("Error in dram size calculation\n");
wdenkc6097192002-11-03 00:24:07 +0000438 return 1;
439 }
440
441 /* SDRAM bank parameters */
442 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
wdenkbf9e3b32004-02-12 00:47:09 +0000443 GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
444 GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
445 DP (printf
446 ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
447 info->slot * 2, (info->slot * 2) + 1, tmp));
wdenkc6097192002-11-03 00:24:07 +0000448
449 /* set the SDRAM configuration for each bank */
450 for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
wdenkbf9e3b32004-02-12 00:47:09 +0000451 DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
wdenkc6097192002-11-03 00:24:07 +0000452
453 /* map the bank */
wdenkbf9e3b32004-02-12 00:47:09 +0000454 memory_map_bank (i, 0, GB / 4);
wdenkc6097192002-11-03 00:24:07 +0000455
456 /* set SDRAM mode */
wdenkbf9e3b32004-02-12 00:47:09 +0000457 GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
458 check = GTREGREAD (SDRAM_OPERATION_MODE);
wdenkc6097192002-11-03 00:24:07 +0000459
460 /* dummy write */
461 *addr = 0;
462
463 /* wait for the command to complete */
wdenkbf9e3b32004-02-12 00:47:09 +0000464 while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
wdenkc6097192002-11-03 00:24:07 +0000465
466 /* switch back to normal operation mode */
wdenkbf9e3b32004-02-12 00:47:09 +0000467 GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
468 check = GTREGREAD (SDRAM_OPERATION_MODE);
wdenkc6097192002-11-03 00:24:07 +0000469
470 /* unmap the bank */
wdenkbf9e3b32004-02-12 00:47:09 +0000471 memory_map_bank (i, 0, 0);
472 DP (printf ("*** MRS cycle for bank %d done ***\n", i));
wdenkc6097192002-11-03 00:24:07 +0000473 }
474
475 return 0;
476}
477
478/*
479 * Check memory range for valid RAM. A simple memory test determines
480 * the actually available RAM size between addresses `base' and
481 * `base + maxsize'. Some (not all) hardware errors are detected:
482 * - short between address lines
483 * - short between data lines
484 */
wdenkbf9e3b32004-02-12 00:47:09 +0000485static long int dram_size (long int *base, long int maxsize)
wdenkc6097192002-11-03 00:24:07 +0000486{
wdenkbf9e3b32004-02-12 00:47:09 +0000487 volatile long int *addr, *b = base;
488 long int cnt, val, save1, save2;
wdenkc6097192002-11-03 00:24:07 +0000489
490#define STARTVAL (1<<20) /* start test at 1M */
wdenkbf9e3b32004-02-12 00:47:09 +0000491 for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
492 cnt <<= 1) {
493 addr = base + cnt; /* pointer arith! */
wdenkc6097192002-11-03 00:24:07 +0000494
wdenkbf9e3b32004-02-12 00:47:09 +0000495 save1 = *addr; /* save contents of addr */
496 save2 = *b; /* save contents of base */
wdenkc6097192002-11-03 00:24:07 +0000497
wdenkbf9e3b32004-02-12 00:47:09 +0000498 *addr = cnt; /* write cnt to addr */
499 *b = 0; /* put null at base */
wdenkc6097192002-11-03 00:24:07 +0000500
wdenkbf9e3b32004-02-12 00:47:09 +0000501 /* check at base address */
502 if ((*b) != 0) {
503 *addr = save1; /* restore *addr */
504 *b = save2; /* restore *b */
505 return (0);
506 }
507 val = *addr; /* read *addr */
wdenkc6097192002-11-03 00:24:07 +0000508
wdenkbf9e3b32004-02-12 00:47:09 +0000509 *addr = save1;
510 *b = save2;
wdenkc6097192002-11-03 00:24:07 +0000511
wdenkbf9e3b32004-02-12 00:47:09 +0000512 if (val != cnt) {
513 /* fix boundary condition.. STARTVAL means zero */
514 if (cnt == STARTVAL / sizeof (long))
515 cnt = 0;
516 return (cnt * sizeof (long));
517 }
518 }
519 return maxsize;
wdenkc6097192002-11-03 00:24:07 +0000520}
521
522/* ------------------------------------------------------------------------- */
523
524/* U-Boot interface function to SDRAM init - this is where all the
525 * controlling logic happens */
wdenkbf9e3b32004-02-12 00:47:09 +0000526long int initdram (int board_type)
wdenkc6097192002-11-03 00:24:07 +0000527{
wdenkbf9e3b32004-02-12 00:47:09 +0000528 ulong checkbank[4] = {[0 ... 3] = 0 };
wdenkc6097192002-11-03 00:24:07 +0000529 int bank_no;
wdenk8bde7f72003-06-27 21:31:46 +0000530 ulong total;
wdenkc6097192002-11-03 00:24:07 +0000531 int nhr;
532 sdram_info_t dimm_info[2];
533
534
535 /* first, use the SPD to get info about the SDRAM */
536
537 /* check the NHR bit and skip mem init if it's already done */
wdenkbf9e3b32004-02-12 00:47:09 +0000538 nhr = get_hid0 () & (1 << 16);
wdenkc6097192002-11-03 00:24:07 +0000539
540 if (nhr) {
wdenkbf9e3b32004-02-12 00:47:09 +0000541 printf ("Skipping SDRAM setup due to NHR bit being set\n");
wdenkc6097192002-11-03 00:24:07 +0000542 } else {
543 /* DIMM0 */
wdenkbf9e3b32004-02-12 00:47:09 +0000544 check_dimm (0, &dimm_info[0]);
wdenkc6097192002-11-03 00:24:07 +0000545
546 /* DIMM1 */
wdenkbf9e3b32004-02-12 00:47:09 +0000547#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
548 check_dimm (1, &dimm_info[1]);
549#else /* CONFIG_EVB64260_750CX */
550 memset (&dimm_info[1], 0, sizeof (sdram_info_t));
wdenkc6097192002-11-03 00:24:07 +0000551#endif
552
553 /* unmap all banks */
wdenkbf9e3b32004-02-12 00:47:09 +0000554 memory_map_bank (0, 0, 0);
555 memory_map_bank (1, 0, 0);
556 memory_map_bank (2, 0, 0);
557 memory_map_bank (3, 0, 0);
wdenkc6097192002-11-03 00:24:07 +0000558
559 /* Now, program the GT with the correct values */
wdenkbf9e3b32004-02-12 00:47:09 +0000560 if (setup_sdram_common (dimm_info)) {
561 printf ("Setup common failed.\n");
wdenkc6097192002-11-03 00:24:07 +0000562 }
563
wdenkbf9e3b32004-02-12 00:47:09 +0000564 if (setup_sdram (&dimm_info[0])) {
565 printf ("Setup for DIMM1 failed.\n");
wdenkc6097192002-11-03 00:24:07 +0000566 }
567
wdenkbf9e3b32004-02-12 00:47:09 +0000568 if (setup_sdram (&dimm_info[1])) {
569 printf ("Setup for DIMM2 failed.\n");
wdenkc6097192002-11-03 00:24:07 +0000570 }
571
572 /* set the NHR bit */
wdenkbf9e3b32004-02-12 00:47:09 +0000573 set_hid0 (get_hid0 () | (1 << 16));
wdenkc6097192002-11-03 00:24:07 +0000574 }
575 /* next, size the SDRAM banks */
576
577 total = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000578 if (dimm_info[0].banks > 0)
579 checkbank[0] = 1;
580 if (dimm_info[0].banks > 1)
581 checkbank[1] = 1;
wdenkc6097192002-11-03 00:24:07 +0000582 if (dimm_info[0].banks > 2)
wdenkbf9e3b32004-02-12 00:47:09 +0000583 printf ("Error, SPD claims DIMM1 has >2 banks\n");
wdenkc6097192002-11-03 00:24:07 +0000584
wdenkbf9e3b32004-02-12 00:47:09 +0000585 if (dimm_info[1].banks > 0)
586 checkbank[2] = 1;
587 if (dimm_info[1].banks > 1)
588 checkbank[3] = 1;
wdenkc6097192002-11-03 00:24:07 +0000589 if (dimm_info[1].banks > 2)
wdenkbf9e3b32004-02-12 00:47:09 +0000590 printf ("Error, SPD claims DIMM2 has >2 banks\n");
wdenkc6097192002-11-03 00:24:07 +0000591
592 /* Generic dram sizer: works even if we don't have i2c DIMMs,
593 * as long as the timing settings are more or less correct */
594
595 /*
596 * pass 1: size all the banks, using first bat (0-256M)
wdenkbf9e3b32004-02-12 00:47:09 +0000597 * limitation: we only support 256M per bank due to
598 * us only having 1 BAT for all DRAM
wdenkc6097192002-11-03 00:24:07 +0000599 */
600 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
601 /* skip over banks that are not populated */
wdenkbf9e3b32004-02-12 00:47:09 +0000602 if (!checkbank[bank_no])
wdenkc6097192002-11-03 00:24:07 +0000603 continue;
604
wdenkbf9e3b32004-02-12 00:47:09 +0000605 DP (printf ("checking bank %d\n", bank_no));
wdenkc6097192002-11-03 00:24:07 +0000606
wdenkbf9e3b32004-02-12 00:47:09 +0000607 memory_map_bank (bank_no, 0, GB / 4);
608 checkbank[bank_no] = dram_size (NULL, GB / 4);
609 memory_map_bank (bank_no, 0, 0);
wdenkc6097192002-11-03 00:24:07 +0000610
wdenkbf9e3b32004-02-12 00:47:09 +0000611 DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
wdenkc6097192002-11-03 00:24:07 +0000612 }
613
614 /*
615 * pass 2: contiguously map each bank into physical address
wdenkbf9e3b32004-02-12 00:47:09 +0000616 * space.
wdenkc6097192002-11-03 00:24:07 +0000617 */
wdenkbf9e3b32004-02-12 00:47:09 +0000618 dimm_info[0].banks = dimm_info[1].banks = 0;
wdenkc6097192002-11-03 00:24:07 +0000619 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
wdenkbf9e3b32004-02-12 00:47:09 +0000620 if (!checkbank[bank_no])
621 continue;
wdenkc6097192002-11-03 00:24:07 +0000622
wdenkbf9e3b32004-02-12 00:47:09 +0000623 dimm_info[bank_no / 2].banks++;
624 dimm_info[bank_no / 2].size += checkbank[bank_no];
wdenkc6097192002-11-03 00:24:07 +0000625
wdenkbf9e3b32004-02-12 00:47:09 +0000626 memory_map_bank (bank_no, total, checkbank[bank_no]);
wdenkc6097192002-11-03 00:24:07 +0000627#ifdef MAP_PCI
wdenkbf9e3b32004-02-12 00:47:09 +0000628 memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
wdenkc6097192002-11-03 00:24:07 +0000629#endif
630 total += checkbank[bank_no];
631 }
632
633#ifdef CONFIG_ECC
634#ifdef CONFIG_ZUMA_V2
635 /*
636 * We always enable ECC when bank 2 and 3 are unpopulated
637 * If we 2 or 3 are populated, we CAN'T support ECC.
638 * (Zuma boards only support ECC in banks 0 and 1; assume that
639 * in that configuration, ECC chips are mounted, even for stacked
640 * chips)
641 */
wdenkbf9e3b32004-02-12 00:47:09 +0000642 if (checkbank[2] == 0 && checkbank[3] == 0) {
643 dimm_info[0].ecc = 2;
644 GT_REG_WRITE (SDRAM_TIMING,
645 GTREGREAD (SDRAM_TIMING) | (1 << 13));
wdenkc6097192002-11-03 00:24:07 +0000646 /* TODO: do we have to run MRS cycles again? */
647 }
648#endif /* CONFIG_ZUMA_V2 */
649
wdenkbf9e3b32004-02-12 00:47:09 +0000650 if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
651 puts ("[ECC] ");
wdenkc6097192002-11-03 00:24:07 +0000652 }
653#endif /* CONFIG_ECC */
654
655#ifdef DEBUG
wdenkbf9e3b32004-02-12 00:47:09 +0000656 dump_dimm_info (&dimm_info[0]);
657 dump_dimm_info (&dimm_info[1]);
wdenkc6097192002-11-03 00:24:07 +0000658#endif
659 /* TODO: return at MOST 256M? */
wdenk8bde7f72003-06-27 21:31:46 +0000660 /* return total > GB/4 ? GB/4 : total; */
wdenkc6097192002-11-03 00:24:07 +0000661 return total;
662}