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wdenk71f95112003-06-15 22:40:42 +00001/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Thomas Chouabe2c932011-04-19 03:48:31 +000017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk71f95112003-06-15 22:40:42 +000018 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef _MMC_H_
27#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000028
Andy Fleming272cc702008-10-30 16:41:01 -050029#include <linux/list.h>
30
31#define SD_VERSION_SD 0x20000
32#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
33#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
34#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
35#define MMC_VERSION_MMC 0x10000
36#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
37#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
38#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
39#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
40#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
41#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
42
43#define MMC_MODE_HS 0x001
44#define MMC_MODE_HS_52MHz 0x010
45#define MMC_MODE_4BIT 0x100
46#define MMC_MODE_8BIT 0x200
Thomas Choud52ebf12010-12-24 13:12:21 +000047#define MMC_MODE_SPI 0x400
Ɓukasz Majewskib1f1e8212011-07-05 02:19:44 +000048#define MMC_MODE_HC 0x800
Andy Fleming272cc702008-10-30 16:41:01 -050049
50#define SD_DATA_4BIT 0x00040000
51
Albin Tonnerre79b91de2009-08-22 14:21:53 +020052#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Fleming272cc702008-10-30 16:41:01 -050053
54#define MMC_DATA_READ 1
55#define MMC_DATA_WRITE 2
56
57#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
58#define UNUSABLE_ERR -17 /* Unusable Card */
59#define COMM_ERR -18 /* Communications Error */
60#define TIMEOUT -19
61
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020062#define MMC_CMD_GO_IDLE_STATE 0
63#define MMC_CMD_SEND_OP_COND 1
64#define MMC_CMD_ALL_SEND_CID 2
65#define MMC_CMD_SET_RELATIVE_ADDR 3
66#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050067#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020068#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050069#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020070#define MMC_CMD_SEND_CSD 9
71#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050072#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020073#define MMC_CMD_SEND_STATUS 13
74#define MMC_CMD_SET_BLOCKLEN 16
75#define MMC_CMD_READ_SINGLE_BLOCK 17
76#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Fleming272cc702008-10-30 16:41:01 -050077#define MMC_CMD_WRITE_SINGLE_BLOCK 24
78#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +000079#define MMC_CMD_ERASE_GROUP_START 35
80#define MMC_CMD_ERASE_GROUP_END 36
81#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020082#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +000083#define MMC_CMD_SPI_READ_OCR 58
84#define MMC_CMD_SPI_CRC_ON_OFF 59
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020085
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020086#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -050087#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020088#define SD_CMD_SEND_IF_COND 8
89
90#define SD_CMD_APP_SET_BUS_WIDTH 6
Lei Wene6f99a52011-06-22 17:03:31 +000091#define SD_CMD_ERASE_WR_BLK_START 32
92#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020093#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -050094#define SD_CMD_APP_SEND_SCR 51
95
96/* SCR definitions in different words */
97#define SD_HIGHSPEED_BUSY 0x00020000
98#define SD_HIGHSPEED_SUPPORTED 0x00020000
99
100#define MMC_HS_TIMING 0x00000100
101#define MMC_HS_52MHZ 0x2
102
Thomas Chouabe2c932011-04-19 03:48:31 +0000103#define OCR_BUSY 0x80000000
104#define OCR_HCS 0x40000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000105#define OCR_VOLTAGE_MASK 0x007FFF80
106#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500107
Lei Wene6f99a52011-06-22 17:03:31 +0000108#define SECURE_ERASE 0x80000000
109
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000110#define MMC_STATUS_MASK (~0x0206BF7F)
Thomas Chouabe2c932011-04-19 03:48:31 +0000111#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
112#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000113#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000114
Andy Fleming272cc702008-10-30 16:41:01 -0500115#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
116#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
117#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
118#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
119#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
120#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
121#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
122#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
123#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
124#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
125#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
126#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
127#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
128#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
129#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
130#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
131#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
132
133#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
134#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
135 addressed by index which are
136 1 in value field */
137#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
138 addressed by index, which are
139 1 in value field */
140#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
141
142#define SD_SWITCH_CHECK 0
143#define SD_SWITCH_SWITCH 1
144
145/*
146 * EXT_CSD fields
147 */
148
Lei Wenbc897b12011-05-02 16:26:26 +0000149#define EXT_CSD_PART_CONF 179 /* R/W */
Andy Fleming272cc702008-10-30 16:41:01 -0500150#define EXT_CSD_BUS_WIDTH 183 /* R/W */
151#define EXT_CSD_HS_TIMING 185 /* R/W */
152#define EXT_CSD_CARD_TYPE 196 /* RO */
153#define EXT_CSD_REV 192 /* RO */
154#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
155
156/*
157 * EXT_CSD field definitions
158 */
159
Thomas Chouabe2c932011-04-19 03:48:31 +0000160#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
161#define EXT_CSD_CMD_SET_SECURE (1 << 1)
162#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500163
Thomas Chouabe2c932011-04-19 03:48:31 +0000164#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
165#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Andy Fleming272cc702008-10-30 16:41:01 -0500166
167#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
168#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
169#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200170
Andy Fleming1de97f92008-10-30 16:31:39 -0500171#define R1_ILLEGAL_COMMAND (1 << 22)
172#define R1_APP_CMD (1 << 5)
173
Andy Fleming272cc702008-10-30 16:41:01 -0500174#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000175#define MMC_RSP_136 (1 << 1) /* 136 bit response */
176#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
177#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
178#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500179
Thomas Chouabe2c932011-04-19 03:48:31 +0000180#define MMC_RSP_NONE (0)
181#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500182#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
183 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000184#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
185#define MMC_RSP_R3 (MMC_RSP_PRESENT)
186#define MMC_RSP_R4 (MMC_RSP_PRESENT)
187#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
188#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
189#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500190
Lei Wenbc897b12011-05-02 16:26:26 +0000191#define MMCPART_NOAVAILABLE (0xff)
192#define PART_ACCESS_MASK (0x7)
193#define PART_SUPPORT (0x1)
wdenk71f95112003-06-15 22:40:42 +0000194
Andy Fleming1de97f92008-10-30 16:31:39 -0500195struct mmc_cid {
196 unsigned long psn;
197 unsigned short oid;
198 unsigned char mid;
199 unsigned char prv;
200 unsigned char mdt;
201 char pnm[7];
202};
203
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200204/*
205 * WARNING!
206 *
207 * This structure is used by atmel_mci.c only.
208 * It works for the AVR32 architecture but NOT
209 * for ARM/AT91 architectures.
210 * Its use is highly depreciated.
211 * After the atmel_mci.c driver for AVR32 has
212 * been replaced this structure will be removed.
213 */
Andy Fleming1de97f92008-10-30 16:31:39 -0500214struct mmc_csd
215{
216 u8 csd_structure:2,
217 spec_vers:4,
218 rsvd1:2;
219 u8 taac;
220 u8 nsac;
221 u8 tran_speed;
222 u16 ccc:12,
223 read_bl_len:4;
224 u64 read_bl_partial:1,
225 write_blk_misalign:1,
226 read_blk_misalign:1,
227 dsr_imp:1,
228 rsvd2:2,
229 c_size:12,
230 vdd_r_curr_min:3,
231 vdd_r_curr_max:3,
232 vdd_w_curr_min:3,
233 vdd_w_curr_max:3,
234 c_size_mult:3,
235 sector_size:5,
236 erase_grp_size:5,
237 wp_grp_size:5,
238 wp_grp_enable:1,
239 default_ecc:2,
240 r2w_factor:3,
241 write_bl_len:4,
242 write_bl_partial:1,
243 rsvd3:5;
244 u8 file_format_grp:1,
245 copy:1,
246 perm_write_protect:1,
247 tmp_write_protect:1,
248 file_format:2,
249 ecc:2;
250 u8 crc:7;
251 u8 one:1;
252};
253
Andy Fleming272cc702008-10-30 16:41:01 -0500254struct mmc_cmd {
255 ushort cmdidx;
256 uint resp_type;
257 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530258 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500259 uint flags;
260};
261
262struct mmc_data {
263 union {
264 char *dest;
265 const char *src; /* src buffers don't get written to */
266 };
267 uint flags;
268 uint blocks;
269 uint blocksize;
270};
271
272struct mmc {
273 struct list_head link;
274 char name[32];
275 void *priv;
276 uint voltages;
277 uint version;
Lei Wenbc897b12011-05-02 16:26:26 +0000278 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500279 uint f_min;
280 uint f_max;
281 int high_capacity;
282 uint bus_width;
283 uint clock;
284 uint card_caps;
285 uint host_caps;
286 uint ocr;
287 uint scr[2];
288 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530289 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500290 ushort rca;
Lei Wenbc897b12011-05-02 16:26:26 +0000291 char part_config;
292 char part_num;
Andy Fleming272cc702008-10-30 16:41:01 -0500293 uint tran_speed;
294 uint read_bl_len;
295 uint write_bl_len;
Lei Wene6f99a52011-06-22 17:03:31 +0000296 uint erase_grp_size;
Andy Fleming272cc702008-10-30 16:41:01 -0500297 u64 capacity;
298 block_dev_desc_t block_dev;
299 int (*send_cmd)(struct mmc *mmc,
300 struct mmc_cmd *cmd, struct mmc_data *data);
301 void (*set_ios)(struct mmc *mmc);
302 int (*init)(struct mmc *mmc);
Sandeep Paulraj57418d22010-12-20 20:01:21 -0500303 uint b_max;
Andy Fleming272cc702008-10-30 16:41:01 -0500304};
305
306int mmc_register(struct mmc *mmc);
307int mmc_initialize(bd_t *bis);
308int mmc_init(struct mmc *mmc);
309int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang4a6ee172010-11-25 17:06:07 +0000310void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Fleming272cc702008-10-30 16:41:01 -0500311struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700312int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500313void print_mmc_devices(char separator);
Lei Wenea6ebe22011-05-02 16:26:25 +0000314int get_mmc_num(void);
Stefano Babic11fdade2010-02-05 15:04:43 +0100315int board_mmc_getcd(u8 *cd, struct mmc *mmc);
Lei Wenbc897b12011-05-02 16:26:26 +0000316int mmc_switch_part(int dev_num, unsigned int part_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500317
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200318#ifdef CONFIG_GENERIC_MMC
319int atmel_mci_init(void *regs);
Thomas Choud52ebf12010-12-24 13:12:21 +0000320#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
321struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200322#else
Andy Fleming272cc702008-10-30 16:41:01 -0500323int mmc_legacy_init(int verbose);
324#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200325
wdenk71f95112003-06-15 22:40:42 +0000326#endif /* _MMC_H_ */