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Mike Frysingercb4b5e82008-10-12 23:08:03 -04001/*
2 * U-boot - Configuration file for BF537 PNAV board
3 */
4
5#ifndef __CONFIG_BF537_PNAV_H__
6#define __CONFIG_BF537_PNAV_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingercb4b5e82008-10-12 23:08:03 -04009
10
11/*
12 * Processor Settings
13 */
14#define CONFIG_BFIN_CPU bf537-0.2
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 24576000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x3b7
49#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
50
51#define CONFIG_EBIU_AMGCTL_VAL 0xFF
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
57
58
59/*
60 * Network Settings
61 */
62#ifndef __ADSPBF534__
63#define ADI_CMDS_NETWORK 1
64#define CONFIG_BFIN_MAC
65#define CONFIG_RMII
66#define CONFIG_NET_MULTI 1
67#endif
68#define CONFIG_HOSTNAME bf537-pnav
69/* Uncomment next line to use fixed MAC address */
70/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */
71
72
73/*
74 * Flash Settings
75 */
76#define CONFIG_FLASH_CFI_DRIVER
77#define CONFIG_SYS_FLASH_BASE 0x20000000
78#define CONFIG_SYS_FLASH_CFI
79#define CONFIG_SYS_MAX_FLASH_BANKS 1
80#define CONFIG_SYS_MAX_FLASH_SECT 71
81
82
83/*
84 * SPI Settings
85 */
86#define CONFIG_BFIN_SPI
87#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040088#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercb4b5e82008-10-12 23:08:03 -040089#define CONFIG_SPI_FLASH
90#define CONFIG_SPI_FLASH_STMICRO
91
92
93/*
94 * Env Storage Settings
95 */
96#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysinger76d82182009-07-21 22:17:36 -040097#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingercb4b5e82008-10-12 23:08:03 -040098#define CONFIG_ENV_IS_IN_SPI_FLASH
99#define CONFIG_ENV_OFFSET 0x4000
100#else
101#define ENV_IS_EMBEDDED
102#define CONFIG_ENV_IS_IN_FLASH 1
103#define CONFIG_ENV_ADDR 0x20004000
104#define CONFIG_ENV_OFFSET 0x4000
105#endif
106#define CONFIG_ENV_SIZE 0x1000
107#define CONFIG_ENV_SECT_SIZE 0x2000
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400108#ifdef ENV_IS_EMBEDDED
109/* WARNING - the following is hand-optimized to fit within
110 * the sector before the environment sector. If it throws
111 * an error during compilation remove an object here to get
112 * it linked after the configuration sector.
113 */
114# define LDS_BOARD_TEXT \
115 cpu/blackfin/traps.o (.text .text.*); \
116 cpu/blackfin/interrupt.o (.text .text.*); \
117 cpu/blackfin/serial.o (.text .text.*); \
118 common/dlmalloc.o (.text .text.*); \
119 lib_generic/crc32.o (.text .text.*); \
120 . = DEFINED(env_offset) ? env_offset : .; \
121 common/env_embedded.o (.text .text.*);
122#endif
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400123
124
125/*
126 * NAND Settings
127 */
128#define CONFIG_NAND_PLAT
129
130#define CONFIG_SYS_NAND_BASE 0x20100000
131#define CONFIG_SYS_MAX_NAND_DEVICE 1
132
133#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
134#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
135#define BFIN_NAND_READY PF12
136#define BFIN_NAND_WRITE(addr, cmd) \
137 do { \
138 bfin_write8(addr, cmd); \
139 SSYNC(); \
140 } while (0)
141
142#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
143#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
144#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY)
145#define NAND_PLAT_INIT() \
146 do { \
147 bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
148 bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
149 bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
150 } while (0)
151
152
153/*
154 * I2C settings
155 */
156#define CONFIG_BFIN_TWI_I2C 1
157#define CONFIG_HARD_I2C 1
158#define CONFIG_SYS_I2C_SPEED 50000
159#define CONFIG_SYS_I2C_SLAVE 0
160
161
162/*
163 * Misc Settings
164 */
165#define CONFIG_BAUDRATE 115200
166#define CONFIG_MISC_INIT_R
167#define CONFIG_RTC_BFIN
168#define CONFIG_UART_CONSOLE 0
169
170/* JFFS Partition offset set */
171#define CONFIG_SYS_JFFS2_FIRST_BANK 0
172#define CONFIG_SYS_JFFS2_NUM_BANKS 1
173/* 512k reserved for u-boot */
174#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
175
176#define CONFIG_BOOTCOMMAND "run nandboot"
177#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
178
179
180/*
181 * Pull in common ADI header for remaining command/environment setup
182 */
183#include <configs/bfin_adi_common.h>
184
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400185#endif