blob: 1aaf064c30cf3a1e0e114d6b1da9d9321cb6f4ec [file] [log] [blame]
Patrick Delaunaye70f70a2018-03-12 10:46:11 +01001
2config STM32MP1_DDR
3 bool "STM32MP1 DDR driver"
4 depends on DM && OF_CONTROL && ARCH_STM32MP
5 select RAM
6 select SPL_RAM if SPL
7 default y
8 help
9 activate STM32MP1 DDR controller driver for STM32MP1 soc
10 family: support for LPDDR2, LPDDR3 and DDR3
11 the SDRAM parameters for controleur and phy need to be provided
12 in device tree (computed by DDR tuning tools)
Patrick Delaunay01a75102019-04-10 14:09:27 +020013
14config STM32MP1_DDR_INTERACTIVE
15 bool "STM32MP1 DDR driver : interactive support"
16 depends on STM32MP1_DDR
17 help
18 activate interactive support in STM32MP1 DDR controller driver
19 used for DDR tuning tools
20 to enter in intercative mode type 'd' during SPL DDR driver
21 initialisation
22
23config STM32MP1_DDR_INTERACTIVE_FORCE
24 bool "STM32MP1 DDR driver : force interactive mode"
25 depends on STM32MP1_DDR_INTERACTIVE
Patrick Delaunay01a75102019-04-10 14:09:27 +020026 help
27 force interactive mode in STM32MP1 DDR controller driver
28 skip the polling of character 'd' in console
29 useful when SPL is loaded in sysram
30 directly by programmer
Patrick Delaunay0d447522019-04-10 14:09:28 +020031
32config STM32MP1_DDR_TESTS
33 bool "STM32MP1 DDR driver : tests support"
34 depends on STM32MP1_DDR_INTERACTIVE
35 default y
36 help
37 activate test support for interactive support in
38 STM32MP1 DDR controller driver: command test
Patrick Delaunay187c41d2019-04-10 14:09:29 +020039
40config STM32MP1_DDR_TUNING
41 bool "STM32MP1 DDR driver : support of tuning"
42 depends on STM32MP1_DDR_INTERACTIVE
43 default y
44 help
45 activate tuning command in STM32MP1 DDR interactive mode
46 used for DDR tuning tools
47 - DQ Deskew algorithm
48 - DQS Trimming