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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 8f1ed2e4ed64959535ee61d396cb2a41fcb97d61 / . / arch / arm / dts / omap5.dtsi
blob: 2ac7f021c284ce65163e9b84074af0d2de39d668 [file] [log] [blame]
Tero Kristo8f1ed2e2020-06-16 11:03:09 +0300[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/omap.h>
12#include <dt-bindings/clock/omap5.h>
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x0>;
44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1500000 1250000
49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
55
56 /* cooling options */
57 #cooling-cells = <2>; /* min followed by max */
58 };
59 cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0x1>;
63
64 operating-points = <
65 /* kHz uV */
66 1000000 1060000
67 1500000 1250000
68 >;
69
70 clocks = <&dpll_mpu_ck>;
71 clock-names = "cpu";
72
73 clock-latency = <300000>; /* From omap-cpufreq driver */
74
75 /* cooling options */
76 #cooling-cells = <2>; /* min followed by max */
77 };
78 };
79
80 thermal-zones {
81 #include "omap4-cpu-thermal.dtsi"
82 #include "omap5-gpu-thermal.dtsi"
83 #include "omap5-core-thermal.dtsi"
84 };
85
86 timer {
87 compatible = "arm,armv7-timer";
88 /* PPI secure/nonsecure IRQ */
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
93 interrupt-parent = <&gic>;
94 };
95
96 pmu {
97 compatible = "arm,cortex-a15-pmu";
98 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 gic: interrupt-controller@48211000 {
103 compatible = "arm,cortex-a15-gic";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0 0x48211000 0 0x1000>,
107 <0 0x48212000 0 0x2000>,
108 <0 0x48214000 0 0x2000>,
109 <0 0x48216000 0 0x2000>;
110 interrupt-parent = <&gic>;
111 };
112
113 wakeupgen: interrupt-controller@48281000 {
114 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
115 interrupt-controller;
116 #interrupt-cells = <3>;
117 reg = <0 0x48281000 0 0x1000>;
118 interrupt-parent = <&gic>;
119 };
120
121 /*
122 * The soc node represents the soc top level view. It is used for IPs
123 * that are not memory mapped in the MPU view or for the MPU itself.
124 */
125 soc {
126 compatible = "ti,omap-infra";
127 mpu {
128 compatible = "ti,omap4-mpu";
129 ti,hwmods = "mpu";
130 sram = <&ocmcram>;
131 };
132 };
133
134 /*
135 * XXX: Use a flat representation of the OMAP3 interconnect.
136 * The real OMAP interconnect network is quite complex.
137 * Since it will not bring real advantage to represent that in DT for
138 * the moment, just use a fake OCP bus entry to represent the whole bus
139 * hierarchy.
140 */
141 ocp {
142 compatible = "ti,omap5-l3-noc", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0 0 0xc0000000>;
146 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
147 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
148 reg = <0 0x44000000 0 0x2000>,
149 <0 0x44800000 0 0x3000>,
150 <0 0x45000000 0 0x4000>;
151 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
153
154 l4_wkup: interconnect@4ae00000 {
155 };
156
157 l4_cfg: interconnect@4a000000 {
158 };
159
160 l4_per: interconnect@48000000 {
161 };
162
163 l4_abe: interconnect@40100000 {
164 };
165
166 ocmcram: sram@40300000 {
167 compatible = "mmio-sram";
168 reg = <0x40300000 0x20000>; /* 128k */
169 };
170
171 gpmc: gpmc@50000000 {
172 compatible = "ti,omap4430-gpmc";
173 reg = <0x50000000 0x1000>;
174 #address-cells = <2>;
175 #size-cells = <1>;
176 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
177 dmas = <&sdma 4>;
178 dma-names = "rxtx";
179 gpmc,num-cs = <8>;
180 gpmc,num-waitpins = <4>;
181 ti,hwmods = "gpmc";
182 clocks = <&l3_iclk_div>;
183 clock-names = "fck";
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 gpio-controller;
187 #gpio-cells = <2>;
188 };
189
190 target-module@55082000 {
191 compatible = "ti,sysc-omap2", "ti,sysc";
192 reg = <0x55082000 0x4>,
193 <0x55082010 0x4>,
194 <0x55082014 0x4>;
195 reg-names = "rev", "sysc", "syss";
196 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
197 <SYSC_IDLE_NO>,
198 <SYSC_IDLE_SMART>;
199 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
200 SYSC_OMAP2_SOFTRESET |
201 SYSC_OMAP2_AUTOIDLE)>;
202 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
203 clock-names = "fck";
204 resets = <&prm_core 2>;
205 reset-names = "rstctrl";
206 ranges = <0x0 0x55082000 0x100>;
207 #size-cells = <1>;
208 #address-cells = <1>;
209
210 mmu_ipu: mmu@0 {
211 compatible = "ti,omap4-iommu";
212 reg = <0x0 0x100>;
213 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
214 #iommu-cells = <0>;
215 ti,iommu-bus-err-back;
216 };
217 };
218
219 dmm@4e000000 {
220 compatible = "ti,omap5-dmm";
221 reg = <0x4e000000 0x800>;
222 interrupts = <0 113 0x4>;
223 ti,hwmods = "dmm";
224 };
225
226 emif1: emif@4c000000 {
227 compatible = "ti,emif-4d5";
228 ti,hwmods = "emif1";
229 ti,no-idle-on-init;
230 phy-type = <2>; /* DDR PHY type: Intelli PHY */
231 reg = <0x4c000000 0x400>;
232 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
233 hw-caps-read-idle-ctrl;
234 hw-caps-ll-interface;
235 hw-caps-temp-alert;
236 };
237
238 emif2: emif@4d000000 {
239 compatible = "ti,emif-4d5";
240 ti,hwmods = "emif2";
241 ti,no-idle-on-init;
242 phy-type = <2>; /* DDR PHY type: Intelli PHY */
243 reg = <0x4d000000 0x400>;
244 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
245 hw-caps-read-idle-ctrl;
246 hw-caps-ll-interface;
247 hw-caps-temp-alert;
248 };
249
250 bandgap: bandgap@4a0021e0 {
251 reg = <0x4a0021e0 0xc
252 0x4a00232c 0xc
253 0x4a002380 0x2c
254 0x4a0023C0 0x3c>;
255 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
256 compatible = "ti,omap5430-bandgap";
257
258 #thermal-sensor-cells = <1>;
259 };
260
261 /* OCP2SCP3 */
262 sata: sata@4a141100 {
263 compatible = "snps,dwc-ahci";
264 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
265 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
266 phys = <&sata_phy>;
267 phy-names = "sata-phy";
268 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
269 ti,hwmods = "sata";
270 ports-implemented = <0x1>;
271 };
272
273 target-module@56000000 {
274 compatible = "ti,sysc-omap4", "ti,sysc";
275 reg = <0x5600fe00 0x4>,
276 <0x5600fe10 0x4>;
277 reg-names = "rev", "sysc";
278 ti,sysc-midle = <SYSC_IDLE_FORCE>,
279 <SYSC_IDLE_NO>,
280 <SYSC_IDLE_SMART>;
281 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
282 <SYSC_IDLE_NO>,
283 <SYSC_IDLE_SMART>;
284 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
285 clock-names = "fck";
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges = <0 0x56000000 0x2000000>;
289
290 /*
291 * Closed source PowerVR driver, no child device
292 * binding or driver in mainline
293 */
294 };
295
296 target-module@58000000 {
297 compatible = "ti,sysc-omap2", "ti,sysc";
298 reg = <0x58000000 4>,
299 <0x58000014 4>;
300 reg-names = "rev", "syss";
301 ti,syss-mask = <1>;
302 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
303 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
304 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
305 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
306 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
307 #address-cells = <1>;
308 #size-cells = <1>;
309 ranges = <0 0x58000000 0x1000000>;
310
311 dss: dss@0 {
312 compatible = "ti,omap5-dss";
313 reg = <0 0x80>;
314 status = "disabled";
315 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
316 clock-names = "fck";
317 #address-cells = <1>;
318 #size-cells = <1>;
319 ranges = <0 0 0x1000000>;
320
321 target-module@1000 {
322 compatible = "ti,sysc-omap2", "ti,sysc";
323 reg = <0x1000 0x4>,
324 <0x1010 0x4>,
325 <0x1014 0x4>;
326 reg-names = "rev", "sysc", "syss";
327 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
328 <SYSC_IDLE_NO>,
329 <SYSC_IDLE_SMART>;
330 ti,sysc-midle = <SYSC_IDLE_FORCE>,
331 <SYSC_IDLE_NO>,
332 <SYSC_IDLE_SMART>;
333 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
334 SYSC_OMAP2_ENAWAKEUP |
335 SYSC_OMAP2_SOFTRESET |
336 SYSC_OMAP2_AUTOIDLE)>;
337 ti,syss-mask = <1>;
338 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
339 clock-names = "fck";
340 #address-cells = <1>;
341 #size-cells = <1>;
342 ranges = <0 0x1000 0x1000>;
343
344 dispc@0 {
345 compatible = "ti,omap5-dispc";
346 reg = <0 0x1000>;
347 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
349 clock-names = "fck";
350 };
351 };
352
353 target-module@2000 {
354 compatible = "ti,sysc-omap2", "ti,sysc";
355 reg = <0x2000 0x4>,
356 <0x2010 0x4>,
357 <0x2014 0x4>;
358 reg-names = "rev", "sysc", "syss";
359 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
360 <SYSC_IDLE_NO>,
361 <SYSC_IDLE_SMART>;
362 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
363 SYSC_OMAP2_AUTOIDLE)>;
364 ti,syss-mask = <1>;
365 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
366 clock-names = "fck";
367 #address-cells = <1>;
368 #size-cells = <1>;
369 ranges = <0 0x2000 0x1000>;
370
371 rfbi: encoder@0 {
372 compatible = "ti,omap5-rfbi";
373 reg = <0 0x100>;
374 status = "disabled";
375 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
376 clock-names = "fck", "ick";
377 };
378 };
379
380 target-module@5000 {
381 compatible = "ti,sysc-omap2", "ti,sysc";
382 reg = <0x5000 0x4>,
383 <0x5010 0x4>,
384 <0x5014 0x4>;
385 reg-names = "rev", "sysc", "syss";
386 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
387 <SYSC_IDLE_NO>,
388 <SYSC_IDLE_SMART>;
389 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
390 SYSC_OMAP2_ENAWAKEUP |
391 SYSC_OMAP2_SOFTRESET |
392 SYSC_OMAP2_AUTOIDLE)>;
393 ti,syss-mask = <1>;
394 #address-cells = <1>;
395 #size-cells = <1>;
396 ranges = <0 0x5000 0x1000>;
397
398 dsi1: encoder@0 {
399 compatible = "ti,omap5-dsi";
400 reg = <0 0x200>,
401 <0x200 0x40>,
402 <0x300 0x40>;
403 reg-names = "proto", "phy", "pll";
404 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
405 status = "disabled";
406 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
407 clock-names = "fck";
408 };
409 };
410
411 target-module@9000 {
412 compatible = "ti,sysc-omap2", "ti,sysc";
413 reg = <0x9000 0x4>,
414 <0x9010 0x4>,
415 <0x9014 0x4>;
416 reg-names = "rev", "sysc", "syss";
417 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
418 <SYSC_IDLE_NO>,
419 <SYSC_IDLE_SMART>;
420 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
421 SYSC_OMAP2_ENAWAKEUP |
422 SYSC_OMAP2_SOFTRESET |
423 SYSC_OMAP2_AUTOIDLE)>;
424 ti,syss-mask = <1>;
425 #address-cells = <1>;
426 #size-cells = <1>;
427 ranges = <0 0x9000 0x1000>;
428
429 dsi2: encoder@0 {
430 compatible = "ti,omap5-dsi";
431 reg = <0 0x200>,
432 <0x200 0x40>,
433 <0x300 0x40>;
434 reg-names = "proto", "phy", "pll";
435 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
436 status = "disabled";
437 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
438 clock-names = "fck";
439 };
440 };
441
442 target-module@40000 {
443 compatible = "ti,sysc-omap4", "ti,sysc";
444 reg = <0x40000 0x4>,
445 <0x40010 0x4>;
446 reg-names = "rev", "sysc";
447 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
448 <SYSC_IDLE_NO>,
449 <SYSC_IDLE_SMART>,
450 <SYSC_IDLE_SMART_WKUP>;
451 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
452 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
453 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
454 clock-names = "fck", "dss_clk";
455 #address-cells = <1>;
456 #size-cells = <1>;
457 ranges = <0 0x40000 0x40000>;
458
459 hdmi: encoder@0 {
460 compatible = "ti,omap5-hdmi";
461 reg = <0 0x200>,
462 <0x200 0x80>,
463 <0x300 0x80>,
464 <0x20000 0x19000>;
465 reg-names = "wp", "pll", "phy", "core";
466 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
467 status = "disabled";
468 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
469 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
470 clock-names = "fck", "sys_clk";
471 dmas = <&sdma 76>;
472 dma-names = "audio_tx";
473 };
474 };
475 };
476 };
477
478 abb_mpu: regulator-abb-mpu {
479 compatible = "ti,abb-v2";
480 regulator-name = "abb_mpu";
481 #address-cells = <0>;
482 #size-cells = <0>;
483 clocks = <&sys_clkin>;
484 ti,settling-time = <50>;
485 ti,clock-cycles = <16>;
486
487 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
488 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
489 reg-names = "base-address", "int-address",
490 "efuse-address", "ldo-address";
491 ti,tranxdone-status-mask = <0x80>;
492 /* LDOVBBMPU_MUX_CTRL */
493 ti,ldovbb-override-mask = <0x400>;
494 /* LDOVBBMPU_VSET_OUT */
495 ti,ldovbb-vset-mask = <0x1F>;
496
497 /*
498 * NOTE: only FBB mode used but actual vset will
499 * determine final biasing
500 */
501 ti,abb_info = <
502 /*uV ABB efuse rbb_m fbb_m vset_m*/
503 1060000 0 0x0 0 0x02000000 0x01F00000
504 1250000 0 0x4 0 0x02000000 0x01F00000
505 >;
506 };
507
508 abb_mm: regulator-abb-mm {
509 compatible = "ti,abb-v2";
510 regulator-name = "abb_mm";
511 #address-cells = <0>;
512 #size-cells = <0>;
513 clocks = <&sys_clkin>;
514 ti,settling-time = <50>;
515 ti,clock-cycles = <16>;
516
517 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
518 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
519 reg-names = "base-address", "int-address",
520 "efuse-address", "ldo-address";
521 ti,tranxdone-status-mask = <0x80000000>;
522 /* LDOVBBMM_MUX_CTRL */
523 ti,ldovbb-override-mask = <0x400>;
524 /* LDOVBBMM_VSET_OUT */
525 ti,ldovbb-vset-mask = <0x1F>;
526
527 /*
528 * NOTE: only FBB mode used but actual vset will
529 * determine final biasing
530 */
531 ti,abb_info = <
532 /*uV ABB efuse rbb_m fbb_m vset_m*/
533 1025000 0 0x0 0 0x02000000 0x01F00000
534 1120000 0 0x4 0 0x02000000 0x01F00000
535 >;
536 };
537 };
538};
539
540&cpu_thermal {
541 polling-delay = <500>; /* milliseconds */
542 coefficients = <65 (-1791)>;
543};
544
545#include "omap5-l4.dtsi"
546#include "omap54xx-clocks.dtsi"
547
548&gpu_thermal {
549 coefficients = <117 (-2992)>;
550};
551
552&core_thermal {
553 coefficients = <0 2000>;
554};
555
556#include "omap5-l4-abe.dtsi"
557#include "omap54xx-clocks.dtsi"
558
559&prm {
560 prm_dsp: prm@400 {
561 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
562 reg = <0x400 0x100>;
563 #reset-cells = <1>;
564 };
565
566 prm_core: prm@700 {
567 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
568 reg = <0x700 0x100>;
569 #reset-cells = <1>;
570 };
571
572 prm_iva: prm@1200 {
573 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
574 reg = <0x1200 0x100>;
575 #reset-cells = <1>;
576 };
577
578 prm_device: prm@1c00 {
579 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
580 reg = <0x1c00 0x100>;
581 #reset-cells = <1>;
582 };
583};