blob: e32e7827871ed5fa1225d7901422e516a1d2fb0c [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Alexey Brodkin67482f52016-11-25 16:23:43 +03002/*
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03003 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Alexey Brodkin67482f52016-11-25 16:23:43 +03005 */
6
7#include <common.h>
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03008#include <config.h>
Simon Glass9edefc22019-11-14 12:57:37 -07009#include <cpu_func.h>
Simon Glass168068f2019-08-01 09:46:47 -060010#include <env.h>
Simon Glass52559322019-11-14 12:57:46 -070011#include <init.h>
Simon Glass36bf4462019-11-14 12:57:42 -070012#include <irq_func.h>
Simon Glass90526e92020-05-10 11:39:56 -060013#include <asm/cache.h>
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +030014#include <linux/printk.h>
15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <asm/arcregs.h>
18#include <fdt_support.h>
Alexey Brodkin67482f52016-11-25 16:23:43 +030019#include <dwmmc.h>
20#include <malloc.h>
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +030021#include <usb.h>
22
23#include "clk-lib.h"
24#include "env-lib.h"
Alexey Brodkin67482f52016-11-25 16:23:43 +030025
26DECLARE_GLOBAL_DATA_PTR;
27
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +030028#define ALL_CPU_MASK GENMASK(NR_CPUS - 1, 0)
29#define MASTER_CPU_ID 0
30#define APERTURE_SHIFT 28
31#define NO_CCM 0x10
32#define SLAVE_CPU_READY 0x12345678
33#define BOOTSTAGE_1 1 /* after SP, FP setup, before HW init */
34#define BOOTSTAGE_2 2 /* after HW init, before self halt */
35#define BOOTSTAGE_3 3 /* after self halt */
36#define BOOTSTAGE_4 4 /* before app launch */
37#define BOOTSTAGE_5 5 /* after app launch, unreachable */
Alexey Brodkin67482f52016-11-25 16:23:43 +030038
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +030039#define RESET_VECTOR_ADDR 0x0
40
41#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
42#define CREG_CPU_START (CREG_BASE + 0x400)
43#define CREG_CPU_START_MASK 0xF
Eugeniy Paltsev4b4da7f2020-01-16 19:22:32 +030044#define CREG_CPU_START_POL BIT(4)
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +030045
Eugeniy Paltseva8eb9b22020-04-29 21:36:44 +030046#define CREG_CORE_BOOT_IMAGE GENMASK(5, 4)
47
Eugeniy Paltsev25998ae2020-04-24 23:11:10 +030048#define CREG_CPU_0_ENTRY (CREG_BASE + 0x404)
49
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +030050#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
51#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
52#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
53
54/* Uncached access macros */
55#define arc_read_uncached_32(ptr) \
56({ \
57 unsigned int __ret; \
58 __asm__ __volatile__( \
59 " ld.di %0, [%1] \n" \
60 : "=r"(__ret) \
61 : "r"(ptr)); \
62 __ret; \
63})
64
65#define arc_write_uncached_32(ptr, data)\
66({ \
67 __asm__ __volatile__( \
68 " st.di %0, [%1] \n" \
69 : \
70 : "r"(data), "r"(ptr)); \
71})
72
73struct hsdk_env_core_ctl {
74 u32_env entry[NR_CPUS];
75 u32_env iccm[NR_CPUS];
76 u32_env dccm[NR_CPUS];
77};
78
79struct hsdk_env_common_ctl {
80 bool halt_on_boot;
81 u32_env core_mask;
82 u32_env cpu_freq;
83 u32_env axi_freq;
84 u32_env tun_freq;
85 u32_env nvlim;
86 u32_env icache;
87 u32_env dcache;
Eugeniy Paltsev6917a9d2020-03-23 21:50:03 +030088 u32_env csm_location;
Eugeniy Paltsev1d897d12020-03-23 20:46:35 +030089 u32_env l2_cache;
Eugeniy Paltsev32ac4ee2020-03-25 12:35:49 +030090 u32_env haps_apb;
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +030091};
92
93/*
94 * Uncached cross-cpu structure. All CPUs must access to this structure fields
95 * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which
96 * implement ld.di / st.di instructions). Simultaneous cached and uncached
97 * access to this area will lead to data loss.
98 * We flush all data caches in board_early_init_r() as we don't want to have
99 * any dirty line in L1d$ or SL$ in this area.
100 */
101struct hsdk_cross_cpu {
102 /* slave CPU ready flag */
103 u32 ready_flag;
104 /* address of the area, which can be used for stack by slave CPU */
105 u32 stack_ptr;
106 /* slave CPU status - bootstage number */
107 s32 status[NR_CPUS];
108
109 /*
110 * Slave CPU data - it is copy of corresponding fields in
111 * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are
112 * required for slave CPUs initialization.
113 * This fields can be populated by copying from hsdk_env_core_ctl
114 * and hsdk_env_common_ctl structures with sync_cross_cpu_data()
115 * function.
116 */
117 u32 entry[NR_CPUS];
118 u32 iccm[NR_CPUS];
119 u32 dccm[NR_CPUS];
120
121 u32 core_mask;
122 u32 icache;
123 u32 dcache;
124
125 u8 cache_padding[ARCH_DMA_MINALIGN];
126} __aligned(ARCH_DMA_MINALIGN);
127
128/* Place for slave CPUs temporary stack */
129static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN);
130
131static struct hsdk_env_common_ctl env_common = {};
132static struct hsdk_env_core_ctl env_core = {};
133static struct hsdk_cross_cpu cross_cpu_data;
134
135static const struct env_map_common env_map_common[] = {
136 { "core_mask", ENV_HEX, true, 0x1, 0xF, &env_common.core_mask },
137 { "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim },
138 { "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache },
139 { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
Eugeniy Paltsev1d897d12020-03-23 20:46:35 +0300140#if defined(CONFIG_BOARD_HSDK_4XD)
141 { "l2_cache_ena", ENV_HEX, true, 0, 1, &env_common.l2_cache },
Eugeniy Paltsev6917a9d2020-03-23 21:50:03 +0300142 { "csm_location", ENV_HEX, true, 0, NO_CCM, &env_common.csm_location },
Eugeniy Paltsev32ac4ee2020-03-25 12:35:49 +0300143 { "haps_apb_location", ENV_HEX, true, 0, 1, &env_common.haps_apb },
Eugeniy Paltsev1d897d12020-03-23 20:46:35 +0300144#endif /* CONFIG_BOARD_HSDK_4XD */
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300145 {}
146};
147
148static const struct env_map_common env_map_clock[] = {
149 { "cpu_freq", ENV_DEC, false, 100, 1000, &env_common.cpu_freq },
150 { "axi_freq", ENV_DEC, false, 200, 800, &env_common.axi_freq },
151 { "tun_freq", ENV_DEC, false, 0, 150, &env_common.tun_freq },
152 {}
153};
154
155static const struct env_map_percpu env_map_core[] = {
156 { "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm },
157 { "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm },
158 {}
159};
160
161static const struct env_map_common env_map_mask[] = {
162 { "core_mask", ENV_HEX, false, 0x1, 0xF, &env_common.core_mask },
163 {}
164};
165
166static const struct env_map_percpu env_map_go[] = {
167 { "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry },
168 {}
169};
170
Eugeniy Paltsevf0f84ef2020-04-22 00:33:40 +0300171enum board_type {
172 T_BOARD_NONE,
173 T_BOARD_HSDK,
174 T_BOARD_HSDK_4XD
175};
176
177static inline enum board_type get_board_type_runtime(void)
178{
179 u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF;
180
181 if (arc_id == 0x52)
182 return T_BOARD_HSDK;
183 else if (arc_id == 0x54)
184 return T_BOARD_HSDK_4XD;
185 else
186 return T_BOARD_NONE;
187}
188
189static inline enum board_type get_board_type_config(void)
190{
191 if (IS_ENABLED(CONFIG_BOARD_HSDK))
192 return T_BOARD_HSDK;
193 else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD))
194 return T_BOARD_HSDK_4XD;
195 else
196 return T_BOARD_NONE;
197}
198
199static bool is_board_match_runtime(enum board_type type_req)
200{
201 return get_board_type_runtime() == type_req;
202}
203
Eugeniy Paltsev1d897d12020-03-23 20:46:35 +0300204static bool is_board_match_config(enum board_type type_req)
205{
206 return get_board_type_config() == type_req;
207}
208
Eugeniy Paltsevf0f84ef2020-04-22 00:33:40 +0300209static const char * board_name(enum board_type type)
210{
211 switch (type) {
212 case T_BOARD_HSDK:
213 return "ARC HS Development Kit";
214 case T_BOARD_HSDK_4XD:
215 return "ARC HS4x/HS4xD Development Kit";
216 default:
217 return "?";
218 }
219}
220
221static bool board_mismatch(void)
222{
223 return get_board_type_config() != get_board_type_runtime();
224}
225
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300226static void sync_cross_cpu_data(void)
Alexey Brodkin67482f52016-11-25 16:23:43 +0300227{
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300228 u32 value;
Alexey Brodkin67482f52016-11-25 16:23:43 +0300229
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300230 for (u32 i = 0; i < NR_CPUS; i++) {
231 value = env_core.entry[i].val;
232 arc_write_uncached_32(&cross_cpu_data.entry[i], value);
233 }
234
235 for (u32 i = 0; i < NR_CPUS; i++) {
236 value = env_core.iccm[i].val;
237 arc_write_uncached_32(&cross_cpu_data.iccm[i], value);
238 }
239
240 for (u32 i = 0; i < NR_CPUS; i++) {
241 value = env_core.dccm[i].val;
242 arc_write_uncached_32(&cross_cpu_data.dccm[i], value);
243 }
244
245 value = env_common.core_mask.val;
246 arc_write_uncached_32(&cross_cpu_data.core_mask, value);
247
248 value = env_common.icache.val;
249 arc_write_uncached_32(&cross_cpu_data.icache, value);
250
251 value = env_common.dcache.val;
252 arc_write_uncached_32(&cross_cpu_data.dcache, value);
253}
254
255/* Can be used only on master CPU */
256static bool is_cpu_used(u32 cpu_id)
257{
258 return !!(env_common.core_mask.val & BIT(cpu_id));
259}
260
261/* TODO: add ICCM BCR and DCCM BCR runtime check */
262static void init_slave_cpu_func(u32 core)
263{
264 u32 val;
265
266 /* Remap ICCM to another memory region if it exists */
267 val = arc_read_uncached_32(&cross_cpu_data.iccm[core]);
268 if (val != NO_CCM)
269 write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT);
270
271 /* Remap DCCM to another memory region if it exists */
272 val = arc_read_uncached_32(&cross_cpu_data.dccm[core]);
273 if (val != NO_CCM)
274 write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT);
275
276 if (arc_read_uncached_32(&cross_cpu_data.icache))
277 icache_enable();
278 else
279 icache_disable();
280
281 if (arc_read_uncached_32(&cross_cpu_data.dcache))
282 dcache_enable();
283 else
284 dcache_disable();
285}
286
287static void init_cluster_nvlim(void)
288{
289 u32 val = env_common.nvlim.val << APERTURE_SHIFT;
290
291 flush_dcache_all();
292 write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
Eugeniy Paltsevf0f84ef2020-04-22 00:33:40 +0300293 /* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */
294 if (is_board_match_runtime(T_BOARD_HSDK))
295 write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300296 flush_n_invalidate_dcache_all();
297}
298
Eugeniy Paltsev1d897d12020-03-23 20:46:35 +0300299static void init_cluster_slc(void)
300{
301 /* ARC HS38 doesn't support SLC disabling */
302 if (!is_board_match_config(T_BOARD_HSDK_4XD))
303 return;
304
305 if (env_common.l2_cache.val)
306 slc_enable();
307 else
308 slc_disable();
309}
310
Eugeniy Paltsev6917a9d2020-03-23 21:50:03 +0300311#define CREG_CSM_BASE (CREG_BASE + 0x210)
312
313static void init_cluster_csm(void)
314{
315 /* ARC HS38 in HSDK SoC doesn't include CSM */
316 if (!is_board_match_config(T_BOARD_HSDK_4XD))
317 return;
318
319 if (env_common.csm_location.val == NO_CCM) {
320 write_aux_reg(ARC_AUX_CSM_ENABLE, 0);
321 } else {
322 /*
323 * CSM base address is 256kByte aligned but we allow to map
324 * CSM only to aperture start (256MByte aligned)
325 * The field in CREG_CSM_BASE is in 17:2 bits itself so we need
326 * to shift it.
327 */
328 u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2;
329
330 write_aux_reg(ARC_AUX_CSM_ENABLE, 1);
331 writel(csm_base, (void __iomem *)CREG_CSM_BASE);
332 }
333}
334
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300335static void init_master_icache(void)
336{
337 if (icache_status()) {
338 /* I$ is enabled - we need to disable it */
339 if (!env_common.icache.val)
340 icache_disable();
341 } else {
342 /* I$ is disabled - we need to enable it */
343 if (env_common.icache.val) {
344 icache_enable();
345
346 /* invalidate I$ right after enable */
347 invalidate_icache_all();
348 }
349 }
350}
351
352static void init_master_dcache(void)
353{
354 if (dcache_status()) {
355 /* D$ is enabled - we need to disable it */
356 if (!env_common.dcache.val)
357 dcache_disable();
358 } else {
359 /* D$ is disabled - we need to enable it */
360 if (env_common.dcache.val)
361 dcache_enable();
362
363 /* TODO: probably we need ti invalidate D$ right after enable */
364 }
365}
366
367static int cleanup_before_go(void)
368{
369 disable_interrupts();
370 sync_n_cleanup_cache_all();
Alexey Brodkin67482f52016-11-25 16:23:43 +0300371
372 return 0;
373}
374
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300375void slave_cpu_set_boot_addr(u32 addr)
376{
377 /* All cores have reset vector pointing to 0 */
378 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
379
380 /* Make sure other cores see written value in memory */
381 sync_n_cleanup_cache_all();
382}
383
384static inline void halt_this_cpu(void)
385{
386 __builtin_arc_flag(1);
387}
388
Eugeniy Paltsev4b4da7f2020-01-16 19:22:32 +0300389static u32 get_masked_cpu_ctart_reg(void)
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300390{
391 int cmd = readl((void __iomem *)CREG_CPU_START);
392
Eugeniy Paltsev4b4da7f2020-01-16 19:22:32 +0300393 /*
394 * Quirk for HSDK-4xD - due to HW issues HSDK can use any pulse polarity
395 * and HSDK-4xD require active low polarity of cpu_start pulse.
396 */
397 cmd &= ~CREG_CPU_START_POL;
398
399 cmd &= ~CREG_CPU_START_MASK;
400
401 return cmd;
402}
403
404static void smp_kick_cpu_x(u32 cpu_id)
405{
406 int cmd;
407
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300408 if (cpu_id > NR_CPUS)
409 return;
410
Eugeniy Paltsev4b4da7f2020-01-16 19:22:32 +0300411 cmd = get_masked_cpu_ctart_reg();
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300412 cmd |= (1 << cpu_id);
413 writel(cmd, (void __iomem *)CREG_CPU_START);
414}
415
416static u32 prepare_cpu_ctart_reg(void)
417{
Eugeniy Paltsev4b4da7f2020-01-16 19:22:32 +0300418 return get_masked_cpu_ctart_reg() | env_common.core_mask.val;
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300419}
420
421/* slave CPU entry for configuration */
422__attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void)
423{
424 __asm__ __volatile__(
425 "ld.di r8, [%0]\n"
426 "mov %%sp, r8\n"
427 "mov %%fp, %%sp\n"
428 : /* no output */
429 : "r" (&cross_cpu_data.stack_ptr));
430
431 invalidate_icache_all();
432
433 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1);
434 init_slave_cpu_func(CPU_ID_GET());
435
436 arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY);
437 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2);
438
439 /* Halt the processor until the master kick us again */
440 halt_this_cpu();
441
442 /*
443 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
444 * cores but we leave them for gebug purposes.
445 */
446 __builtin_arc_nop();
447 __builtin_arc_nop();
448 __builtin_arc_nop();
449
450 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3);
451
452 /* get the updated entry - invalidate i$ */
453 invalidate_icache_all();
454
455 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4);
456
457 /* Run our program */
458 ((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))();
459
460 /* This bootstage is unreachable as we don't return from app we launch */
461 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5);
462
463 /* Something went terribly wrong */
464 while (true)
465 halt_this_cpu();
466}
467
468static void clear_cross_cpu_data(void)
469{
470 arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
471 arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0);
472
473 for (u32 i = 0; i < NR_CPUS; i++)
474 arc_write_uncached_32(&cross_cpu_data.status[i], 0);
475}
476
477static noinline void do_init_slave_cpu(u32 cpu_id)
478{
479 /* attempts number for check clave CPU ready_flag */
480 u32 attempts = 100;
481 u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id));
482
483 if (cpu_id >= NR_CPUS)
484 return;
485
486 arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
487
488 /* Use global unique place for each slave cpu stack */
489 arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr);
490
491 debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack);
492 debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr);
493 slave_cpu_set_boot_addr((u32)hsdk_core_init_f);
494
495 smp_kick_cpu_x(cpu_id);
496
497 debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id,
498 arc_read_uncached_32(&cross_cpu_data.ready_flag));
499
500 while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--)
501 mdelay(10);
502
503 /* Just to be sure that slave cpu is halted after it set ready_flag */
504 mdelay(20);
505
506 /*
507 * Only print error here if we reach timeout as there is no option to
508 * halt slave cpu (or check that slave cpu is halted)
509 */
510 if (!attempts)
511 pr_err("CPU %u is not responding after init!\n", cpu_id);
512
513 /* Check current stage of slave cpu */
514 if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2)
515 pr_err("CPU %u status is unexpected: %d\n", cpu_id,
516 arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
517
518 debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id,
519 arc_read_uncached_32(&cross_cpu_data.ready_flag));
520 debug("CPU %u: status: %d [after timeout]\n", cpu_id,
521 arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
522}
523
524static void do_init_slave_cpus(void)
525{
526 clear_cross_cpu_data();
527 sync_cross_cpu_data();
528
529 debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data);
530
531 for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++)
532 if (is_cpu_used(i))
533 do_init_slave_cpu(i);
534}
535
536static void do_init_master_cpu(void)
537{
538 /*
539 * Setup master caches even if master isn't used as we want to use
540 * same cache configuration on all running CPUs
541 */
542 init_master_icache();
543 init_master_dcache();
544}
545
546enum hsdk_axi_masters {
547 M_HS_CORE = 0,
548 M_HS_RTT,
549 M_AXI_TUN,
550 M_HDMI_VIDEO,
551 M_HDMI_AUDIO,
552 M_USB_HOST,
553 M_ETHERNET,
554 M_SDIO,
555 M_GPU,
556 M_DMAC_0,
557 M_DMAC_1,
558 M_DVFS
559};
560
561#define UPDATE_VAL 1
562
563/*
564 * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
565 * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
566 * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
567 * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
568 * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
569 * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
570 * 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
571 * 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
572 * 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
573 * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
574 * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
575 * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
576 * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
577 *
578 * Please read ARC HS Development IC Specification, section 17.2 for more
579 * information about apertures configuration.
580 * NOTE: we intentionally modify default settings in U-boot. Default settings
581 * are specified in "Table 111 CREG Address Decoder register reset values".
582 */
583
584#define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m)))
585#define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004))
586#define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008))
587#define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C))
588#define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014))
589
590#define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
591
592#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
593#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
594
595void init_memory_bridge(void)
596{
597 u32 reg;
598
599 /*
600 * M_HS_CORE has one unic register - BOOT.
601 * We need to clean boot mirror (BOOT[1:0]) bits in them.
602 */
603 reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
604 writel(reg, CREG_AXI_M_HS_CORE_BOOT);
605 writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
606 writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
607 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
608 writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
609 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
610
611 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
612 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
613 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
614 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
615 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
616
617 writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
618 writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
620 writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
622
623 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
624 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
625 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
626 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
627 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
628
629 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
630 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
631 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
632 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
633 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
634
635 writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
636 writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
637 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
638 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
639 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
640
641 writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
642 writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
643 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
644 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
645 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
646
647 writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
648 writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
649 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
650 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
651 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
652
653 writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
654 writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
655 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
656 writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
657 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
658
659 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
660 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
661 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
662 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
663 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
664
665 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
666 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
667 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
668 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
669 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
670
671 writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
672 writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
673 writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
674 writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
675 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
676
677 writel(0x00000000, CREG_PAE);
678 writel(UPDATE_VAL, CREG_PAE_UPDT);
679}
680
Eugeniy Paltsev32ac4ee2020-03-25 12:35:49 +0300681/*
682 * For HSDK-4xD we do additional AXI bridge tweaking in hsdk_init command:
683 * - we shrink IOC region.
684 * - we configure HS CORE SLV1 aperture depending on haps_apb_location
685 * environment variable.
686 *
687 * As we've already configured AXI bridge in init_memory_bridge we don't
688 * do full configuration here but reconfigure changed part.
689 *
690 * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
691 * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210 [haps_apb_location = 0]
692 * 0 HS (CBU) 0x11111111 0x61111111 0xFEDCBA98 0x06543210 [haps_apb_location = 1]
693 * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
694 * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
695 * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
696 * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
697 * 5 USB-HOST 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
698 * 6 ETHERNET 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
699 * 7 SDIO 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
700 * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
701 * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
702 * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
703 * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
704 */
705void tweak_memory_bridge_cfg(void)
706{
707 /*
708 * Only HSDK-4xD requre additional AXI bridge tweaking depending on
709 * haps_apb_location environment variable
710 */
711 if (!is_board_match_config(T_BOARD_HSDK_4XD))
712 return;
713
714 if (env_common.haps_apb.val) {
715 writel(0x61111111, CREG_AXI_M_SLV1(M_HS_CORE));
716 writel(0x06543210, CREG_AXI_M_OFT1(M_HS_CORE));
717 } else {
718 writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
719 writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
720 }
721 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
722
723 writel(0x77779999, CREG_AXI_M_SLV1(M_USB_HOST));
724 writel(0x7654BA98, CREG_AXI_M_OFT1(M_USB_HOST));
725 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
726
727 writel(0x77779999, CREG_AXI_M_SLV1(M_ETHERNET));;
728 writel(0x7654BA98, CREG_AXI_M_OFT1(M_ETHERNET));
729 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
730
731 writel(0x77779999, CREG_AXI_M_SLV1(M_SDIO));
732 writel(0x7654BA98, CREG_AXI_M_OFT1(M_SDIO));
733 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
734}
735
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300736static void setup_clocks(void)
737{
738 ulong rate;
739
740 /* Setup CPU clock */
741 if (env_common.cpu_freq.set) {
742 rate = env_common.cpu_freq.val;
743 soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
744 }
745
746 /* Setup TUN clock */
747 if (env_common.tun_freq.set) {
748 rate = env_common.tun_freq.val;
749 if (rate)
750 soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
751 else
752 soc_clk_ctl("tun-clk", NULL, CLK_OFF);
753 }
754
755 if (env_common.axi_freq.set) {
756 rate = env_common.axi_freq.val;
757 soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ);
758 }
759}
760
761static void do_init_cluster(void)
762{
763 /*
764 * A multi-core ARC HS configuration always includes only one
765 * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the
766 * cores.
767 */
768 init_cluster_nvlim();
Eugeniy Paltsev6917a9d2020-03-23 21:50:03 +0300769 init_cluster_csm();
Eugeniy Paltsev1d897d12020-03-23 20:46:35 +0300770 init_cluster_slc();
Eugeniy Paltsev32ac4ee2020-03-25 12:35:49 +0300771 tweak_memory_bridge_cfg();
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300772}
773
774static int check_master_cpu_id(void)
775{
776 if (CPU_ID_GET() == MASTER_CPU_ID)
777 return 0;
778
779 pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET());
780
781 return -ENOENT;
782}
783
784static noinline int prepare_cpus(void)
785{
786 int ret;
787
788 ret = check_master_cpu_id();
789 if (ret)
790 return ret;
791
792 ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used);
793 if (ret)
794 return ret;
795
796 printf("CPU start mask is %#x\n", env_common.core_mask.val);
797
798 do_init_slave_cpus();
799 do_init_master_cpu();
800 do_init_cluster();
801
802 return 0;
803}
804
805static int hsdk_go_run(u32 cpu_start_reg)
806{
807 /* Cleanup caches, disable interrupts */
808 cleanup_before_go();
809
810 if (env_common.halt_on_boot)
811 halt_this_cpu();
812
813 /*
814 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
815 * cores but we leave them for gebug purposes.
816 */
817 __builtin_arc_nop();
818 __builtin_arc_nop();
819 __builtin_arc_nop();
820
821 /* Kick chosen slave CPUs */
822 writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
823
824 if (is_cpu_used(MASTER_CPU_ID))
825 ((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))();
826 else
827 halt_this_cpu();
828
829 pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET());
830
831 /*
832 * We will never return after executing our program if master cpu used
833 * otherwise halt master cpu manually.
834 */
835 while (true)
836 halt_this_cpu();
837
838 return 0;
839}
840
841int board_prep_linux(bootm_headers_t *images)
842{
843 int ret, ofst;
844 char mask[15];
845
846 ret = envs_read_validate_common(env_map_mask);
847 if (ret)
848 return ret;
849
850 /* Rollback to default values */
851 if (!env_common.core_mask.set) {
852 env_common.core_mask.val = ALL_CPU_MASK;
853 env_common.core_mask.set = true;
854 }
855
856 printf("CPU start mask is %#x\n", env_common.core_mask.val);
857
858 if (!is_cpu_used(MASTER_CPU_ID))
859 pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n");
860
861 /*
862 * If we want to launch linux on all CPUs we don't need to patch
863 * linux DTB as it is default configuration
864 */
865 if (env_common.core_mask.val == ALL_CPU_MASK)
866 return 0;
867
868 if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
869 pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
870 return 0;
871 }
872
873 /* patch '/possible-cpus' property according to cpu mask */
874 ofst = fdt_path_offset(images->ft_addr, "/");
875 sprintf(mask, "%s%s%s%s",
876 is_cpu_used(0) ? "0," : "",
877 is_cpu_used(1) ? "1," : "",
878 is_cpu_used(2) ? "2," : "",
879 is_cpu_used(3) ? "3," : "");
880 ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask);
881 /*
882 * If we failed to patch '/possible-cpus' property we don't need break
883 * linux loading process: kernel will handle it but linux will print
884 * warning like "Timeout: CPU1 FAILED to comeup !!!".
885 * So warn here about error, but return 0 like no error had occurred.
886 */
887 if (ret)
888 pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n",
889 ret);
890
891 return 0;
892}
893
894void board_jump_and_run(ulong entry, int zero, int arch, uint params)
895{
896 void (*kernel_entry)(int zero, int arch, uint params);
897 u32 cpu_start_reg;
898
899 kernel_entry = (void (*)(int, int, uint))entry;
900
901 /* Prepare CREG_CPU_START for kicking chosen CPUs */
902 cpu_start_reg = prepare_cpu_ctart_reg();
903
904 /* In case of run without hsdk_init */
905 slave_cpu_set_boot_addr(entry);
906
907 /* In case of run with hsdk_init */
908 for (u32 i = 0; i < NR_CPUS; i++) {
909 env_core.entry[i].val = entry;
910 env_core.entry[i].set = true;
911 }
912 /* sync cross_cpu struct as we updated core-entry variables */
913 sync_cross_cpu_data();
914
915 /* Kick chosen slave CPUs */
916 writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
917
918 if (is_cpu_used(0))
919 kernel_entry(zero, arch, params);
920}
921
922static int hsdk_go_prepare_and_run(void)
923{
924 /* Prepare CREG_CPU_START for kicking chosen CPUs */
925 u32 reg = prepare_cpu_ctart_reg();
926
927 if (env_common.halt_on_boot)
928 printf("CPU will halt before application start, start application with debugger.\n");
929
930 return hsdk_go_run(reg);
931}
932
933static int do_hsdk_go(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
934{
935 int ret;
936
Eugeniy Paltsevf0f84ef2020-04-22 00:33:40 +0300937 if (board_mismatch()) {
938 printf("ERR: U-boot is not configured for this board!\n");
939 return CMD_RET_FAILURE;
940 }
941
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300942 /*
943 * Check for 'halt' parameter. 'halt' = enter halt-mode just before
944 * starting the application; can be used for debug.
945 */
946 if (argc > 1) {
947 env_common.halt_on_boot = !strcmp(argv[1], "halt");
948 if (!env_common.halt_on_boot) {
949 pr_err("Unrecognised parameter: \'%s\'\n", argv[1]);
950 return CMD_RET_FAILURE;
951 }
952 }
953
954 ret = check_master_cpu_id();
955 if (ret)
956 return ret;
957
958 ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used);
959 if (ret)
960 return ret;
961
962 /* sync cross_cpu struct as we updated core-entry variables */
963 sync_cross_cpu_data();
964
965 ret = hsdk_go_prepare_and_run();
966
967 return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
968}
969
970U_BOOT_CMD(
971 hsdk_go, 3, 0, do_hsdk_go,
972 "Synopsys HSDK specific command",
973 " - Boot stand-alone application on HSDK\n"
974 "hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
975);
976
Eugeniy Paltsev25998ae2020-04-24 23:11:10 +0300977/*
978 * We may simply use static variable here to store init status, but we also want
979 * to avoid the situation when we reload U-boot via MDB after previous
980 * init is done but HW reset (board reset) isn't done. So let's store the
981 * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
982 * survive after U-boot is reloaded via MDB.
983 */
984#define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY)
985/* must be equal to INIT_MARKER_REGISTER reset value */
986#define INIT_MARKER_PENDING 0
987
988static bool init_marker_get(void)
989{
990 return readl(INIT_MARKER_REGISTER) != INIT_MARKER_PENDING;
991}
992
993static void init_mark_done(void)
994{
995 writel(~INIT_MARKER_PENDING, INIT_MARKER_REGISTER);
996}
997
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +0300998static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
999{
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001000 int ret;
1001
Eugeniy Paltsevf0f84ef2020-04-22 00:33:40 +03001002 if (board_mismatch()) {
1003 printf("ERR: U-boot is not configured for this board!\n");
1004 return CMD_RET_FAILURE;
1005 }
1006
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001007 /* hsdk_init can be run only once */
Eugeniy Paltsev25998ae2020-04-24 23:11:10 +03001008 if (init_marker_get()) {
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001009 printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
1010 return CMD_RET_FAILURE;
1011 }
1012
1013 ret = prepare_cpus();
1014 if (!ret)
Eugeniy Paltsev25998ae2020-04-24 23:11:10 +03001015 init_mark_done();
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001016
1017 return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
1018}
1019
1020U_BOOT_CMD(
1021 hsdk_init, 1, 0, do_hsdk_init,
1022 "Synopsys HSDK specific command",
1023 "- Init HSDK HW\n"
1024);
1025
1026static int do_hsdk_clock_set(cmd_tbl_t *cmdtp, int flag, int argc,
1027 char *const argv[])
1028{
1029 int ret = 0;
1030
1031 /* Strip off leading subcommand argument */
1032 argc--;
1033 argv++;
1034
1035 envs_cleanup_common(env_map_clock);
1036
1037 if (!argc) {
1038 printf("Set clocks to values specified in environment\n");
1039 ret = envs_read_common(env_map_clock);
1040 } else {
1041 printf("Set clocks to values specified in args\n");
1042 ret = args_envs_enumerate(env_map_clock, 2, argc, argv);
1043 }
1044
1045 if (ret)
1046 return CMD_RET_FAILURE;
1047
1048 ret = envs_validate_common(env_map_clock);
1049 if (ret)
1050 return CMD_RET_FAILURE;
1051
1052 /* Setup clock tree HW */
1053 setup_clocks();
1054
1055 return CMD_RET_SUCCESS;
1056}
1057
1058static int do_hsdk_clock_get(cmd_tbl_t *cmdtp, int flag, int argc,
1059 char *const argv[])
1060{
1061 ulong rate;
1062
1063 if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ))
1064 return CMD_RET_FAILURE;
1065
1066 if (env_set_ulong("cpu_freq", rate))
1067 return CMD_RET_FAILURE;
1068
1069 if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ))
1070 return CMD_RET_FAILURE;
1071
1072 if (env_set_ulong("tun_freq", rate))
1073 return CMD_RET_FAILURE;
1074
1075 if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ))
1076 return CMD_RET_FAILURE;
1077
1078 if (env_set_ulong("axi_freq", rate))
1079 return CMD_RET_FAILURE;
1080
1081 printf("Clock values are saved to environment\n");
1082
1083 return CMD_RET_SUCCESS;
1084}
1085
1086static int do_hsdk_clock_print(cmd_tbl_t *cmdtp, int flag, int argc,
1087 char *const argv[])
1088{
1089 /* Main clocks */
1090 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
1091 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
1092 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
1093 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
1094
1095 return CMD_RET_SUCCESS;
1096}
1097
1098static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int flag, int argc,
1099 char *const argv[])
1100{
1101 /*
1102 * NOTE: as of today we don't use some peripherals like HDMI / EBI
1103 * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll",
1104 * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully
1105 * functional and we can print their clocks if it is required
1106 */
1107
1108 /* CPU clock domain */
1109 soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ);
1110 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
1111 printf("\n");
1112
1113 /* SYS clock domain */
1114 soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ);
1115 soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ);
1116 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
1117 soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
1118 soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
1119 soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
Eugeniy Paltsevb84aa4c2020-04-22 02:08:06 +03001120 if (is_board_match_runtime(T_BOARD_HSDK_4XD))
1121 soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001122 soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
Eugeniy Paltsevda34c6b2020-04-22 22:44:24 +03001123 if (is_board_match_runtime(T_BOARD_HSDK)) {
1124 soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
1125 soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
1126 }
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001127 soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
1128 soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
1129 soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
1130 soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ);
1131 soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ);
1132/* soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */
1133 soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ);
1134 printf("\n");
1135
1136 /* DDR clock domain */
1137 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
1138 printf("\n");
1139
1140 /* HDMI clock domain */
Eugeniy Paltsevb84aa4c2020-04-22 02:08:06 +03001141 if (is_board_match_runtime(T_BOARD_HSDK_4XD)) {
1142 soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ);
1143 soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ);
1144 printf("\n");
1145 }
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001146
1147 /* TUN clock domain */
1148 soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
1149 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
1150 soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
1151 soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
Eugeniy Paltsevd4ee5c32020-04-23 14:52:43 +03001152 if (is_board_match_runtime(T_BOARD_HSDK_4XD))
1153 soc_clk_ctl("timer-clk", NULL, CLK_PRINT | CLK_MHZ);
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001154 printf("\n");
1155
1156 return CMD_RET_SUCCESS;
1157}
1158
1159cmd_tbl_t cmd_hsdk_clock[] = {
1160 U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""),
1161 U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""),
1162 U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""),
1163 U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""),
1164};
1165
1166static int do_hsdk_clock(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1167{
1168 cmd_tbl_t *c;
1169
1170 if (argc < 2)
1171 return CMD_RET_USAGE;
1172
1173 /* Strip off leading 'hsdk_clock' command argument */
1174 argc--;
1175 argv++;
1176
1177 c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock));
1178 if (!c)
1179 return CMD_RET_USAGE;
1180
1181 return c->cmd(cmdtp, flag, argc, argv);
1182}
1183
1184U_BOOT_CMD(
1185 hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock,
1186 "Synopsys HSDK specific clock command",
1187 "set - Set clock to values specified in environment / command line arguments\n"
1188 "hsdk_clock get - Save clock values to environment\n"
1189 "hsdk_clock print - Print main clock values to console\n"
1190 "hsdk_clock print_all - Print all clock values to console\n"
1191);
1192
1193/* init calls */
1194int board_early_init_f(void)
1195{
1196 /*
1197 * Setup AXI apertures unconditionally as we want to have DDR
1198 * in 0x00000000 region when we are kicking slave cpus.
1199 */
1200 init_memory_bridge();
1201
Eugeniy Paltsev54858312019-02-25 18:35:29 +03001202 /*
1203 * Switch SDIO external ciu clock divider from default div-by-8 to
1204 * minimum possible div-by-2.
1205 */
1206 writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
1207
Eugeniy Paltsevada8aff2018-03-26 15:57:37 +03001208 return 0;
1209}
1210
1211int board_early_init_r(void)
1212{
1213 /*
1214 * TODO: Init USB here to be able read environment from USB MSD.
1215 * It can be done with usb_init() call. We can't do it right now
1216 * due to brocken USB IP SW reset and lack of USB IP HW reset in
1217 * linux kernel (if we init USB here we will break USB in linux)
1218 */
1219
1220 /*
1221 * Flush all d$ as we want to use uncached area with st.di / ld.di
1222 * instructions and we don't want to have any dirty line in L1d$ or SL$
1223 * in this area. It is enough to flush all d$ once here as we access to
1224 * uncached area with regular st (non .di) instruction only when we copy
1225 * data during u-boot relocation.
1226 */
1227 flush_dcache_all();
1228
1229 printf("Relocation Offset is: %08lx\n", gd->reloc_off);
1230
1231 return 0;
1232}
1233
1234int board_late_init(void)
1235{
1236 /*
1237 * Populate environment with clock frequency values -
1238 * run hsdk_clock get callback without uboot command run.
1239 */
1240 do_hsdk_clock_get(NULL, 0, 0, NULL);
1241
1242 return 0;
1243}
Eugeniy Paltsev4e782b52017-10-21 15:35:12 +03001244
Alexey Brodkin6ef705b2018-11-27 09:47:01 +03001245int checkboard(void)
1246{
Eugeniy Paltseva8eb9b22020-04-29 21:36:44 +03001247 u32 reg;
1248
Eugeniy Paltsevf0f84ef2020-04-22 00:33:40 +03001249 printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
1250
1251 if (board_mismatch())
1252 printf("WARN: U-boot is configured NOT for this board but for %s!\n",
1253 board_name(get_board_type_config()));
1254
Eugeniy Paltseva8eb9b22020-04-29 21:36:44 +03001255 reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE;
1256 printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled");
1257
Alexey Brodkin6ef705b2018-11-27 09:47:01 +03001258 return 0;
1259};