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Dirk Eibach50dcf892014-11-13 19:21:18 +01001/*
2 * (C) Copyright 2014
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_MPC83xx 1 /* MPC83xx family */
17#define CONFIG_MPC830x 1 /* MPC830x family */
18#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19#define CONFIG_HRCON 1 /* HRCON board specific */
20
21#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
Dirk Eibach50dcf892014-11-13 19:21:18 +010023#define CONFIG_BOARD_EARLY_INIT_R
24#define CONFIG_LAST_STAGE_INIT
25
Dirk Eibach50dcf892014-11-13 19:21:18 +010026#define CONFIG_FSL_ESDHC
27#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
Dirk Eibach50dcf892014-11-13 19:21:18 +010028
Dirk Eibach50dcf892014-11-13 19:21:18 +010029/*
30 * System Clock Setup
31 */
32#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
33#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
34
35/*
36 * Hardware Reset Configuration Word
37 * if CLKIN is 66.66MHz, then
38 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
39 * We choose the A type silicon as default, so the core is 400Mhz.
40 */
41#define CONFIG_SYS_HRCW_LOW (\
42 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
43 HRCWL_DDR_TO_SCB_CLK_2X1 |\
44 HRCWL_SVCOD_DIV_2 |\
45 HRCWL_CSB_TO_CLKIN_4X1 |\
46 HRCWL_CORE_TO_CSB_3X1)
47/*
48 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
49 * in 8308's HRCWH according to the manual, but original Freescale's
50 * code has them and I've expirienced some problems using the board
51 * with BDI3000 attached when I've tried to set these bits to zero
52 * (UART doesn't work after the 'reset run' command).
53 */
54#define CONFIG_SYS_HRCW_HIGH (\
55 HRCWH_PCI_HOST |\
56 HRCWH_PCI1_ARBITER_ENABLE |\
57 HRCWH_CORE_ENABLE |\
58 HRCWH_FROM_0XFFF00100 |\
59 HRCWH_BOOTSEQ_DISABLE |\
60 HRCWH_SW_WATCHDOG_DISABLE |\
61 HRCWH_ROM_LOC_LOCAL_16BIT |\
62 HRCWH_RL_EXT_LEGACY |\
63 HRCWH_TSEC1M_IN_RGMII |\
64 HRCWH_TSEC2M_IN_RGMII |\
65 HRCWH_BIG_ENDIAN)
66
67/*
68 * System IO Config
69 */
70#define CONFIG_SYS_SICRH (\
71 SICRH_ESDHC_A_SD |\
72 SICRH_ESDHC_B_SD |\
73 SICRH_ESDHC_C_SD |\
74 SICRH_GPIO_A_GPIO |\
75 SICRH_GPIO_B_GPIO |\
76 SICRH_IEEE1588_A_GPIO |\
77 SICRH_USB |\
78 SICRH_GTM_GPIO |\
79 SICRH_IEEE1588_B_GPIO |\
80 SICRH_ETSEC2_GPIO |\
81 SICRH_GPIOSEL_1 |\
82 SICRH_TMROBI_V3P3 |\
83 SICRH_TSOBI1_V2P5 |\
84 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
85#define CONFIG_SYS_SICRL (\
86 SICRL_SPI_PF0 |\
87 SICRL_UART_PF0 |\
88 SICRL_IRQ_PF0 |\
89 SICRL_I2C2_PF0 |\
90 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
91
92/*
93 * IMMR new address
94 */
95#define CONFIG_SYS_IMMR 0xE0000000
96
97/*
98 * SERDES
99 */
100#define CONFIG_FSL_SERDES
101#define CONFIG_FSL_SERDES1 0xe3000
102
103/*
104 * Arbiter Setup
105 */
106#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
107#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
108#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
109
110/*
111 * DDR Setup
112 */
113#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
114#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
115#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
116#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
117#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
118 | DDRCDR_PZ_LOZ \
119 | DDRCDR_NZ_LOZ \
120 | DDRCDR_ODT \
121 | DDRCDR_Q_DRN)
122 /* 0x7b880001 */
123/*
124 * Manually set up DDR parameters
125 * consist of one chip NT5TU64M16HG from NANYA
126 */
127
128#define CONFIG_SYS_DDR_SIZE 128 /* MB */
129
130#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
131#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
132 | CSCONFIG_ODT_RD_NEVER \
133 | CSCONFIG_ODT_WR_ONLY_CURRENT \
134 | CSCONFIG_BANK_BIT_3 \
135 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
136 /* 0x80010102 */
137#define CONFIG_SYS_DDR_TIMING_3 0
138#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
139 | (0 << TIMING_CFG0_WRT_SHIFT) \
140 | (0 << TIMING_CFG0_RRT_SHIFT) \
141 | (0 << TIMING_CFG0_WWT_SHIFT) \
142 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
143 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
144 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
145 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
146 /* 0x00260802 */
147#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
148 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
149 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
150 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
151 | (9 << TIMING_CFG1_REFREC_SHIFT) \
152 | (2 << TIMING_CFG1_WRREC_SHIFT) \
153 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
154 | (2 << TIMING_CFG1_WRTORD_SHIFT))
155 /* 0x26279222 */
156#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
157 | (4 << TIMING_CFG2_CPO_SHIFT) \
158 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
159 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
160 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
161 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
162 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
163 /* 0x021848c5 */
164#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
165 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
166 /* 0x08240100 */
167#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
168 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
169 | SDRAM_CFG_DBW_16)
170 /* 0x43100000 */
171
172#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
173#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
174 | (0x0242 << SDRAM_MODE_SD_SHIFT))
175 /* ODT 150ohm CL=4, AL=0 on SDRAM */
176#define CONFIG_SYS_DDR_MODE2 0x00000000
177
178/*
179 * Memory test
180 */
181#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
182#define CONFIG_SYS_MEMTEST_END 0x07f00000
183
184/*
185 * The reserved memory
186 */
187#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
188
189#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
190#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
191
192/*
193 * Initial RAM Base Address Setup
194 */
195#define CONFIG_SYS_INIT_RAM_LOCK 1
196#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
197#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
198#define CONFIG_SYS_GBL_DATA_OFFSET \
199 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
200
201/*
202 * Local Bus Configuration & Clock Setup
203 */
204#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
205#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
206#define CONFIG_SYS_LBC_LBCR 0x00040000
207
208/*
209 * FLASH on the Local Bus
210 */
211#if 1
212#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
213#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
214#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
215#define CONFIG_FLASH_CFI_LEGACY
216#define CONFIG_SYS_FLASH_LEGACY_512Kx16
Dirk Eibach50dcf892014-11-13 19:21:18 +0100217#endif
218
219#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
220#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
221#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
222
223/* Window base at flash base */
224#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
225#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
226
227#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
228 | BR_PS_16 /* 16 bit port */ \
229 | BR_MS_GPCM /* MSEL = GPCM */ \
230 | BR_V) /* valid */
231#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
232 | OR_UPM_XAM \
233 | OR_GPCM_CSNT \
234 | OR_GPCM_ACS_DIV2 \
235 | OR_GPCM_XACS \
236 | OR_GPCM_SCY_15 \
237 | OR_GPCM_TRLX_SET \
238 | OR_GPCM_EHTR_SET)
239
240#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
241#define CONFIG_SYS_MAX_FLASH_SECT 135
242
243#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
244#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
245
246/*
247 * FPGA
248 */
249#define CONFIG_SYS_FPGA0_BASE 0xE0600000
250#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
251
252/* Window base at FPGA base */
253#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
254#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
255
256#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
257 | BR_PS_16 /* 16 bit port */ \
258 | BR_MS_GPCM /* MSEL = GPCM */ \
259 | BR_V) /* valid */
260#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
261 | OR_UPM_XAM \
262 | OR_GPCM_CSNT \
263 | OR_GPCM_ACS_DIV2 \
264 | OR_GPCM_XACS \
265 | OR_GPCM_SCY_15 \
266 | OR_GPCM_TRLX_SET \
267 | OR_GPCM_EHTR_SET)
268
269#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
270#define CONFIG_SYS_FPGA_DONE(k) 0x0010
271
272#define CONFIG_SYS_FPGA_COUNT 1
273
274#define CONFIG_SYS_MCLINK_MAX 3
275
276#define CONFIG_SYS_FPGA_PTR \
277 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
278
279/*
280 * Serial Port
281 */
282#define CONFIG_CONS_INDEX 2
Dirk Eibach50dcf892014-11-13 19:21:18 +0100283#define CONFIG_SYS_NS16550_SERIAL
284#define CONFIG_SYS_NS16550_REG_SIZE 1
285#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
286
287#define CONFIG_SYS_BAUDRATE_TABLE \
288 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
289
290#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
291#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
292
Dirk Eibach50dcf892014-11-13 19:21:18 +0100293/* Pass open firmware flat tree */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100294
295/* I2C */
296#define CONFIG_SYS_I2C
297#define CONFIG_SYS_I2C_FSL
298#define CONFIG_SYS_FSL_I2C_SPEED 400000
299#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
300#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
301
302#define CONFIG_PCA953X /* NXP PCA9554 */
303#define CONFIG_PCA9698 /* NXP PCA9698 */
304
305#define CONFIG_SYS_I2C_IHS
306#define CONFIG_SYS_I2C_IHS_CH0
307#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
308#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
309#define CONFIG_SYS_I2C_IHS_CH1
310#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
311#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
312#define CONFIG_SYS_I2C_IHS_CH2
313#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
314#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
315#define CONFIG_SYS_I2C_IHS_CH3
316#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
317#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
318
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100319#ifdef CONFIG_HRCON_DH
320#define CONFIG_SYS_I2C_IHS_DUAL
321#define CONFIG_SYS_I2C_IHS_CH0_1
322#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
323#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
324#define CONFIG_SYS_I2C_IHS_CH1_1
325#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
326#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
327#define CONFIG_SYS_I2C_IHS_CH2_1
328#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
329#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
330#define CONFIG_SYS_I2C_IHS_CH3_1
331#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
332#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
333#endif
334
Dirk Eibach50dcf892014-11-13 19:21:18 +0100335/*
336 * Software (bit-bang) I2C driver configuration
337 */
338#define CONFIG_SYS_I2C_SOFT
339#define CONFIG_SYS_I2C_SOFT_SPEED 50000
340#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
341#define I2C_SOFT_DECLARATIONS2
342#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
343#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
344#define I2C_SOFT_DECLARATIONS3
345#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
346#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
347#define I2C_SOFT_DECLARATIONS4
348#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
349#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100350#define I2C_SOFT_DECLARATIONS5
351#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
352#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
353#define I2C_SOFT_DECLARATIONS6
354#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
355#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
356#define I2C_SOFT_DECLARATIONS7
357#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
358#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
359#define I2C_SOFT_DECLARATIONS8
360#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
361#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100362
363#ifdef CONFIG_HRCON_DH
364#define I2C_SOFT_DECLARATIONS9
365#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
366#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
367#define I2C_SOFT_DECLARATIONS10
368#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
369#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
370#define I2C_SOFT_DECLARATIONS11
371#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
372#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
373#define I2C_SOFT_DECLARATIONS12
374#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
375#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100376#endif
377
378#ifdef CONFIG_HRCON_DH
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100379#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100380#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100381#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
382 {12, 0x4c} }
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100383#else
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100384#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
Dirk Eibach50dcf892014-11-13 19:21:18 +0100385#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100386#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
387 {8, 0x4c} }
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100388#endif
Dirk Eibach50dcf892014-11-13 19:21:18 +0100389
390#ifndef __ASSEMBLY__
391void fpga_gpio_set(unsigned int bus, int pin);
392void fpga_gpio_clear(unsigned int bus, int pin);
393int fpga_gpio_get(unsigned int bus, int pin);
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100394void fpga_control_set(unsigned int bus, int pin);
395void fpga_control_clear(unsigned int bus, int pin);
Dirk Eibach50dcf892014-11-13 19:21:18 +0100396#endif
397
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100398#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
399#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
400#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
401
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100402#ifdef CONFIG_HRCON_DH
403#define I2C_ACTIVE \
404 do { \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100405 if (I2C_ADAP_HWNR > 7) \
406 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100407 else \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100408 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100409 } while (0)
410#else
Dirk Eibach50dcf892014-11-13 19:21:18 +0100411#define I2C_ACTIVE { }
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100412#endif
Dirk Eibach50dcf892014-11-13 19:21:18 +0100413#define I2C_TRISTATE { }
414#define I2C_READ \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100415 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
Dirk Eibach50dcf892014-11-13 19:21:18 +0100416#define I2C_SDA(bit) \
417 do { \
418 if (bit) \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100419 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
Dirk Eibach50dcf892014-11-13 19:21:18 +0100420 else \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100421 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
Dirk Eibach50dcf892014-11-13 19:21:18 +0100422 } while (0)
423#define I2C_SCL(bit) \
424 do { \
425 if (bit) \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100426 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
Dirk Eibach50dcf892014-11-13 19:21:18 +0100427 else \
Dirk Eibach5c3b6dc2015-10-28 11:46:36 +0100428 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
Dirk Eibach50dcf892014-11-13 19:21:18 +0100429 } while (0)
430#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
431
432/*
433 * Software (bit-bang) MII driver configuration
434 */
435#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
436#define CONFIG_BITBANGMII_MULTI
437
438/*
439 * OSD Setup
440 */
441#define CONFIG_SYS_OSD_SCREENS 1
442#define CONFIG_SYS_DP501_DIFFERENTIAL
443#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
444
Dirk Eibach7ed45d32015-10-28 11:46:35 +0100445#ifdef CONFIG_HRCON_DH
446#define CONFIG_SYS_OSD_DH
447#endif
448
Dirk Eibach50dcf892014-11-13 19:21:18 +0100449/*
450 * General PCI
451 * Addresses are mapped 1-1.
452 */
453#define CONFIG_SYS_PCIE1_BASE 0xA0000000
454#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
455#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
456#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
457#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
458#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
459#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
460#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
461#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
462
463/* enable PCIE clock */
464#define CONFIG_SYS_SCCR_PCIEXP1CM 1
465
Dirk Eibach50dcf892014-11-13 19:21:18 +0100466#define CONFIG_PCI_INDIRECT_BRIDGE
467#define CONFIG_PCIE
468
Dirk Eibach50dcf892014-11-13 19:21:18 +0100469#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
470#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
471
472/*
473 * TSEC
474 */
475#define CONFIG_TSEC_ENET /* TSEC ethernet support */
476#define CONFIG_SYS_TSEC1_OFFSET 0x24000
477#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
478
479/*
480 * TSEC ethernet configuration
481 */
482#define CONFIG_MII 1 /* MII PHY management */
483#define CONFIG_TSEC1
484#define CONFIG_TSEC1_NAME "eTSEC0"
485#define TSEC1_PHY_ADDR 1
486#define TSEC1_PHYIDX 0
487#define TSEC1_FLAGS TSEC_GIGABIT
488
489/* Options are: eTSEC[0-1] */
490#define CONFIG_ETHPRIME "eTSEC0"
491
492/*
493 * Environment
494 */
495#if 1
Dirk Eibach50dcf892014-11-13 19:21:18 +0100496#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
497 CONFIG_SYS_MONITOR_LEN)
498#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
499#define CONFIG_ENV_SIZE 0x2000
500#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
501#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
502#else
Dirk Eibach50dcf892014-11-13 19:21:18 +0100503#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
504#endif
505
506#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
507#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
508
509/*
510 * Command line configuration.
511 */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100512#define CONFIG_CMD_PCI
Dirk Eibach50dcf892014-11-13 19:21:18 +0100513
514#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
515#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
516
517/*
518 * Miscellaneous configurable options
519 */
520#define CONFIG_SYS_LONGHELP /* undef to save memory */
521#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dirk Eibach50dcf892014-11-13 19:21:18 +0100522#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
523
Dirk Eibach50dcf892014-11-13 19:21:18 +0100524#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
525
Dirk Eibach50dcf892014-11-13 19:21:18 +0100526/* Print Buffer Size */
527#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
528#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
529#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
530
531/*
532 * For booting Linux, the board info and command line data
533 * have to be in the first 256 MB of memory, since this is
534 * the maximum mapped by the Linux kernel during initialization.
535 */
536#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
537
538/*
539 * Core HID Setup
540 */
541#define CONFIG_SYS_HID0_INIT 0x000000000
542#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
543 HID0_ENABLE_INSTRUCTION_CACHE | \
544 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
545#define CONFIG_SYS_HID2 HID2_HBE
546
547/*
548 * MMU Setup
549 */
550
551/* DDR: cache cacheable */
552#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
553 BATL_MEMCOHERENCE)
554#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
555 BATU_VS | BATU_VP)
556#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
557#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
558
559/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
560#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
561 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
562#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
563 BATU_VP)
564#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
565#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
566
567/* FLASH: icache cacheable, but dcache-inhibit and guarded */
568#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
569 BATL_MEMCOHERENCE)
570#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
571 BATU_VS | BATU_VP)
572#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
573 BATL_CACHEINHIBIT | \
574 BATL_GUARDEDSTORAGE)
575#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
576
577/* Stack in dcache: cacheable, no memory coherence */
578#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
579#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
580 BATU_VS | BATU_VP)
581#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
582#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
583
584/*
585 * Environment Configuration
586 */
587
588#define CONFIG_ENV_OVERWRITE
589
590#if defined(CONFIG_TSEC_ENET)
591#define CONFIG_HAS_ETH0
592#endif
593
Dirk Eibach50dcf892014-11-13 19:21:18 +0100594#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
595
Dirk Eibach50dcf892014-11-13 19:21:18 +0100596
597#define CONFIG_HOSTNAME hrcon
598#define CONFIG_ROOTPATH "/opt/nfsroot"
599#define CONFIG_BOOTFILE "uImage"
600
601#define CONFIG_PREBOOT /* enable preboot variable */
602
603#define CONFIG_EXTRA_ENV_SETTINGS \
604 "netdev=eth0\0" \
605 "consoledev=ttyS1\0" \
606 "u-boot=u-boot.bin\0" \
607 "kernel_addr=1000000\0" \
608 "fdt_addr=C00000\0" \
609 "fdtfile=hrcon.dtb\0" \
610 "load=tftp ${loadaddr} ${u-boot}\0" \
611 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
612 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
613 " +${filesize};cp.b ${fileaddr} " \
614 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
615 "upd=run load update\0" \
616
617#define CONFIG_NFSBOOTCOMMAND \
618 "setenv bootargs root=/dev/nfs rw " \
619 "nfsroot=$serverip:$rootpath " \
620 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
621 "console=$consoledev,$baudrate $othbootargs;" \
622 "tftp ${kernel_addr} $bootfile;" \
623 "tftp ${fdt_addr} $fdtfile;" \
624 "bootm ${kernel_addr} - ${fdt_addr}"
625
626#define CONFIG_MMCBOOTCOMMAND \
627 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
628 "console=$consoledev,$baudrate $othbootargs;" \
629 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
630 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
631 "bootm ${kernel_addr} - ${fdt_addr}"
632
633#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
634
Dirk Eibach50dcf892014-11-13 19:21:18 +0100635#endif /* __CONFIG_H */