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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */
38#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/
39
40#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
41#define CONFIG_8xx_CONS_SMC2 1
42#undef CONFIG_8xx_CONS_NONE
43
44#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
46
47#undef CONFIG_CLOCKS_IN_MHZ
48
49#if 0
50#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp"
51#define CONFIG_BOOTCOMMAND \
52 "setenv bootargs root=/dev/ram ip=off panic=1;" \
53 "bootm 40040000 400e0000"
54#else
55#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1"
56#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000"
57#endif /* 0|1*/
58
59#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
60#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
61
62/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */
63#undef CONFIG_WATCHDOG /* watchdog disabled */
64
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050065/*
66 * BOOTP options
67 */
68#define CONFIG_BOOTP_SUBNETMASK
69#define CONFIG_BOOTP_GATEWAY
70#define CONFIG_BOOTP_HOSTNAME
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_BOOTFILESIZE
73
wdenk0f8c9762002-08-19 11:57:05 +000074
Jon Loeliger60a08762007-07-07 21:04:26 -050075/*
76 * Command line configuration.
77 */
wdenk0f8c9762002-08-19 11:57:05 +000078
Jon Loeliger60a08762007-07-07 21:04:26 -050079#define CONFIG_CMD_BDI
80#define CONFIG_CMD_IMI
81#define CONFIG_CMD_CACHE
82#define CONFIG_CMD_MEMORY
83#define CONFIG_CMD_FLASH
84#define CONFIG_CMD_LOADB
85#define CONFIG_CMD_LOADS
86#define CONFIG_CMD_ENV
87#define CONFIG_CMD_REGINFO
88#define CONFIG_CMD_IMMAP
89#define CONFIG_CMD_NET
90
wdenk0f8c9762002-08-19 11:57:05 +000091
92/*
93 * Miscellaneous configurable options
94 */
95#define CFG_LONGHELP /* undef to save memory */
96#define CFG_PROMPT "EEG> " /* Monitor Command Prompt */
Jon Loeliger60a08762007-07-07 21:04:26 -050097#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +000098#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
99#else
100#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
101#endif
102#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
103#define CFG_MAXARGS 16 /* max number of command args */
104#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
105
106#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
107#define CFG_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */
108
109#define CFG_LOAD_ADDR 0x40040000 /* default load address */
110
111#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
112
113#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
114
115/*
116 * Low Level Configuration Settings
117 * (address mappings, register initial values, etc.)
118 * You should know what you are doing if you make changes here.
119 */
120/*-----------------------------------------------------------------------
121 * Internal Memory Mapped Register
122 */
123#define CFG_IMMR 0xFF000000
124
125/*-----------------------------------------------------------------------
126 * Definitions for initial stack pointer and data area (in DPRAM)
127 */
128#define CFG_INIT_RAM_ADDR CFG_IMMR
129#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
130#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
131#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
132#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
133
134/*-----------------------------------------------------------------------
135 * Start addresses for the final memory configuration
136 * (Set up by the startup code)
137 * Please note that CFG_SDRAM_BASE _must_ start at 0
138 */
139#define CFG_SDRAM_BASE 0x00000000
140#define CFG_FLASH_BASE 0x40000000
141#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
142#define CFG_MONITOR_BASE CFG_FLASH_BASE
143#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
144
145/*
146 * For booting Linux, the board info and command line data
147 * have to be in the first 8 MB of memory, since this is
148 * the maximum mapped by the Linux kernel during initialization.
149 */
150#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
151
152/*-----------------------------------------------------------------------
153 * FLASH organization
154 */
155#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
156#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
157
158#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
159#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
160
161#define CFG_ENV_IS_IN_FLASH 1
162/* This is a litlebit wasteful, but one sector is 128kb and we have to
163 * assigne a whole sector for the environment, so that we can safely
164 * erase and write it without disturbing the boot sector
165 */
166#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
167#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
168
169/*-----------------------------------------------------------------------
170 * Cache Configuration
171 */
172#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500173#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000174#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
175#endif
176
177/*-----------------------------------------------------------------------
178 * SYPCR - System Protection Control 11-9
179 * SYPCR can only be written once after reset!
180 *-----------------------------------------------------------------------
181 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
182 */
183#ifdef CONFIG_WATCHDOG
184#define CFG_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
185#else
186#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
187#endif
188
189/*-----------------------------------------------------------------------
190 * SIUMCR - SIU Module Configuration 11-6
191 *-----------------------------------------------------------------------
192 * PCMCIA config., multi-function pin tri-state
193 */
194#define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
195 SIUMCR_MLRC01 | SIUMCR_GB5E)
196#define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK)
197
198/*-----------------------------------------------------------------------
199 * TBSCR - Time Base Status and Control 11-26
200 *-----------------------------------------------------------------------
201 * Clear Reference Interrupt Status, Timebase freezing enabled
202 */
203#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
204
205/*-----------------------------------------------------------------------
206 * RTCSC - Real-Time Clock Status and Control Register 11-27
207 *-----------------------------------------------------------------------
208 */
209#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
210
211/*-----------------------------------------------------------------------
212 * PISCR - Periodic Interrupt Status and Control 11-31
213 *-----------------------------------------------------------------------
214 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
215 */
216#define CFG_PISCR (PISCR_PS | PISCR_PITF)
217
218/*-----------------------------------------------------------------------
219 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
220 *-----------------------------------------------------------------------
221 * Reset PLL lock status sticky bit, timer expired status bit and timer
222 * interrupt status bit miltiplier of 0x00b i.e. operation clock is
223 * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz
224 */
225#define CFG_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
226
227/*-----------------------------------------------------------------------
228 * SCCR - System Clock and reset Control Register 15-27
229 *-----------------------------------------------------------------------
230 * Set clock output, timebase and RTC source and divider,
231 * power management and some other internal clocks
232 */
233#define SCCR_MASK SCCR_EBDF11
234#define CFG_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
235 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
236 SCCR_DFALCD00)
237
238#define CFG_DER 0
239
240/*
241 * In the Flaga DM we have:
242 * Flash on BR0/OR0/CS0a at 0x40000000
243 * Display on BR1/OR1/CS1 at 0x20000000
244 * SDRAM on BR2/OR2/CS2 at 0x00000000
245 * Free BR3/OR3/CS3
246 * DSP1 on BR4/OR4/CS4 at 0x80000000
247 * DSP2 on BR5/OR5/CS5 at 0xa0000000
248 *
249 * For now we just configure the Flash and the SDRAM and leave the others
250 * untouched.
251*/
252
253#define CFG_FLASH_PROTECTION 0
254
255#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */
256
257/* used to re-map FLASH both when starting from SRAM or FLASH:
258 * restrict access enough to keep SRAM working (if any)
259 * but not too much to meddle with FLASH accesses
260 */
261#define CFG_OR_AM 0xff000000 /* OR addr mask */
262#define CFG_OR_ATM 0x00006000
263
264/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
265#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \
266 OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
267
268#define CFG_OR0_PRELIM (CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH)
269#define CFG_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
270
271/*
272 * BR2 and OR2 (SDRAM)
273 *
274 */
275#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */
276#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
277
278/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
279#define CFG_OR_TIMING_SDRAM ( 0x00000800 )
280
281#define CFG_OR2_PRELIM (CFG_OR_AM | CFG_OR_TIMING_SDRAM)
282#define CFG_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
283
284#define CFG_BR2 CFG_BR2_PRELIM
285#define CFG_OR2 CFG_OR2_PRELIM
286
287/*
288 * MAMR settings for SDRAM
289 */
290#define CFG_MAMR_48_SDR (CFG_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \
291 | MAMR_G0CLA_A11)
292
293/*
294 * Memory Periodic Timer Prescaler
295 */
296
297/* periodic timer for refresh */
298#define CFG_MAMR_PTA 0x0F000000
299
300/*
301 * BR4 and OR4 (DSP1)
302 *
303 * We do not wan't preliminary setup of the DSP, anyway we need the
304 * UPMB setup correctly before we can access the DSP.
305 *
306*/
307#define DSP_BASE 0x80000000
308
309#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
310#define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
311
312/*
313 * Internal Definitions
314 *
315 * Boot Flags
316 */
317#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
318#define BOOTFLAG_WARM 0x02 /* Software reboot */
319
320#endif /* __CONFIG_H */