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Roy Zang3f7f6b82011-06-09 11:30:52 +08001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Roy Zang3f7f6b82011-06-09 11:30:52 +08003 *
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <b25806@freescale.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Roy Zang3f7f6b82011-06-09 11:30:52 +08008 */
9
10/*
11 * p1023rds board configuration file
12 *
13 */
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17#ifdef CONFIG_NAND
18#define CONFIG_NAND_U_BOOT
19#define CONFIG_RAMBOOT_NAND
20#endif
21
22#ifdef CONFIG_NAND_U_BOOT
23#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
24#define CONFIG_SYS_TEXT_BASE 0x11001000
25
26#ifdef CONFIG_NAND_SPL
27#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
28#else
Masahiro Yamada4a377552014-02-25 19:26:48 +090029#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
Roy Zang3f7f6b82011-06-09 11:30:52 +080030#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
31#endif /* CONFIG_NAND_SPL */
32#endif
33
34#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053035#define CONFIG_SYS_TEXT_BASE 0xeff40000
Roy Zang3f7f6b82011-06-09 11:30:52 +080036#endif
37
38#ifndef CONFIG_SYS_MONITOR_BASE
39#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
40#endif
41
42#ifndef CONFIG_RESET_VECTOR_ADDRESS
43#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
44#endif
45
46/* High Level Configuration Options */
47#define CONFIG_BOOKE /* BOOKE */
48#define CONFIG_E500 /* BOOKE e500 family */
Roy Zang3f7f6b82011-06-09 11:30:52 +080049#define CONFIG_P1023
50#define CONFIG_P1023RDS
51#define CONFIG_MP /* support multiple processors */
52
53#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
54#define CONFIG_PCI /* Enable PCI/PCIE */
55#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
56#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
57#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
58#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000059#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Roy Zang3f7f6b82011-06-09 11:30:52 +080060#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
61#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62#define CONFIG_FSL_LAW /* Use common FSL init code */
63
64#ifndef __ASSEMBLY__
65extern unsigned long get_clock_freq(void);
66#endif
67
68#define CONFIG_SYS_CLK_FREQ 66666666
69#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
70
71/*
72 * These can be toggled for performance analysis, otherwise use default.
73 */
74#define CONFIG_L2_CACHE /* toggle L2 cache */
75#define CONFIG_BTB /* toggle branch predition */
76#define CONFIG_HWCONFIG
77
78#define CONFIG_ENABLE_36BIT_PHYS
79
80#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
81#define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */
82#define CONFIG_PANIC_HANG /* do not reset board on panic */
83
84#define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of
85 addresses in the LBC */
Roy Zang3f7f6b82011-06-09 11:30:52 +080086
87/* DDR Setup */
88#define CONFIG_VERY_BIG_RAM
89
90#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
91#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92
93#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
94#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
95
96#define CONFIG_DIMM_SLOTS_PER_CTLR 1
97#define CONFIG_CHIP_SELECTS_PER_CTRL 2
98
99/* These are used when DDR doesn't use SPD. */
100#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */
101
102/* Default settings for "stable" mode */
103#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
104#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
105#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
106#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
107#define CONFIG_SYS_DDR_TIMING_3 0x00020000
108#define CONFIG_SYS_DDR_TIMING_0 0x40110104
109#define CONFIG_SYS_DDR_TIMING_1 0x5C59E544
110#define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA
111#define CONFIG_SYS_DDR_MODE_1 0x00441210
112#define CONFIG_SYS_DDR_MODE_2 0x00000000
113#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
114#define CONFIG_SYS_DDR_INTERVAL 0x0A280100
115#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
116#define CONFIG_SYS_DDR_CLK_CTRL 0x01800000
117#define CONFIG_SYS_DDR_TIMING_4 0x00000001
118#define CONFIG_SYS_DDR_TIMING_5 0x01401400
119#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
120#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605
121#define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */
122#define CONFIG_SYS_DDR_CONTROL2 0x24401010
123#define CONFIG_SYS_DDR_CDR1 0x00000000
124#define CONFIG_SYS_DDR_CDR2 0x00000000
125
126#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
127#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
128#define CONFIG_SYS_DDR_SBE 0x00000000
129
130/* Settings that differ for "performance" mode */
131#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
132#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
133#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302
134#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544
135#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA
136/* Type = DDR3: cs0-cs1 interleaving */
137#define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008
138#define CONFIG_SYS_DDR_CDR_1 0x00000000
139#define CONFIG_SYS_DDR_CDR_2 0x00000000
140
141
142/*
143 * Memory map
144 *
145 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
146 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
147 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
148 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
149 *
150 * Localbus non-cacheable
151 * 0xe000_0000 0xe003_ffff BCSR 256K BCSR
152 * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
153 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
154 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
155 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
156 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
157 */
158
159/*
160 * Local Bus Definitions
161 */
162#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
163#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
164
165#ifndef CONFIG_NAND
166#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
167
168#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
169
170#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
171 | BR_PS_16 | BR_V)
172#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
173
174#define CONFIG_FLASH_CFI_DRIVER
175#define CONFIG_SYS_FLASH_CFI
176#define CONFIG_SYS_FLASH_EMPTY_INFO
177
178#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
179#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
180#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
181#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
182#else
183#define CONFIG_SYS_NO_FLASH
184#endif
185
186#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
187#define CONFIG_SYS_RAMBOOT
188#endif
189
190#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
191#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
192
193#define CONFIG_SYS_INIT_RAM_LOCK
194#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
195#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
196
Roy Zang3f7f6b82011-06-09 11:30:52 +0800197#define CONFIG_SYS_GBL_DATA_OFFSET \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900198 (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
Roy Zang3f7f6b82011-06-09 11:30:52 +0800199#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
200
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530201#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Roy Zang3f7f6b82011-06-09 11:30:52 +0800202#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
203
204#ifndef CONFIG_NAND_SPL
205#define CONFIG_SYS_NAND_BASE 0xffa00000
206#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
207#else
208#define CONFIG_SYS_NAND_BASE 0xfff00000
209#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
210#endif
211
212#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
213#define CONFIG_SYS_MAX_NAND_DEVICE 1
214#define CONFIG_MTD_NAND_VERIFY_WRITE
215#define CONFIG_CMD_NAND
216#define CONFIG_NAND_FSL_ELBC
217#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
218
219/* NAND boot: 4K NAND loader config */
220#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530221#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
Roy Zang3f7f6b82011-06-09 11:30:52 +0800222#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
223#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
224#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
225#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
226#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
227
228/* NAND flash config */
229#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
230 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
231 | BR_PS_8 /* Port Size = 8bit */ \
232 | BR_MS_FCM /* MSEL = FCM */ \
233 | BR_V) /* valid */
234#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
235 | OR_FCM_CSCT \
236 | OR_FCM_CST \
237 | OR_FCM_CHT \
238 | OR_FCM_SCY_1 \
239 | OR_FCM_TRLX \
240 | OR_FCM_EHTR)
241
242#ifdef CONFIG_RAMBOOT_NAND
243/* NAND Base Address */
244#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
245#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
246/* chip select 1 - BCSR */
247#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
248 | BR_MS_GPCM | BR_PS_8 | BR_V)
249#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
250 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
251 | OR_GPCM_EAD)
252#else
253#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
254#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
255/* chip select 1 - BCSR */
256#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
257 | BR_MS_GPCM | BR_PS_8 | BR_V)
258#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
259 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
260 | OR_GPCM_EAD)
261#endif
262
263/* Serial Port
264 * open - index 2
265 * shorted - index 1
266 */
267#define CONFIG_CONS_INDEX 1
268#undef CONFIG_SERIAL_SOFTWARE_FIFO
269#define CONFIG_SYS_NS16550
270#define CONFIG_SYS_NS16550_SERIAL
271#define CONFIG_SYS_NS16550_REG_SIZE 1
272#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
273#ifdef CONFIG_NAND_SPL
274#define CONFIG_NS16550_MIN_FUNCTIONS
275#endif
276
277#define CONFIG_SYS_BAUDRATE_TABLE \
278 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
279
280#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
281#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
282
283/* Use the HUSH parser */
284#define CONFIG_SYS_HUSH_PARSER
Roy Zang3f7f6b82011-06-09 11:30:52 +0800285
286/*
287 * Pass open firmware flat tree
288 */
289#define CONFIG_OF_LIBFDT
290#define CONFIG_OF_BOARD_SETUP
291#define CONFIG_OF_STDOUT_VIA_ALIAS
292
Roy Zang3f7f6b82011-06-09 11:30:52 +0800293/* new uImage format support */
294#define CONFIG_FIT
295#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
296
297/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200298#define CONFIG_SYS_I2C
299#define CONFIG_SYS_I2C_FSL
300#define CONFIG_SYS_FSL_I2C_SPEED 400000
301#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
302#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
303#define CONFIG_SYS_FSL_I2C2_SPEED 400000
304#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
305#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Roy Zang3f7f6b82011-06-09 11:30:52 +0800306#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
Roy Zang3f7f6b82011-06-09 11:30:52 +0800307
308/*
309 * I2C2 EEPROM
310 */
311#define CONFIG_ID_EEPROM
312#ifdef CONFIG_ID_EEPROM
313#define CONFIG_SYS_I2C_EEPROM_NXID
314#endif
315#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
316#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
317#define CONFIG_SYS_EEPROM_BUS_NUM 0
318
319#define CONFIG_CMD_I2C
320
321/*
322 * eSPI - Enhanced SPI
323 */
324#define CONFIG_SPI_FLASH
325#define CONFIG_SPI_FLASH_ATMEL
326
327#define CONFIG_HARD_SPI
328#define CONFIG_FSL_ESPI
329
330#define CONFIG_CMD_SF
331#define CONFIG_SF_DEFAULT_SPEED 10000000
332#define CONFIG_SF_DEFAULT_MODE 0
333
334/*
335 * General PCI
336 * Memory space is mapped 1-1, but I/O space must start from 0.
337 */
338
339/* controller 3, Slot 1, tgtid 3, Base address b000 */
340#define CONFIG_SYS_PCIE3_NAME "Slot 3"
341#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
342#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
343#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
344#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
345#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
346#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
347#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
348#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
349
350/* controller 2, direct to uli, tgtid 2, Base address 9000 */
351#define CONFIG_SYS_PCIE2_NAME "Slot 2"
352#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
353#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
354#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
355#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
356#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
357#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
358#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
359#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
360
361/* controller 1, Slot 2, tgtid 1, Base address a000 */
362#define CONFIG_SYS_PCIE1_NAME "Slot 1"
363#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
364#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
365#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
366#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
367#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
368#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
369#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
370#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
371
372#if defined(CONFIG_PCI)
373#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
Roy Zang3f7f6b82011-06-09 11:30:52 +0800374#define CONFIG_PCI_PNP /* do pci plug-and-play */
375#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
376#endif /* CONFIG_PCI */
377
Roy Zang3f7f6b82011-06-09 11:30:52 +0800378/*
379 * Environment
380 */
381#define CONFIG_ENV_OVERWRITE
382
383#if defined(CONFIG_SYS_RAMBOOT)
384#if defined(CONFIG_RAMBOOT_NAND)
385#define CONFIG_ENV_IS_IN_NAND
386#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530387#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Roy Zang3f7f6b82011-06-09 11:30:52 +0800388#else
389#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
390#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
391#define CONFIG_ENV_SIZE 0x2000
392#endif
393#else
394#define CONFIG_ENV_IS_IN_FLASH
Roy Zang3f7f6b82011-06-09 11:30:52 +0800395#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Roy Zang3f7f6b82011-06-09 11:30:52 +0800396#define CONFIG_ENV_SIZE 0x2000
397#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
398#endif
399
400#define CONFIG_LOADS_ECHO /* echo on for serial download */
401#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
402
403/*
404 * Command line configuration.
405 */
406#include <config_cmd_default.h>
407
408#define CONFIG_CMD_IRQ
409#define CONFIG_CMD_PING
410#define CONFIG_CMD_MII
411#define CONFIG_CMD_ELF
412#define CONFIG_CMD_SETEXPR
413#define CONFIG_CMD_REGINFO
414
415#if defined(CONFIG_PCI)
416#define CONFIG_CMD_PCI
417#define CONFIG_CMD_NET
418#endif
419
420/*
421 * USB
422 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000423#define CONFIG_HAS_FSL_DR_USB
424#ifdef CONFIG_HAS_FSL_DR_USB
Roy Zang3f7f6b82011-06-09 11:30:52 +0800425#define CONFIG_USB_EHCI
426
427#ifdef CONFIG_USB_EHCI
428#define CONFIG_CMD_USB
429#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
430#define CONFIG_USB_EHCI_FSL
431#define CONFIG_USB_STORAGE
432#define CONFIG_CMD_FAT
433#define CONFIG_CMD_EXT2
434#define CONFIG_CMD_FAT
435#define CONFIG_DOS_PARTITION
436#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000437#endif
Roy Zang3f7f6b82011-06-09 11:30:52 +0800438
439/*
440 * Miscellaneous configurable options
441 */
442#define CONFIG_SYS_LONGHELP /* undef to save memory */
443#define CONFIG_CMDLINE_EDITING /* Command-line editing */
444#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Roy Zang3f7f6b82011-06-09 11:30:52 +0800445#if defined(CONFIG_CMD_KGDB)
446#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
447#else
448#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
449#endif
450/* Print Buffer Size */
451#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
452#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
453/* Boot Argument Buffer Size */
454#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Roy Zang3f7f6b82011-06-09 11:30:52 +0800455
456/*
457 * For booting Linux, the board info and command line data
458 * have to be in the first 16 MB of memory, since this is
459 * the maximum mapped by the Linux kernel during initialization.
460 */
461#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
462#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
463
464#if defined(CONFIG_CMD_KGDB)
465#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Roy Zang3f7f6b82011-06-09 11:30:52 +0800466#endif
467
468/*
469 * Environment Configuration
470 */
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000471#define CONFIG_BOOTFILE "uImage"
Roy Zang3f7f6b82011-06-09 11:30:52 +0800472#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
473
474/* default location for tftp and bootm */
475#define CONFIG_LOADADDR 1000000
476
477#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
478
479#define CONFIG_BAUDRATE 115200
480
481/* Qman/Bman */
482#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
483#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
484#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
485#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
486#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
487#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
488#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
489
490/* For FM */
491#define CONFIG_SYS_DPAA_FMAN
492#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
493
494#ifdef CONFIG_SYS_DPAA_FMAN
495#define CONFIG_FMAN_ENET
Roy Zangfe1a1da2011-02-04 13:42:45 -0600496#define CONFIG_PHY_MARVELL
Roy Zang3f7f6b82011-06-09 11:30:52 +0800497#endif
498
499#ifndef CONFIG_NAND
500/* Default address of microcode for the Linux Fman driver */
501/* QE microcode/firmware address */
Timur Tabif2717b42011-11-22 09:21:25 -0600502#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800503#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Roy Zang3f7f6b82011-06-09 11:30:52 +0800504#else
Timur Tabif2717b42011-11-22 09:21:25 -0600505#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800506#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000
Roy Zang3f7f6b82011-06-09 11:30:52 +0800507#endif
Timur Tabif2717b42011-11-22 09:21:25 -0600508#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
509#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
Roy Zang3f7f6b82011-06-09 11:30:52 +0800510
511#ifdef CONFIG_FMAN_ENET
512#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
513#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7
514
515#define CONFIG_SYS_TBIPA_VALUE 8
516#define CONFIG_MII /* MII PHY management */
517#define CONFIG_ETHPRIME "FM1@DTSEC1"
518#endif
519
520#define CONFIG_EXTRA_ENV_SETTINGS \
521 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
522
523#endif /* __CONFIG_H */