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wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * (C) Copyright 2003 Motorola Inc.
3 * Xianghua Xiao (X.Xiao@motorola.com)
4 * Modified based on 8260 for 8560.
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
28 */
29
30/*
31 * Minimal serial functions needed to use one of the SCC ports
32 * as serial console interface.
33 */
34
35#include <common.h>
36#include <asm/cpm_85xx.h>
37
Wolfgang Denkd87080b2006-03-31 18:32:53 +020038DECLARE_GLOBAL_DATA_PTR;
39
wdenk42d1f032003-10-15 23:53:47 +000040#if defined(CONFIG_CONS_ON_SCC)
41
42#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
43
44#define SCC_INDEX 0
45#define PROFF_SCC PROFF_SCC1
46#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
47 CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
48#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
49#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
50#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
51
52#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
53
54#define SCC_INDEX 1
55#define PROFF_SCC PROFF_SCC2
56#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
57 CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
58#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
59#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
60#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
61
62#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
63
64#define SCC_INDEX 2
65#define PROFF_SCC PROFF_SCC3
66#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
67 CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
68#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
69#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
70#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
71
72#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
73
74#define SCC_INDEX 3
75#define PROFF_SCC PROFF_SCC4
76#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
77 CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
78#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
79#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
80#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
81
82#else
83
84#error "console not correctly defined"
85
86#endif
87
88int serial_init (void)
89{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +000091 volatile ccsr_cpm_scc_t *sp;
92 volatile scc_uart_t *up;
93 volatile cbd_t *tbdf, *rbdf;
Kumar Galaaafeefb2007-11-28 00:36:33 -060094 volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
wdenk42d1f032003-10-15 23:53:47 +000095 uint dpaddr;
96
97 /* initialize pointers to SCC */
98
Kumar Galaaafeefb2007-11-28 00:36:33 -060099 sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
100 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
wdenk42d1f032003-10-15 23:53:47 +0000101
102 /* Disable transmitter/receiver.
103 */
104 sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
105
106 /* put the SCC channel into NMSI (non multiplexd serial interface)
107 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
108 */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600109 cpm->im_cpm_mux.cmxscr = \
110 (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
wdenk42d1f032003-10-15 23:53:47 +0000111
112 /* Set up the baud rate generator.
113 */
114 serial_setbrg ();
115
116 /* Allocate space for two buffer descriptors in the DP ram.
117 * damm: allocating space after the two buffers for rx/tx data
118 */
119
120 dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
121
122 /* Set the physical address of the host memory buffers in
123 * the buffer descriptors.
124 */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600125 rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
wdenk42d1f032003-10-15 23:53:47 +0000126 rbdf->cbd_bufaddr = (uint) (rbdf+2);
127 rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
128 tbdf = rbdf + 1;
129 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
130 tbdf->cbd_sc = BD_SC_WRAP;
131
132 /* Set up the uart parameters in the parameter ram.
133 */
134 up->scc_genscc.scc_rbase = dpaddr;
135 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
136 up->scc_genscc.scc_rfcr = CPMFCR_EB;
137 up->scc_genscc.scc_tfcr = CPMFCR_EB;
138 up->scc_genscc.scc_mrblr = 1;
139 up->scc_maxidl = 0;
140 up->scc_brkcr = 1;
141 up->scc_parec = 0;
142 up->scc_frmec = 0;
143 up->scc_nosec = 0;
144 up->scc_brkec = 0;
145 up->scc_uaddr1 = 0;
146 up->scc_uaddr2 = 0;
147 up->scc_toseq = 0;
148 up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
149 up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
150 up->scc_rccm = 0xc0ff;
151
152 /* Mask all interrupts and remove anything pending.
153 */
154 sp->sccm = 0;
155 sp->scce = 0xffff;
156
157 /* Set 8 bit FIFO, 16 bit oversampling and UART mode.
158 */
159 sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
160 sp->gsmrl = \
161 SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
162
163 /* Set CTS no flow control, 1 stop bit, 8 bit character length,
164 * normal async UART mode, no parity
165 */
166 sp->psmr = SCU_PSMR_CL;
167
168 /* execute the "Init Rx and Tx params" CP command.
169 */
170
171 while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
172 ;
173
174 cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
175 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
176
177 while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
178 ;
179
180 /* Enable transmitter/receiver.
181 */
182 sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
183
184 return (0);
185}
186
187void
188serial_setbrg (void)
189{
wdenk42d1f032003-10-15 23:53:47 +0000190#if defined(CONFIG_CONS_USE_EXTC)
191 m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
192 CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
193#else
194 m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
195#endif
196}
197
198void
199serial_putc(const char c)
200{
201 volatile scc_uart_t *up;
202 volatile cbd_t *tbdf;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000204
205 if (c == '\n')
206 serial_putc ('\r');
207
Kumar Galaaafeefb2007-11-28 00:36:33 -0600208 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
209 tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
wdenk42d1f032003-10-15 23:53:47 +0000210
211 /* Wait for last character to go.
212 */
213 while (tbdf->cbd_sc & BD_SC_READY)
214 ;
215
216 /* Load the character into the transmit buffer.
217 */
218 *(volatile char *)tbdf->cbd_bufaddr = c;
219 tbdf->cbd_datlen = 1;
220 tbdf->cbd_sc |= BD_SC_READY;
221}
222
223void
224serial_puts (const char *s)
225{
226 while (*s) {
227 serial_putc (*s++);
228 }
229}
230
231int
232serial_getc(void)
233{
234 volatile cbd_t *rbdf;
235 volatile scc_uart_t *up;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000237 unsigned char c;
238
Kumar Galaaafeefb2007-11-28 00:36:33 -0600239 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
240 rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
wdenk42d1f032003-10-15 23:53:47 +0000241
242 /* Wait for character to show up.
243 */
244 while (rbdf->cbd_sc & BD_SC_EMPTY)
245 ;
246
247 /* Grab the char and clear the buffer again.
248 */
249 c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
250 rbdf->cbd_sc |= BD_SC_EMPTY;
251
252 return (c);
253}
254
255int
256serial_tstc()
257{
258 volatile cbd_t *rbdf;
259 volatile scc_uart_t *up;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000261
Kumar Galaaafeefb2007-11-28 00:36:33 -0600262 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
263 rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
wdenk42d1f032003-10-15 23:53:47 +0000264
265 return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
266}
267
268#endif /* CONFIG_CONS_ON_SCC */