arch/arm/dts/imxrt1050-evk.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019
 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
 */

/dts-v1/;
#include "imxrt1050.dtsi"
#include "imxrt1050-pinfunc.h"

/ {
	model = "NXP IMXRT1050-evk board";
	compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";

	chosen {
		stdout-path = &lpuart1;
	};

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		mmc0 = &usdhc1;
		serial0 = &lpuart1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x2000000>;
	};
};

&lpuart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl_lpuart1: lpuart1grp {
		fsl,pins = <
			MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD	0xf1
			MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD	0xf1
		>;
	};

	pinctrl_usdhc0: usdhc0grp {
		fsl,pins = <
			MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B		0x1B000
			MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT	0xB069
			MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0	0x17061
		>;
	};
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc0>;
	pinctrl-1 = <&pinctrl_usdhc0>;
	pinctrl-2 = <&pinctrl_usdhc0>;
	pinctrl-3 = <&pinctrl_usdhc0>;
	cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
	status = "okay";
};